1.\" $OpenBSD: uperf.4,v 1.17 2015/02/15 22:26:45 bentley Exp $ 2.\" 3.\" Copyright (c) 2002 Jason L. Wright (jason@thought.net) 4.\" All rights reserved. 5.\" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Redistributions in binary form must reproduce the above copyright 12.\" notice, this list of conditions and the following disclaimer in the 13.\" documentation and/or other materials provided with the distribution. 14.\" 15.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17.\" WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18.\" DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19.\" INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20.\" (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21.\" SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23.\" STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24.\" ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25.\" POSSIBILITY OF SUCH DAMAGE. 26.\" 27.Dd $Mdocdate: February 15 2015 $ 28.Dt UPERF 4 sparc64 29.Os 30.Sh NAME 31.Nm uperf 32.Nd performance counters driver 33.Sh SYNOPSIS 34.Cd "uperf* at ebus?" 35.Cd "uperf* at sbus?" 36.Sh DESCRIPTION 37Some UltraSPARC host bridges provide performance counters on their host 38bridges. 39The counters are a part of the system controller chip (usc, dsc, or qsc). 40On PCI machines the system controller shows up as a device on the EBus, but 41on SBus machines the system controller exists in SBus space. 42The 43.Nm 44driver provides access to these counters via 45.Xr ioctl 2 . 46.Sh IOCTLS 47All of the ioctl calls supported by the 48.Nm 49driver take the following structure as an argument: 50.Bd -literal -offset indent 51struct uperf_io { 52 int cnt_flags; 53 int cnt_src0; 54 int cnt_src1; 55 u_int32_t cnt_val0; 56 u_int32_t cnt_val1; 57}; 58.Ed 59.Pp 60The 61.Fa cnt_flags 62field specifies which counters are being operated on and is a bit mask 63of 64.Fa UPERF_CNT0 65and/or 66.Fa UPERF_CNT1 . 67.Pp 68The 69.Fa cnt_src0 70and 71.Fa cnt_src1 72fields specify the source for the counter. 73Not all counters support monitoring all sources and specifying an invalid 74source for a counter to monitor will result in an error. 75The sources are specified below: 76.Pp 77.Bl -tag -width "UPERFSRC_TLBMISS" -offset indent -compact 78.It Em UPERFSRC_SYSCK 79system clock ticks 80.It Em UPERFSRC_PRALL 81all p-requests 82.It Em UPERFSRC_PRP0 83p-requests from processor 0 84.It Em UPERFSRC_PRU2S 85p-requests from the U2S 86.It Em UPERFSRC_UPA128 87cycles UPA 128 bit data is busy 88.It Em UPERFSRC_UPA64 89cycles UPA 64 bit data is busy 90.It Em UPERFSRC_PIOS 91cycles stalled during PIO 92.It Em UPERFSRC_MEMRI 93memory requests issued 94.It Em UPERFSRC_MCBUSY 95cycles memory controller is busy 96.It Em UPERFSRC_PXSH 97stall cycles due to pending transaction scoreboard hit 98.It Em UPERFSRC_P0CWMR 99coherent write miss requests, processor 0 100.It Em UPERFSRC_P1CWMR 101coherent write miss requests, processor 1 102.It Em UPERFSRC_CIT 103coherent intervention transactions 104.It Em UPERFSRC_U2SDAT 105data transactions on U2S 106.It Em UPERFSRC_CRXI 107coherent read transactions issued 108.It Em UPERFSRC_RDP0 109read requests, processor 0 110.It Em UPERFSRC_P0CRMR 111coherent read misses, processor 0 112.It Em UPERFSRC_P0PIO 113PIO accesses, processor 0 114.It Em UPERFSRC_MEMRC 115memory requests completed 116.It Em UPERFSRC_P1RR 117read requests, processor 1 118.It Em UPERFSRC_CRMP1 119coherent read misses, processor 1 120.It Em UPERFSRC_PIOP1 121PIO accesses, processor 1 122.It Em UPERFSRC_CWXI 123coherent write transactions issued 124.It Em UPERFSRC_RP0 125read requests, processor 0 126.It Em UPERFSRC_SDVRA 127streaming DVMA read transfers, PCI bus A 128.It Em UPERFSRC_SDVWA 129streaming DVMA write transfers, PCI bus A 130.It Em UPERFSRC_CDVRA 131consistent DVMA read transfers, PCI bus A 132.It Em UPERFSRC_CDVWA 133consistent DVMA write transfers, PCI bus A 134.It Em UPERFSRC_SBMA 135streaming buffer misses, PCI bus A 136.It Em UPERFSRC_DVA 137DVMA cycles, PCI bus A 138.It Em UPERFSRC_DVWA 139words transferred via DVMA, PCI bus A 140.It Em UPERFSRC_PIOA 141cycles consumed by PIO, bus A 142.It Em UPERFSRC_SDVRB 143streaming DVMA read transfers, PCI bus B 144.It Em UPERFSRC_SDVWB 145streaming DVMA write transfers, PCI bus B 146.It Em UPERFSRC_CDVRB 147consistent DVMA read transfers, PCI bus B 148.It Em UPERFSRC_CDVWB 149consistent DVMA write transfers, PCI bus B 150.It Em UPERFSRC_SBMB 151streaming buffer misses, PCI bus B 152.It Em UPERFSRC_DVB 153DVMA cycles, PCI bus B 154.It Em UPERFSRC_DVWB 155words transferred via DVMA, PCI bus B 156.It Em UPERFSRC_PIOB 157cycles consumed by PIO, bus B 158.It Em UPERFSRC_TLBMISS 159TLB misses 160.It Em UPERFSRC_NINTRS 161interrupts 162.It Em UPERFSRC_INACK 163interrupt NACKS on UPA 164.It Em UPERFSRC_PIOR 165PIO read transfers 166.It Em UPERFSRC_PIOW 167PIO write transfers 168.It Em UPERFSRC_MERGE 169merge buffer transactions 170.It Em UPERFSRC_TBLA 171DMA requests retried due to tablewalks, PCI bus A 172.It Em UPERFSRC_STCA 173DMA requests retries due to STC, PCI bus A 174.It Em UPERFSRC_TBLB 175DMA requests retries due to tablewalks, PCI bus B 176.It Em UPERFSRC_STCB 177DMA requests retries due to STC, PCI bus B 178.El 179.Pp 180The 181.Fa cnt_val0 182and 183.Fa cnt_val1 184contain the values fetched for the counters. 185Software using this interface should be prepared to handle the counters 186rolling over. 187.Pp 188The 189.Nm 190device responds to the following 191.Xr ioctl 2 192calls, which are defined in 193.In dev/sun/uperfio.h . 194.Bl -tag -width UPIO_GCNTSRC 195.It Dv UPIO_GCNTSRC 196.Pq Li "struct uperf_io" 197Retrieve the source the counters are monitoring. 198The 199.Fa cnt_flags 200is a bit mask for which of the counters is to be fetched. 201The result is returned in 202.Fa cnt_src0 203and/or 204.Fa cnt_src1 . 205.It Dv UPIO_SCNTSRC 206.Pq Li "struct uperf_io" 207Set the source the counters should monitor. 208This call also clears the current value of the counters that are set. 209The 210.Fa cnt_flags 211is a bit mask for which of the counters is to be set. 212The 213.Fa cnt_src0 214and/or 215.Fa cnt_src1 216fields specify the source to be set for the respective counter. 217.It Dv UPIO_CLRCNT 218.Pq Li "struct uperf_io" 219Clear the counters specified in 220.Fa cnt_flags . 221.It Dv UPIO_GETCNT 222.Pq Li "struct uperf_io" 223Retrieve the value for the counters specified in 224.Fa cnt_flags . 225The values are returned in 226.Fa cnt_val0 227and/or 228.Fa cnt_val1 . 229.El 230.Sh SEE ALSO 231.Xr ioctl 2 , 232.Xr ebus 4 , 233.Xr intro 4 , 234.Xr sbus 4 235.Sh HISTORY 236The 237.Nm 238driver was first supported in 239.Ox 3.1 . 240.Sh AUTHORS 241The driver was written by 242.An Jason Wright Aq Mt jason@thought.net . 243