1.\" $OpenBSD: pci_mapreg_map.9,v 1.1 2019/02/23 04:54:25 dlg Exp $ 2.\" 3.\" Copyright (c) 2019 David Gwynne <dlg@openbsd.org> 4.\" All rights reserved. 5.\" 6.\" Permission to use, copy, modify, and distribute this software for any 7.\" purpose with or without fee is hereby granted, provided that the above 8.\" copyright notice and this permission notice appear in all copies. 9.\" 10.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17.\" 18.Dd $Mdocdate: February 23 2019 $ 19.Dt PCI_MAPREG_MAP 9 20.Os 21.Sh NAME 22.Nm pci_mapreg_map , 23.Nm pci_mapreg_info , 24.Nm pci_mapreg_probe , 25.Nm pci_mapreg_type 26.\" .Nm pci_mem_find , 27.\" .Nm pci_io_find 28.Nd PCI register mappings 29.Sh SYNOPSIS 30.In dev/pci/pcivar.h 31.Ft int 32.Fo pci_mapreg_map 33.Fa "struct pci_attach_args *paa" 34.Fa "int reg" 35.Fa "pcireg_t type" 36.Fa "int flags" 37.Fa "bus_space_tag_t *tagp" 38.Fa "bus_space_handle_t *handlep" 39.Fa "bus_addr_t *basep" 40.Fa "bus_size_t *sizep" 41.Fa "bus_size_t maxsize" 42.Fc 43.Ft int 44.Fo pci_mapreg_info 45.Fa "pci_chipset_tag_t pc" 46.Fa "pcitag_t tag" 47.Fa "int reg" 48.Fa "pcireg_t type" 49.Fa "bus_addr_t *basep" 50.Fa "bus_size_t *sizep" 51.Fa "int *flagsp" 52.Fc 53.Ft int 54.Fo pci_mapreg_probe 55.Fa "pci_chipset_tag_t pc" 56.Fa "pcitag_t tag" 57.Fa "int reg" 58.Fa "pcireg_t *typep" 59.Fc 60.Ft pcireg_t 61.Fo pci_mapreg_type 62.Fa "pci_chipset_tag_t pc" 63.Fa "pcitag_t tag" 64.Fa "int reg" 65.Fc 66.\" .Ft int 67.\" .Fo pci_mem_find 68.\" .Fa "pci_chipset_tag_t pc" 69.\" .Fa "pcitag_t pcitag" 70.\" .Fa "int reg" 71.\" .Fa "bus_addr_t *basep" 72.\" .Fa "bus_size_t *sizep" 73.\" .Fa "int *cacheablep" 74.\" .Fc 75.\" .Ft int 76.\" .Fo pci_io_find 77.\" .Fa "pci_chipset_tag_t pc" 78.\" .Fa "pcitag_t pcitag" 79.\" .Fa "int reg" 80.\" .Fa "bus_addr_t *basep" 81.\" .Fa "bus_size_t *sizep" 82.\" .Fa "int *cacheablep" 83.\" .Fc 84.Sh DESCRIPTION 85These functions provide wrappers and helpers around 86.Xr bus_space 9 87mappings for device registers described by the Base Address Registers 88(BARs) in a PCI devices configuration space. 89.Pp 90.Nm pci_mapreg_map 91wraps a call to 92.Xr bus_space_map 9 93using information from the BAR referenced by 94.Fa reg 95for the device being attached with 96.Fa paa . 97Memory or I/O mappings are derived from the 98.Fa type 99argument. 100The size of the register mapping can be restricted by specifying a 101non-zero value in 102.Fa maxsize . 103The bus space tag and handle used for the mapping, as well 104as the base address and size of the mapping, will be provided 105to the caller via the optional 106.Fa tagp , 107.Fa handlep , 108.Fa basep , 109and 110.Fa sizep 111pointers. 112.Pp 113.Nm pci_mapreg_info 114provides bus space mapping information from the BAR referenced by 115.Fa reg . 116The 117.Fa type 118argument specifies whether the mapping provides Memory or I/O access. 119The base address, size, and bus space flags are optionally provided 120to the caller via the 121.Fa basep , 122.Fa sizep , 123and 124.Fa flagsp 125pointers. 126.Pp 127.Nm pci_mapreg_probe 128attempts to determine if the BAR referenced by 129.Fa reg 130describes a valid register mapping. 131.Pp 132.Nm pci_mapreg_type 133returns the type of register access for the registers at the BAR 134referenced by 135.Fa reg . 136.Sh RETURN VALUES 137.Nm pci_mapreg_map , 138.Nm pci_mapreg_info , 139and 140.Nm pci_mapreg_probe 141return 0 on success, or an 142.Xr errno 2 143style value on failure. 144.Pp 145.Nm pci_mapreg_type 146returns either 147.Dv PCI_MAPREG_TYPE_IO 148or 149.Dv PCI_MAPREG_TYPE_MEM . 150.Sh SEE ALSO 151.Xr pci 4 , 152.Xr bus_space 9 , 153.Xr pci_conf_read 9 154