1.\" $OpenBSD: pci_mapreg_map.9,v 1.2 2023/04/13 15:07:42 miod Exp $ 2.\" 3.\" Copyright (c) 2019 David Gwynne <dlg@openbsd.org> 4.\" All rights reserved. 5.\" 6.\" Permission to use, copy, modify, and distribute this software for any 7.\" purpose with or without fee is hereby granted, provided that the above 8.\" copyright notice and this permission notice appear in all copies. 9.\" 10.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17.\" 18.Dd $Mdocdate: April 13 2023 $ 19.Dt PCI_MAPREG_MAP 9 20.Os 21.Sh NAME 22.Nm pci_mapreg_map , 23.Nm pci_mapreg_info , 24.Nm pci_mapreg_probe , 25.Nm pci_mapreg_type 26.Nd PCI register mappings 27.Sh SYNOPSIS 28.In dev/pci/pcivar.h 29.Ft int 30.Fo pci_mapreg_map 31.Fa "struct pci_attach_args *paa" 32.Fa "int reg" 33.Fa "pcireg_t type" 34.Fa "int flags" 35.Fa "bus_space_tag_t *tagp" 36.Fa "bus_space_handle_t *handlep" 37.Fa "bus_addr_t *basep" 38.Fa "bus_size_t *sizep" 39.Fa "bus_size_t maxsize" 40.Fc 41.Ft int 42.Fo pci_mapreg_info 43.Fa "pci_chipset_tag_t pc" 44.Fa "pcitag_t tag" 45.Fa "int reg" 46.Fa "pcireg_t type" 47.Fa "bus_addr_t *basep" 48.Fa "bus_size_t *sizep" 49.Fa "int *flagsp" 50.Fc 51.Ft int 52.Fo pci_mapreg_probe 53.Fa "pci_chipset_tag_t pc" 54.Fa "pcitag_t tag" 55.Fa "int reg" 56.Fa "pcireg_t *typep" 57.Fc 58.Ft pcireg_t 59.Fo pci_mapreg_type 60.Fa "pci_chipset_tag_t pc" 61.Fa "pcitag_t tag" 62.Fa "int reg" 63.Fc 64.Sh DESCRIPTION 65These functions provide wrappers and helpers around 66.Xr bus_space 9 67mappings for device registers described by the Base Address Registers 68(BARs) in a PCI devices configuration space. 69.Pp 70.Nm pci_mapreg_map 71wraps a call to 72.Xr bus_space_map 9 73using information from the BAR referenced by 74.Fa reg 75for the device being attached with 76.Fa paa . 77Memory or I/O mappings are derived from the 78.Fa type 79argument. 80The size of the register mapping can be restricted by specifying a 81non-zero value in 82.Fa maxsize . 83The bus space tag and handle used for the mapping, as well 84as the base address and size of the mapping, will be provided 85to the caller via the optional 86.Fa tagp , 87.Fa handlep , 88.Fa basep , 89and 90.Fa sizep 91pointers. 92.Pp 93.Nm pci_mapreg_info 94provides bus space mapping information from the BAR referenced by 95.Fa reg . 96The 97.Fa type 98argument specifies whether the mapping provides Memory or I/O access. 99The base address, size, and bus space flags are optionally provided 100to the caller via the 101.Fa basep , 102.Fa sizep , 103and 104.Fa flagsp 105pointers. 106.Pp 107.Nm pci_mapreg_probe 108attempts to determine if the BAR referenced by 109.Fa reg 110describes a valid register mapping. 111.Pp 112.Nm pci_mapreg_type 113returns the type of register access for the registers at the BAR 114referenced by 115.Fa reg . 116.Sh RETURN VALUES 117.Nm pci_mapreg_map , 118.Nm pci_mapreg_info , 119and 120.Nm pci_mapreg_probe 121return 0 on success, or an 122.Xr errno 2 123style value on failure. 124.Pp 125.Nm pci_mapreg_type 126returns either 127.Dv PCI_MAPREG_TYPE_IO 128or 129.Dv PCI_MAPREG_TYPE_MEM . 130.Sh SEE ALSO 131.Xr pci 4 , 132.Xr bus_space 9 , 133.Xr pci_conf_read 9 134