1 /* $OpenBSD: mcbusreg.h,v 1.1 2007/03/16 21:22:27 robert Exp $ */ 2 /* $NetBSD: mcbusreg.h,v 1.3 1999/11/16 18:36:27 mjacob Exp $ */ 3 4 /* 5 * Copyright (c) 1998 by Matthew Jacob 6 * NASA AMES Research Center. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice immediately at the beginning of the file, without modification, 14 * this list of conditions, and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * 'Register' definitions for the MCBUS main 36 * system bus found on AlphaServer 4100 systems. 37 */ 38 39 /* 40 * Information gathered from: 41 * 42 * "Rawhide System Programmer's Manual, revision 1.4". 43 */ 44 45 /* 46 * There are 7 possible MC bus modules (architecture says 10, but 47 * the address map details say otherwise), 1 though 7. 48 * Their uses are defined as follows: 49 * 50 * MID Module 51 * ---- ------ 52 * 1 Memory 53 * 2 CPU 54 * 3 CPU 55 * 4 CPU, PCI 56 * 5 CPU, PCI 57 * 6 CPU, PCI 58 * 7 CPU, PCI 59 * 60 */ 61 #define MCBUS_MID_MAX 7 62 63 /* 64 * For this architecture, bit 39 of a 40 bit address controls whether 65 * you access I/O or Memory space. Further, there *could* be multiple 66 * MC busses (but only one specified for now). 67 */ 68 69 #define MCBUS_IOSPACE 0x0000008000000000L 70 #define MCBUS_GID_MASK 0x0000007000000000L 71 #define MCBUS_GID_SHIFT 36 72 #define MCBUS_MID_MASK 0x0000000E00000000L 73 #define MCBUS_MID_SHIFT 33 74 75 #define MAX_MC_BUS 8 76 77 /* 78 * This is something of a layering violation, but it makes probing cleaner. 79 */ 80 #define MCPCIA_PER_MCBUS 4 81 82 /* 83 * defaults for locators 84 */ 85 #define MCBUSCF_NLOCS 1 86 #define MCBUSCF_MID 0 87 #define MCBUSCF_MID_DEFAULT -1 88 89 /* the MCPCIA bridge CSR addresses, offset zero, is a good thing to probe for */ 90 #define MCPCIA_BRIDGE_ADDR(gid, mid) \ 91 (MCBUS_IOSPACE | 0x1E0000000LL | \ 92 (((unsigned long) gid) << MCBUS_GID_SHIFT) | \ 93 (((unsigned long) mid) << MCBUS_MID_SHIFT)) 94