1*625a31e9Sjason /* $OpenBSD: apecsreg.h,v 1.6 2001/02/16 08:23:39 jason Exp $ */ 213a8f984Sjason /* $NetBSD: apecsreg.h,v 1.5.2.2 1997/06/06 20:26:53 thorpej Exp $ */ 3df930be7Sderaadt 4df930be7Sderaadt /* 5df930be7Sderaadt * Copyright (c) 1995 Carnegie-Mellon University. 6df930be7Sderaadt * All rights reserved. 7df930be7Sderaadt * 8df930be7Sderaadt * Author: Chris G. Demetriou 9df930be7Sderaadt * 10df930be7Sderaadt * Permission to use, copy, modify and distribute this software and 11df930be7Sderaadt * its documentation is hereby granted, provided that both the copyright 12df930be7Sderaadt * notice and this permission notice appear in all copies of the 13df930be7Sderaadt * software, derivative works or modified versions, and any portions 14df930be7Sderaadt * thereof, and that both notices appear in supporting documentation. 15df930be7Sderaadt * 16df930be7Sderaadt * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17df930be7Sderaadt * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18df930be7Sderaadt * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19df930be7Sderaadt * 20df930be7Sderaadt * Carnegie Mellon requests users of this software to return to 21df930be7Sderaadt * 22df930be7Sderaadt * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23df930be7Sderaadt * School of Computer Science 24df930be7Sderaadt * Carnegie Mellon University 25df930be7Sderaadt * Pittsburgh PA 15213-3890 26df930be7Sderaadt * 27df930be7Sderaadt * any improvements or extensions that they make and grant Carnegie the 28df930be7Sderaadt * rights to redistribute these changes. 29df930be7Sderaadt */ 30df930be7Sderaadt 31df930be7Sderaadt /* 32df930be7Sderaadt * APECS Chipset registers and constants. 33df930be7Sderaadt * 34df930be7Sderaadt * Taken from ``DECchip 21071 and DECchip 21072 Core Logic Chipsets Data 35df930be7Sderaadt * Sheet'' (DEC order number EC-QAEMA-TE), pages 4-1 - 4-27, 10-21 - 10-38. 36df930be7Sderaadt */ 37df930be7Sderaadt 38*625a31e9Sjason #define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r)) 3934fbf6deSderaadt 40df930be7Sderaadt /* 41df930be7Sderaadt * Base addresses 42df930be7Sderaadt */ 43df930be7Sderaadt #define COMANCHE_BASE 0x180000000L /* 21071-CA Regs */ 44df930be7Sderaadt #define EPIC_BASE 0x1a0000000L /* 21071-DA Regs */ 45df930be7Sderaadt #define APECS_PCI_IACK 0x1b0000000L /* PCI Int. Ack. */ 46df930be7Sderaadt #define APECS_PCI_SIO 0x1c0000000L /* PCI Sp. I/O Space */ 47df930be7Sderaadt #define APECS_PCI_CONF 0x1e0000000L /* PCI Conf. Space */ 48df930be7Sderaadt #define APECS_PCI_SPARSE 0x200000000L /* PCI Sparse Space */ 49df930be7Sderaadt #define APECS_PCI_DENSE 0x300000000L /* PCI Dense Space */ 50df930be7Sderaadt 51df930be7Sderaadt 52df930be7Sderaadt /* 53df930be7Sderaadt * 21071-CA Registers 54df930be7Sderaadt */ 55df930be7Sderaadt 56df930be7Sderaadt /* 57df930be7Sderaadt * 21071-CA General Registers 58df930be7Sderaadt */ 59df930be7Sderaadt #define COMANCHE_GCR (COMANCHE_BASE + 0x0000) /* General Control */ 60df930be7Sderaadt #define COMANCHE_GCR_RSVD 0xc009 61df930be7Sderaadt #define COMANCHE_GCR_SYSARB 0x0006 62df930be7Sderaadt #define COMANCHE_GCR_WIDEMEM 0x0010 63df930be7Sderaadt #define COMANCHE_GCR_BC_EN 0x0020 64df930be7Sderaadt #define COMANCHE_GCR_BC_NOALLOC 0x0040 65df930be7Sderaadt #define COMANCHE_GCR_BC_LONGWR 0x0080 66df930be7Sderaadt #define COMANCHE_GCR_BC_IGNTAG 0x0100 67df930be7Sderaadt #define COMANCHE_GCR_BC_FRCTAG 0x0200 68df930be7Sderaadt #define COMANCHE_GCR_BC_FRCD 0x0400 69df930be7Sderaadt #define COMANCHE_GCR_BC_FRCV 0x0800 70df930be7Sderaadt #define COMANCHE_GCR_BC_FRCP 0x1000 71df930be7Sderaadt #define COMANCHE_GCR_BC_BADAP 0x2000 72df930be7Sderaadt 73df930be7Sderaadt #define COMANCHE_RSVD (COMANCHE_BASE + 0x0020) /* Reserved */ 74df930be7Sderaadt 75df930be7Sderaadt #define COMANCHE_ED (COMANCHE_BASE + 0x0040) /* Err & Diag Status */ 76df930be7Sderaadt #define COMANCHE_ED_LOSTERR 0x0001 77df930be7Sderaadt #define COMANCHE_ED_BC_TAPERR 0x0002 78df930be7Sderaadt #define COMANCHE_ED_BC_TCPERR 0x0004 79df930be7Sderaadt #define COMANCHE_ED_NXMERR 0x0008 80df930be7Sderaadt #define COMANCHE_ED_DMACAUSE 0x0010 81df930be7Sderaadt #define COMANCHE_ED_VICCAUSE 0x0020 82df930be7Sderaadt #define COMANCHE_ED_CREQCAUSE 0x01c0 83df930be7Sderaadt #define COMANCHE_ED_RSVD 0x1e00 84df930be7Sderaadt #define COMANCHE_ED_PASS2 0x2000 85df930be7Sderaadt #define COMANCHE_ED_IDXLLOCK 0x4000 86df930be7Sderaadt #define COMANCHE_ED_WRPEND 0x8000 87df930be7Sderaadt 88df930be7Sderaadt #define COMANCHE_TAGENB (COMANCHE_BASE + 0x0060) /* Tag Enable */ 89df930be7Sderaadt #define COMANCHE_TAGENB_RSVD 0x0001 90df930be7Sderaadt 91df930be7Sderaadt #define COMANCHE_TAGENB_C_4G 0x0000 92df930be7Sderaadt #define COMANCHE_TAGENB_C_2G 0x8000 93df930be7Sderaadt #define COMANCHE_TAGENB_C_1G 0xc000 94df930be7Sderaadt #define COMANCHE_TAGENB_C_512M 0xe000 95df930be7Sderaadt #define COMANCHE_TAGENB_C_256M 0xf000 96df930be7Sderaadt #define COMANCHE_TAGENB_C_128M 0xf800 97df930be7Sderaadt #define COMANCHE_TAGENB_C_64M 0xfc00 98df930be7Sderaadt #define COMANCHE_TAGENB_C_32M 0xfe00 99df930be7Sderaadt #define COMANCHE_TAGENB_C_16M 0xff00 100df930be7Sderaadt #define COMANCHE_TAGENB_C_8M 0xff80 101df930be7Sderaadt #define COMANCHE_TAGENB_C_4M 0xffc0 102df930be7Sderaadt #define COMANCHE_TAGENB_C_2M 0xffe0 103df930be7Sderaadt #define COMANCHE_TAGENB_C_1M 0xfff0 104df930be7Sderaadt #define COMANCHE_TAGENB_C_512K 0xfff8 105df930be7Sderaadt #define COMANCHE_TAGENB_C_256K 0xfffc 106df930be7Sderaadt #define COMANCHE_TAGENB_C_128K 0xfffe 107df930be7Sderaadt 108df930be7Sderaadt #define COMANCHE_TAGENB_M_4G 0xffff 109df930be7Sderaadt #define COMANCHE_TAGENB_M_2G 0x7fff 110df930be7Sderaadt #define COMANCHE_TAGENB_M_1G 0x3fff 111df930be7Sderaadt #define COMANCHE_TAGENB_M_512M 0x1fff 112df930be7Sderaadt #define COMANCHE_TAGENB_M_256M 0x0fff 113df930be7Sderaadt #define COMANCHE_TAGENB_M_128M 0x07ff 114df930be7Sderaadt #define COMANCHE_TAGENB_M_64M 0x03ff 115df930be7Sderaadt #define COMANCHE_TAGENB_M_32M 0x01ff 116df930be7Sderaadt #define COMANCHE_TAGENB_M_16M 0x00ff 117df930be7Sderaadt #define COMANCHE_TAGENB_M_8M 0x007f 118df930be7Sderaadt #define COMANCHE_TAGENB_M_4M 0x003f 119df930be7Sderaadt #define COMANCHE_TAGENB_M_2M 0x001f 120df930be7Sderaadt #define COMANCHE_TAGENB_M_1M 0x000e 121df930be7Sderaadt #define COMANCHE_TAGENB_M_512K 0x0006 122df930be7Sderaadt #define COMANCHE_TAGENB_M_256K 0x0002 123df930be7Sderaadt #define COMANCHE_TAGENB_M_128K 0x0000 124df930be7Sderaadt 125df930be7Sderaadt #define COMANCHE_ERR_LO (COMANCHE_BASE + 0x0080) /* Error Low Address */ 126df930be7Sderaadt 127df930be7Sderaadt #define COMANCHE_ERR_HI (COMANCHE_BASE + 0x00a0) /* Error High Address */ 128df930be7Sderaadt #define COMANCHE_ERR_HI_RSVD 0xe000 129df930be7Sderaadt 130df930be7Sderaadt #define COMANCHE_LCK_LO (COMANCHE_BASE + 0x00c0) /* LDx_L Low Address */ 131df930be7Sderaadt 132df930be7Sderaadt #define COMANCHE_LCK_HI (COMANCHE_BASE + 0x00e0) /* LDx_L High Address */ 133df930be7Sderaadt #define COMANCHE_LOCK_HI_RSVD 0xe000 134df930be7Sderaadt 135df930be7Sderaadt /* 136df930be7Sderaadt * 21071-CA Memory Registers 137df930be7Sderaadt */ 138df930be7Sderaadt #define COMANCHE_GTIM (COMANCHE_BASE + 0x0200) /* Global Timing */ 139df930be7Sderaadt #define COMANCHE_LOCK_HI_RSVD 0xe000 140df930be7Sderaadt 141df930be7Sderaadt #define COMANCHE_RTIM (COMANCHE_BASE + 0x0220) /* Refresh Timing */ 142df930be7Sderaadt 143df930be7Sderaadt #define COMANCHE_VFP (COMANCHE_BASE + 0x0240) /* Video Frame Ptr. */ 144df930be7Sderaadt #define COMANCHE_VFP_COL 0x001f 145df930be7Sderaadt #define COMANCHE_VFP_ROW 0x3fe0 146df930be7Sderaadt #define COMANCHE_VFP_SUBBANK 0x4000 147df930be7Sderaadt #define COMANCHE_VFP_RSVD 0x8000 148df930be7Sderaadt 149df930be7Sderaadt #define COMANCHE_PD_LO (COMANCHE_BASE + 0x0260) /* Pres Detect Low */ 150df930be7Sderaadt 151df930be7Sderaadt #define COMANCHE_PD_HI (COMANCHE_BASE + 0x0280) /* Pres Detect High */ 152df930be7Sderaadt 153df930be7Sderaadt /* 154df930be7Sderaadt * 21071-CA Memory banks' Base Address Register format 155df930be7Sderaadt */ 156df930be7Sderaadt #define COMANCHE_B0_BAR (COMANCHE_BASE + 0x0800) /* Bank 0 BA */ 157df930be7Sderaadt #define COMANCHE_B1_BAR (COMANCHE_BASE + 0x0820) /* Bank 1 BA */ 158df930be7Sderaadt #define COMANCHE_B2_BAR (COMANCHE_BASE + 0x0840) /* Bank 2 BA */ 159df930be7Sderaadt #define COMANCHE_B3_BAR (COMANCHE_BASE + 0x0860) /* Bank 3 BA */ 160df930be7Sderaadt #define COMANCHE_B4_BAR (COMANCHE_BASE + 0x0880) /* Bank 4 BA */ 161df930be7Sderaadt #define COMANCHE_B5_BAR (COMANCHE_BASE + 0x08a0) /* Bank 5 BA */ 162df930be7Sderaadt #define COMANCHE_B6_BAR (COMANCHE_BASE + 0x08c0) /* Bank 6 BA */ 163df930be7Sderaadt #define COMANCHE_B7_BAR (COMANCHE_BASE + 0x08e0) /* Bank 7 BA */ 164df930be7Sderaadt #define COMANCHE_B8_BAR (COMANCHE_BASE + 0x0900) /* Bank 8 BA */ 165df930be7Sderaadt #define COMANCHE_BAR_RSVD 0x001f 166df930be7Sderaadt 167df930be7Sderaadt /* 168df930be7Sderaadt * 21071-CA Memory banks' Configuration Register format 169df930be7Sderaadt */ 170df930be7Sderaadt #define COMANCHE_B0_CR (COMANCHE_BASE + 0x0a00) /* Bank 0 Config */ 171df930be7Sderaadt #define COMANCHE_B1_CR (COMANCHE_BASE + 0x0a20) /* Bank 1 Config */ 172df930be7Sderaadt #define COMANCHE_B2_CR (COMANCHE_BASE + 0x0a40) /* Bank 2 Config */ 173df930be7Sderaadt #define COMANCHE_B3_CR (COMANCHE_BASE + 0x0a60) /* Bank 3 Config */ 174df930be7Sderaadt #define COMANCHE_B4_CR (COMANCHE_BASE + 0x0a80) /* Bank 4 Config */ 175df930be7Sderaadt #define COMANCHE_B5_CR (COMANCHE_BASE + 0x0aa0) /* Bank 5 Config */ 176df930be7Sderaadt #define COMANCHE_B6_CR (COMANCHE_BASE + 0x0ac0) /* Bank 6 Config */ 177df930be7Sderaadt #define COMANCHE_B7_CR (COMANCHE_BASE + 0x0ae0) /* Bank 7 Config */ 178df930be7Sderaadt #define COMANCHE_B8_CR (COMANCHE_BASE + 0x0b00) /* Bank 8 Config */ 179df930be7Sderaadt #define COMANCHE_CR_VALID 0x0001 180df930be7Sderaadt #define COMANCHE_CR_SIZE 0x001e 181df930be7Sderaadt #define COMANCHE_CR_SUBENA 0x0020 182df930be7Sderaadt #define COMANCHE_CR_COLSEL 0x01c0 183df930be7Sderaadt #define COMANCHE_CR_S0_RSVD 0xfe00 184df930be7Sderaadt #define COMANCHE_CR_S8_CHECK 0x0200 185df930be7Sderaadt #define COMANCHE_CR_S8_RSVD 0xfc00 186df930be7Sderaadt 187df930be7Sderaadt /* 188df930be7Sderaadt * 21071-CA Memory banks' Timing Register A format 189df930be7Sderaadt */ 190df930be7Sderaadt #define COMANCHE_B0_TRA (COMANCHE_BASE + 0x0c00) /* Bank 0 Timing A */ 191df930be7Sderaadt #define COMANCHE_B1_TRA (COMANCHE_BASE + 0x0c20) /* Bank 1 Timing A */ 192df930be7Sderaadt #define COMANCHE_B2_TRA (COMANCHE_BASE + 0x0c40) /* Bank 2 Timing A */ 193df930be7Sderaadt #define COMANCHE_B3_TRA (COMANCHE_BASE + 0x0c60) /* Bank 3 Timing A */ 194df930be7Sderaadt #define COMANCHE_B4_TRA (COMANCHE_BASE + 0x0c80) /* Bank 4 Timing A */ 195df930be7Sderaadt #define COMANCHE_B5_TRA (COMANCHE_BASE + 0x0ca0) /* Bank 5 Timing A */ 196df930be7Sderaadt #define COMANCHE_B6_TRA (COMANCHE_BASE + 0x0cc0) /* Bank 6 Timing A */ 197df930be7Sderaadt #define COMANCHE_B7_TRA (COMANCHE_BASE + 0x0ce0) /* Bank 7 Timing A */ 198df930be7Sderaadt #define COMANCHE_B8_TRA (COMANCHE_BASE + 0x0d00) /* Bank 8 Timing A */ 199df930be7Sderaadt #define COMANCHE_TRA_ROWSETUP 0x0003 200df930be7Sderaadt #define COMANCHE_TRA_ROWHOLD 0x000c 201df930be7Sderaadt #define COMANCHE_TRA_COLSETUP 0x0070 202df930be7Sderaadt #define COMANCHE_TRA_COLHOLD 0x0180 203df930be7Sderaadt #define COMANCHE_TRA_RDLYROW 0x0e00 204df930be7Sderaadt #define COMANCHE_TRA_RDLYCOL 0x7000 205df930be7Sderaadt #define COMANCHE_TRA_RSVD 0x8000 206df930be7Sderaadt 207df930be7Sderaadt /* 208df930be7Sderaadt * 21071-CA Memory banks' Timing Register B format 209df930be7Sderaadt */ 210df930be7Sderaadt #define COMANCHE_B0_TRB (COMANCHE_BASE + 0x0e00) /* Bank 0 Timing B */ 211df930be7Sderaadt #define COMANCHE_B1_TRB (COMANCHE_BASE + 0x0e20) /* Bank 1 Timing B */ 212df930be7Sderaadt #define COMANCHE_B2_TRB (COMANCHE_BASE + 0x0e40) /* Bank 2 Timing B */ 213df930be7Sderaadt #define COMANCHE_B3_TRB (COMANCHE_BASE + 0x0e60) /* Bank 3 Timing B */ 214df930be7Sderaadt #define COMANCHE_B4_TRB (COMANCHE_BASE + 0x0e80) /* Bank 4 Timing B */ 215df930be7Sderaadt #define COMANCHE_B5_TRB (COMANCHE_BASE + 0x0ea0) /* Bank 5 Timing B */ 216df930be7Sderaadt #define COMANCHE_B6_TRB (COMANCHE_BASE + 0x0ec0) /* Bank 6 Timing B */ 217df930be7Sderaadt #define COMANCHE_B7_TRB (COMANCHE_BASE + 0x0ee0) /* Bank 7 Timing B */ 218df930be7Sderaadt #define COMANCHE_B8_TRB (COMANCHE_BASE + 0x0f00) /* Bank 8 Timing B */ 219df930be7Sderaadt #define COMANCHE_TRB_RTCAS 0x0007 220df930be7Sderaadt #define COMANCHE_TRB_WTCAS 0x0038 221df930be7Sderaadt #define COMANCHE_TRB_TCP 0x00c0 222df930be7Sderaadt #define COMANCHE_TRB_WHOLD0ROW 0x0700 223df930be7Sderaadt #define COMANCHE_TRB_WHOLD0COL 0x3800 224df930be7Sderaadt #define COMANCHE_TRB_RSVD 0xc000 225df930be7Sderaadt 226df930be7Sderaadt 227df930be7Sderaadt /* 228df930be7Sderaadt * 21071-DA Registers 229df930be7Sderaadt */ 230df930be7Sderaadt #define EPIC_DCSR (EPIC_BASE + 0x0000) /* Diagnostic CSR */ 231df930be7Sderaadt #define EPIC_DCSR_TENB 0x00000001 232df930be7Sderaadt #define EPIC_DCSR_RSVD 0x7fc00082 233df930be7Sderaadt #define EPIC_DCSR_PENB 0x00000004 234df930be7Sderaadt #define EPIC_DCSR_DCEI 0x00000008 235df930be7Sderaadt #define EPIC_DCSR_DPEC 0x00000010 236df930be7Sderaadt #define EPIC_DCSR_IORT 0x00000020 237df930be7Sderaadt #define EPIC_DCSR_LOST 0x00000040 238df930be7Sderaadt #define EPIC_DCSR_DDPE 0x00000100 239df930be7Sderaadt #define EPIC_DCSR_IOPE 0x00000200 240df930be7Sderaadt #define EPIC_DCSR_TABT 0x00000400 241df930be7Sderaadt #define EPIC_DCSR_NDEV 0x00000800 242df930be7Sderaadt #define EPIC_DCSR_CMRD 0x00001000 243df930be7Sderaadt #define EPIC_DCSR_UMRD 0x00002000 244df930be7Sderaadt #define EPIC_DCSR_IPTL 0x00004000 245df930be7Sderaadt #define EPIC_DCSR_MERR 0x00008000 246df930be7Sderaadt #define EPIC_DCSR_DBYP 0x00030000 247df930be7Sderaadt #define EPIC_DCSR_PCMD 0x003c0000 248df930be7Sderaadt #define EPIC_DCSR_PASS2 0x80000000 249df930be7Sderaadt 250df930be7Sderaadt #define EPIC_PEAR (EPIC_BASE + 0x0020) /* PCI Err Addr. */ 251df930be7Sderaadt 252df930be7Sderaadt #define EPIC_SEAR (EPIC_BASE + 0x0040) /* sysBus Err Addr. */ 253df930be7Sderaadt #define EPIC_SEAR_RSVD 0x0000000f 254df930be7Sderaadt #define EPIC_SEAR_SYS_ERR 0xfffffff0 255df930be7Sderaadt 256df930be7Sderaadt #define EPIC_DUMMY_1 (EPIC_BASE + 0x0060) /* Dummy 1 */ 257df930be7Sderaadt #define EPIC_DUMMY_2 (EPIC_BASE + 0x0080) /* Dummy 2 */ 258df930be7Sderaadt #define EPIC_DUMMY_3 (EPIC_BASE + 0x00a0) /* Dummy 3 */ 259df930be7Sderaadt 260df930be7Sderaadt #define EPIC_TBASE_1 (EPIC_BASE + 0x00c0) /* Trans. Base 1 */ 261df930be7Sderaadt #define EPIC_TBASE_2 (EPIC_BASE + 0x00e0) /* Trans. Base 2 */ 262df930be7Sderaadt #define EPIC_TBASE_RSVD 0x000001ff 263df930be7Sderaadt #define EPIC_TBASE_T_BASE 0xfffffe00 26413a8f984Sjason #define EPIC_TBASE_SHIFT 1 265df930be7Sderaadt 266df930be7Sderaadt #define EPIC_PCI_BASE_1 (EPIC_BASE + 0x0100) /* PCI Base 1 */ 267df930be7Sderaadt #define EPIC_PCI_BASE_2 (EPIC_BASE + 0x0120) /* PCI Base 2 */ 268df930be7Sderaadt #define EPIC_PCI_BASE_RSVD 0x0003ffff 269df930be7Sderaadt #define EPIC_PCI_BASE_SGEN 0x00040000 270df930be7Sderaadt #define EPIC_PCI_BASE_WENB 0x00080000 271df930be7Sderaadt #define EPIC_PCI_BASE_PCI_BASE 0xfff00000 272df930be7Sderaadt 273df930be7Sderaadt #define EPIC_PCI_MASK_1 (EPIC_BASE + 0x0140) /* PCI Mask 1 */ 27413a8f984Sjason #define EPIC_PCI_MASK_2 (EPIC_BASE + 0x0160) /* PCI Mask 2 */ 275df930be7Sderaadt #define EPIC_PCI_MASK_RSVD 0x000fffff 276df930be7Sderaadt #define EPIC_PCI_MASK_PCI_MASK 0xfff00000 27713a8f984Sjason #define EPIC_PCI_MASK_1M 0x00000000 27813a8f984Sjason #define EPIC_PCI_MASK_2M 0x00100000 27913a8f984Sjason #define EPIC_PCI_MASK_4M 0x00300000 28013a8f984Sjason #define EPIC_PCI_MASK_8M 0x00700000 28113a8f984Sjason #define EPIC_PCI_MASK_16M 0x00f00000 28213a8f984Sjason #define EPIC_PCI_MASK_32M 0x01f00000 28313a8f984Sjason #define EPIC_PCI_MASK_64M 0x03f00000 28413a8f984Sjason #define EPIC_PCI_MASK_128M 0x07f00000 28513a8f984Sjason #define EPIC_PCI_MASK_256M 0x0ff00000 28613a8f984Sjason #define EPIC_PCI_MASK_512M 0x1ff00000 28713a8f984Sjason #define EPIC_PCI_MASK_1G 0x3ff00000 28813a8f984Sjason #define EPIC_PCI_MASK_2G 0x7ff00000 28913a8f984Sjason #define EPIC_PCI_MASK_4G 0xfff00000 290df930be7Sderaadt 291df930be7Sderaadt #define EPIC_HAXR0 (EPIC_BASE + 0x0180) /* Host Addr Extn 0 */ 292df930be7Sderaadt 293df930be7Sderaadt #define EPIC_HAXR1 (EPIC_BASE + 0x01a0) /* Host Addr Extn 1 */ 294df930be7Sderaadt #define EPIC_HAXR1_RSVD 0x07ffffff 295df930be7Sderaadt #define EPIC_HAXR1_EADDR 0xf8000000 296df930be7Sderaadt 297df930be7Sderaadt #define EPIC_HAXR2 (EPIC_BASE + 0x01c0) /* Host Addr Extn 2 */ 29834fbf6deSderaadt #define EPIC_HAXR2_CONF_TYPE 0x00000003 29934fbf6deSderaadt #define EPIC_HAXR2_CONF_TYPO0 0x00000000 30034fbf6deSderaadt #define EPIC_HAXR2_CONF_TYPE1 0x00000001 301df930be7Sderaadt #define EPIC_HAXR2_RSVD 0x00fffffc 302df930be7Sderaadt #define EPIC_HAXR2_EADDR 0xff000000 303df930be7Sderaadt 304df930be7Sderaadt #define EPIC_PMLT (EPIC_BASE + 0x01e0) /* PCI Mstr Lat Tmr */ 305df930be7Sderaadt #define EPIC_PMLT_PMLC 0x000000ff 306df930be7Sderaadt #define EPIC_PMLT_RSVD 0xffffff00 307df930be7Sderaadt 308df930be7Sderaadt #define EPIC_TLB_TAG_0 (EPIC_BASE + 0x0200) /* TLB Tag 0 */ 309df930be7Sderaadt #define EPIC_TLB_TAG_1 (EPIC_BASE + 0x0220) /* TLB Tag 1 */ 310df930be7Sderaadt #define EPIC_TLB_TAG_2 (EPIC_BASE + 0x0240) /* TLB Tag 2 */ 311df930be7Sderaadt #define EPIC_TLB_TAG_3 (EPIC_BASE + 0x0260) /* TLB Tag 3 */ 312df930be7Sderaadt #define EPIC_TLB_TAG_4 (EPIC_BASE + 0x0280) /* TLB Tag 4 */ 313df930be7Sderaadt #define EPIC_TLB_TAG_5 (EPIC_BASE + 0x02a0) /* TLB Tag 5 */ 314df930be7Sderaadt #define EPIC_TLB_TAG_6 (EPIC_BASE + 0x02c0) /* TLB Tag 6 */ 315df930be7Sderaadt #define EPIC_TLB_TAG_7 (EPIC_BASE + 0x02e0) /* TLB Tag 7 */ 316df930be7Sderaadt #define EPIC_TLB_TAG_RSVD 0x00000fff 317df930be7Sderaadt #define EPIC_TLB_TAG_EVAL 0x00001000 318df930be7Sderaadt #define EPIC_TLB_TAG_PCI_PAGE 0xffffe000 319df930be7Sderaadt 320df930be7Sderaadt #define EPIC_TLB_DATA_0 (EPIC_BASE + 0x0300) /* TLB Data 0 */ 321df930be7Sderaadt #define EPIC_TLB_DATA_1 (EPIC_BASE + 0x0320) /* TLB Data 1 */ 322df930be7Sderaadt #define EPIC_TLB_DATA_2 (EPIC_BASE + 0x0340) /* TLB Data 2 */ 323df930be7Sderaadt #define EPIC_TLB_DATA_3 (EPIC_BASE + 0x0360) /* TLB Data 3 */ 324df930be7Sderaadt #define EPIC_TLB_DATA_4 (EPIC_BASE + 0x0380) /* TLB Data 4 */ 325df930be7Sderaadt #define EPIC_TLB_DATA_5 (EPIC_BASE + 0x03a0) /* TLB Data 5 */ 326df930be7Sderaadt #define EPIC_TLB_DATA_6 (EPIC_BASE + 0x03c0) /* TLB Data 6 */ 327df930be7Sderaadt #define EPIC_TLB_DATA_7 (EPIC_BASE + 0x03e0) /* TLB Data 7 */ 328df930be7Sderaadt #define EPIC_TLB_DATA_RSVD 0xffe00001 329df930be7Sderaadt #define EPIC_TLB_DATA_CPU_PAGE 0x001ffffe 330df930be7Sderaadt 331df930be7Sderaadt #define EPIC_TBIA (EPIC_BASE + 0x0400) /* TLB Invl All */ 332df930be7Sderaadt 333df930be7Sderaadt /* 334df930be7Sderaadt * EPIC Scatter-Gather Map Entries 335df930be7Sderaadt */ 336df930be7Sderaadt 337df930be7Sderaadt struct sgmapent { 338df930be7Sderaadt u_int64_t val; 339df930be7Sderaadt }; 340df930be7Sderaadt #define SGMAPENT_EVAL 0x0000000000000001L 341df930be7Sderaadt #define SGMAPENT_PFN 0x00000000001ffffeL 342df930be7Sderaadt #define SGMAPENT_RSVD 0xffffffffffe00000L 343df930be7Sderaadt 344df930be7Sderaadt #define SGMAP_MAKEENTRY(pfn) (SGMAPENT_EVAL | ((pfn) << 1)) 345