1 /* $OpenBSD: cia_dma.c,v 1.10 2009/02/01 14:34:00 miod Exp $ */ 2 /* $NetBSD: cia_dma.c,v 1.16 2000/06/29 08:58:46 mrg Exp $ */ 3 4 /*- 5 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * XXX - We should define this before including bus.h, but since other stuff 36 * pulls in bus.h we must do this here. 37 */ 38 #define _ALPHA_BUS_DMA_PRIVATE 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 46 #include <uvm/uvm_extern.h> 47 48 #include <machine/bus.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 #include <alpha/pci/ciareg.h> 53 #include <alpha/pci/ciavar.h> 54 55 bus_dma_tag_t cia_dma_get_tag(bus_dma_tag_t, alpha_bus_t); 56 57 int cia_bus_dmamap_create_direct(bus_dma_tag_t, bus_size_t, int, 58 bus_size_t, bus_size_t, int, bus_dmamap_t *); 59 60 int cia_bus_dmamap_load_sgmap(bus_dma_tag_t, bus_dmamap_t, void *, 61 bus_size_t, struct proc *, int); 62 63 int cia_bus_dmamap_load_mbuf_sgmap(bus_dma_tag_t, bus_dmamap_t, 64 struct mbuf *, int); 65 66 int cia_bus_dmamap_load_uio_sgmap(bus_dma_tag_t, bus_dmamap_t, 67 struct uio *, int); 68 69 int cia_bus_dmamap_load_raw_sgmap(bus_dma_tag_t, bus_dmamap_t, 70 bus_dma_segment_t *, int, bus_size_t, int); 71 72 void cia_bus_dmamap_unload_sgmap(bus_dma_tag_t, bus_dmamap_t); 73 74 /* 75 * Direct-mapped window: 1G at 1G 76 */ 77 #define CIA_DIRECT_MAPPED_BASE (1*1024*1024*1024) 78 #define CIA_DIRECT_MAPPED_SIZE (1*1024*1024*1024) 79 80 /* 81 * SGMAP window: 8M at 8M 82 */ 83 #define CIA_SGMAP_MAPPED_BASE (8*1024*1024) 84 #define CIA_SGMAP_MAPPED_SIZE (8*1024*1024) 85 86 void cia_tlb_invalidate(void); 87 void cia_broken_pyxis_tlb_invalidate(void); 88 89 void (*cia_tlb_invalidate_fn)(void); 90 91 #define CIA_TLB_INVALIDATE() (*cia_tlb_invalidate_fn)() 92 93 struct alpha_sgmap cia_pyxis_bug_sgmap; 94 #define CIA_PYXIS_BUG_BASE (128*1024*1024) 95 #define CIA_PYXIS_BUG_SIZE (2*1024*1024) 96 97 void 98 cia_dma_init(ccp) 99 struct cia_config *ccp; 100 { 101 bus_addr_t tbase; 102 bus_dma_tag_t t; 103 104 /* 105 * Initialize the DMA tag used for direct-mapped DMA. 106 */ 107 t = &ccp->cc_dmat_direct; 108 t->_cookie = ccp; 109 t->_wbase = CIA_DIRECT_MAPPED_BASE; 110 t->_wsize = CIA_DIRECT_MAPPED_SIZE; 111 t->_next_window = &ccp->cc_dmat_sgmap; 112 t->_boundary = 0; 113 t->_sgmap = NULL; 114 t->_get_tag = cia_dma_get_tag; 115 t->_dmamap_create = cia_bus_dmamap_create_direct; 116 t->_dmamap_destroy = _bus_dmamap_destroy; 117 t->_dmamap_load = _bus_dmamap_load_direct; 118 t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf_direct; 119 t->_dmamap_load_uio = _bus_dmamap_load_uio_direct; 120 t->_dmamap_load_raw = _bus_dmamap_load_raw_direct; 121 t->_dmamap_unload = _bus_dmamap_unload; 122 t->_dmamap_sync = _bus_dmamap_sync; 123 124 t->_dmamem_alloc = _bus_dmamem_alloc; 125 t->_dmamem_free = _bus_dmamem_free; 126 t->_dmamem_map = _bus_dmamem_map; 127 t->_dmamem_unmap = _bus_dmamem_unmap; 128 t->_dmamem_mmap = _bus_dmamem_mmap; 129 130 /* 131 * Initialize the DMA tag used for sgmap-mapped DMA. 132 */ 133 t = &ccp->cc_dmat_sgmap; 134 t->_cookie = ccp; 135 t->_wbase = CIA_SGMAP_MAPPED_BASE; 136 t->_wsize = CIA_SGMAP_MAPPED_SIZE; 137 t->_next_window = NULL; 138 t->_boundary = 0; 139 t->_sgmap = &ccp->cc_sgmap; 140 t->_get_tag = cia_dma_get_tag; 141 t->_dmamap_create = alpha_sgmap_dmamap_create; 142 t->_dmamap_destroy = alpha_sgmap_dmamap_destroy; 143 t->_dmamap_load = cia_bus_dmamap_load_sgmap; 144 t->_dmamap_load_mbuf = cia_bus_dmamap_load_mbuf_sgmap; 145 t->_dmamap_load_uio = cia_bus_dmamap_load_uio_sgmap; 146 t->_dmamap_load_raw = cia_bus_dmamap_load_raw_sgmap; 147 t->_dmamap_unload = cia_bus_dmamap_unload_sgmap; 148 t->_dmamap_sync = _bus_dmamap_sync; 149 150 t->_dmamem_alloc = _bus_dmamem_alloc; 151 t->_dmamem_free = _bus_dmamem_free; 152 t->_dmamem_map = _bus_dmamem_map; 153 t->_dmamem_unmap = _bus_dmamem_unmap; 154 t->_dmamem_mmap = _bus_dmamem_mmap; 155 156 /* 157 * The firmware has set up window 1 as a 1G direct-mapped DMA 158 * window beginning at 1G. We leave it alone. Leave window 159 * 0 alone until we reconfigure it for SGMAP-mapped DMA. 160 * Windows 2 and 3 are already disabled. 161 */ 162 163 /* 164 * Initialize the SGMAP. Must align page table to 32k 165 * (hardware bug?). 166 */ 167 alpha_sgmap_init(t, &ccp->cc_sgmap, "cia_sgmap", 168 CIA_SGMAP_MAPPED_BASE, 0, CIA_SGMAP_MAPPED_SIZE, 169 sizeof(u_int64_t), NULL, (32*1024)); 170 171 /* 172 * Set up window 0 as an 8MB SGMAP-mapped window 173 * starting at 8MB. 174 */ 175 REGVAL(CIA_PCI_W0BASE) = CIA_SGMAP_MAPPED_BASE | 176 CIA_PCI_WnBASE_SG_EN | CIA_PCI_WnBASE_W_EN; 177 alpha_mb(); 178 179 REGVAL(CIA_PCI_W0MASK) = CIA_PCI_WnMASK_8M; 180 alpha_mb(); 181 182 tbase = ccp->cc_sgmap.aps_ptpa >> CIA_PCI_TnBASE_SHIFT; 183 if ((tbase & CIA_PCI_TnBASE_MASK) != tbase) 184 panic("cia_dma_init: bad page table address"); 185 REGVAL(CIA_PCI_T0BASE) = tbase; 186 alpha_mb(); 187 188 /* 189 * Pass 1 and 2 (i.e. revision <= 1) of the Pyxis have a 190 * broken scatter/gather TLB; it cannot be invalidated. To 191 * work around this problem, we configure window 2 as an SG 192 * 2M window at 128M, which we use in DMA loopback mode to 193 * read a spill page. This works by causing TLB misses, 194 * causing the old entries to be purged to make room for 195 * the new entries coming in for the spill page. 196 */ 197 if ((ccp->cc_flags & CCF_ISPYXIS) != 0 && ccp->cc_rev <= 1) { 198 u_int64_t *page_table; 199 int i; 200 201 cia_tlb_invalidate_fn = 202 cia_broken_pyxis_tlb_invalidate; 203 204 alpha_sgmap_init(t, &cia_pyxis_bug_sgmap, 205 "pyxis_bug_sgmap", CIA_PYXIS_BUG_BASE, 0, 206 CIA_PYXIS_BUG_SIZE, sizeof(u_int64_t), NULL, 207 (32*1024)); 208 209 REGVAL(CIA_PCI_W2BASE) = CIA_PYXIS_BUG_BASE | 210 CIA_PCI_WnBASE_SG_EN | CIA_PCI_WnBASE_W_EN; 211 alpha_mb(); 212 213 REGVAL(CIA_PCI_W2MASK) = CIA_PCI_WnMASK_2M; 214 alpha_mb(); 215 216 tbase = cia_pyxis_bug_sgmap.aps_ptpa >> 217 CIA_PCI_TnBASE_SHIFT; 218 if ((tbase & CIA_PCI_TnBASE_MASK) != tbase) 219 panic("cia_dma_init: bad page table address"); 220 REGVAL(CIA_PCI_T2BASE) = tbase; 221 alpha_mb(); 222 223 /* 224 * Initialize the page table to point at the spill 225 * page. Leave the last entry invalid. 226 */ 227 pci_sgmap_pte64_init_spill_page_pte(); 228 for (i = 0, page_table = cia_pyxis_bug_sgmap.aps_pt; 229 i < (CIA_PYXIS_BUG_SIZE / PAGE_SIZE) - 1; i++) { 230 page_table[i] = 231 pci_sgmap_pte64_prefetch_spill_page_pte; 232 } 233 alpha_mb(); 234 } else 235 cia_tlb_invalidate_fn = cia_tlb_invalidate; 236 237 CIA_TLB_INVALIDATE(); 238 239 /* XXX XXX BEGIN XXX XXX */ 240 { /* XXX */ 241 extern paddr_t alpha_XXX_dmamap_or; /* XXX */ 242 alpha_XXX_dmamap_or = CIA_DIRECT_MAPPED_BASE; /* XXX */ 243 } /* XXX */ 244 /* XXX XXX END XXX XXX */ 245 } 246 247 /* 248 * Return the bus dma tag to be used for the specified bus type. 249 * INTERNAL USE ONLY! 250 */ 251 bus_dma_tag_t 252 cia_dma_get_tag(t, bustype) 253 bus_dma_tag_t t; 254 alpha_bus_t bustype; 255 { 256 struct cia_config *ccp = t->_cookie; 257 258 switch (bustype) { 259 case ALPHA_BUS_PCI: 260 case ALPHA_BUS_EISA: 261 /* 262 * Systems with a CIA can only support 1G 263 * of memory, so we use the direct-mapped window 264 * on busses that have 32-bit DMA. 265 * 266 * Ahem: I have a PWS 500au with 1.5G of memory, and it 267 * had problems doing DMA because it was not falling back 268 * to using SGMAPs. I've fixed that and my PWS now works with 269 * 1.5G. There have been other reports about failures with 270 * more than 1.0G of memory. Michael Hitch 271 */ 272 return (&ccp->cc_dmat_direct); 273 274 case ALPHA_BUS_ISA: 275 /* 276 * ISA doesn't have enough address bits to use 277 * the direct-mapped DMA window, so we must use 278 * SGMAPs. 279 */ 280 return (&ccp->cc_dmat_sgmap); 281 282 default: 283 panic("cia_dma_get_tag: shouldn't be here, really..."); 284 } 285 } 286 287 /* 288 * Create a CIA direct-mapped DMA map. 289 */ 290 int 291 cia_bus_dmamap_create_direct(t, size, nsegments, maxsegsz, boundary, 292 flags, dmamp) 293 bus_dma_tag_t t; 294 bus_size_t size; 295 int nsegments; 296 bus_size_t maxsegsz; 297 bus_size_t boundary; 298 int flags; 299 bus_dmamap_t *dmamp; 300 { 301 struct cia_config *ccp = t->_cookie; 302 bus_dmamap_t map; 303 int error; 304 305 error = _bus_dmamap_create(t, size, nsegments, maxsegsz, 306 boundary, flags, dmamp); 307 if (error) 308 return (error); 309 310 map = *dmamp; 311 312 if ((ccp->cc_flags & CCF_PYXISBUG) != 0 && 313 map->_dm_segcnt > 1) { 314 /* 315 * We have a Pyxis with the DMA page crossing bug, make 316 * sure we don't coalesce adjacent DMA segments. 317 * 318 * NOTE: We can only do this if the max segment count 319 * is greater than 1. This is because many network 320 * drivers allocate large contiguous blocks of memory 321 * for control data structures, even though they won't 322 * do any single DMA that crosses a page boundary. 323 * -- thorpej@netbsd.org, 2/5/2000 324 */ 325 map->_dm_flags |= DMAMAP_NO_COALESCE; 326 } 327 328 return (0); 329 } 330 331 /* 332 * Load a CIA SGMAP-mapped DMA map with a linear buffer. 333 */ 334 int 335 cia_bus_dmamap_load_sgmap(t, map, buf, buflen, p, flags) 336 bus_dma_tag_t t; 337 bus_dmamap_t map; 338 void *buf; 339 bus_size_t buflen; 340 struct proc *p; 341 int flags; 342 { 343 int error; 344 345 error = pci_sgmap_pte64_load(t, map, buf, buflen, p, flags, 346 t->_sgmap); 347 if (error == 0) 348 CIA_TLB_INVALIDATE(); 349 350 return (error); 351 } 352 353 /* 354 * Load a CIA SGMAP-mapped DMA map with an mbuf chain. 355 */ 356 int 357 cia_bus_dmamap_load_mbuf_sgmap(t, map, m, flags) 358 bus_dma_tag_t t; 359 bus_dmamap_t map; 360 struct mbuf *m; 361 int flags; 362 { 363 int error; 364 365 error = pci_sgmap_pte64_load_mbuf(t, map, m, flags, t->_sgmap); 366 if (error == 0) 367 CIA_TLB_INVALIDATE(); 368 369 return (error); 370 } 371 372 /* 373 * Load a CIA SGMAP-mapped DMA map with a uio. 374 */ 375 int 376 cia_bus_dmamap_load_uio_sgmap(t, map, uio, flags) 377 bus_dma_tag_t t; 378 bus_dmamap_t map; 379 struct uio *uio; 380 int flags; 381 { 382 int error; 383 384 error = pci_sgmap_pte64_load_uio(t, map, uio, flags, t->_sgmap); 385 if (error == 0) 386 CIA_TLB_INVALIDATE(); 387 388 return (error); 389 } 390 391 /* 392 * Load a CIA SGMAP-mapped DMA map with raw memory. 393 */ 394 int 395 cia_bus_dmamap_load_raw_sgmap(t, map, segs, nsegs, size, flags) 396 bus_dma_tag_t t; 397 bus_dmamap_t map; 398 bus_dma_segment_t *segs; 399 int nsegs; 400 bus_size_t size; 401 int flags; 402 { 403 int error; 404 405 error = pci_sgmap_pte64_load_raw(t, map, segs, nsegs, size, flags, 406 t->_sgmap); 407 if (error == 0) 408 CIA_TLB_INVALIDATE(); 409 410 return (error); 411 } 412 413 /* 414 * Unload a CIA DMA map. 415 */ 416 void 417 cia_bus_dmamap_unload_sgmap(t, map) 418 bus_dma_tag_t t; 419 bus_dmamap_t map; 420 { 421 422 /* 423 * Invalidate any SGMAP page table entries used by this 424 * mapping. 425 */ 426 pci_sgmap_pte64_unload(t, map, t->_sgmap); 427 CIA_TLB_INVALIDATE(); 428 429 /* 430 * Do the generic bits of the unload. 431 */ 432 _bus_dmamap_unload(t, map); 433 } 434 435 /* 436 * Flush the CIA scatter/gather TLB. 437 */ 438 void 439 cia_tlb_invalidate() 440 { 441 442 alpha_mb(); 443 REGVAL(CIA_PCI_TBIA) = CIA_PCI_TBIA_ALL; 444 alpha_mb(); 445 } 446 447 /* 448 * Flush the scatter/gather TLB on broken Pyxis chips. 449 */ 450 void 451 cia_broken_pyxis_tlb_invalidate() 452 { 453 volatile u_int64_t dummy; 454 u_int32_t ctrl; 455 int i, s; 456 457 s = splhigh(); 458 459 /* 460 * Put the Pyxis into PCI loopback mode. 461 */ 462 alpha_mb(); 463 ctrl = REGVAL(CIA_CSR_CTRL); 464 REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN; 465 alpha_mb(); 466 467 /* 468 * Now, read from PCI dense memory space at offset 128M (our 469 * target window base), skipping 64k on each read. This forces 470 * S/G TLB misses. 471 * 472 * XXX Looks like the TLB entries are `not quite LRU'. We need 473 * XXX to read more times than there are actual tags! 474 */ 475 for (i = 0; i < CIA_TLB_NTAGS + 4; i++) { 476 dummy = *((volatile u_int64_t *) 477 ALPHA_PHYS_TO_K0SEG(CIA_PCI_DENSE + CIA_PYXIS_BUG_BASE + 478 (i * 65536))); 479 } 480 481 /* 482 * Restore normal PCI operation. 483 */ 484 alpha_mb(); 485 REGVAL(CIA_CSR_CTRL) = ctrl; 486 alpha_mb(); 487 488 splx(s); 489 } 490