1 /* $OpenBSD: ciareg.h,v 1.4 1996/10/30 22:39:57 niklas Exp $ */ 2 /* $NetBSD: ciareg.h,v 1.5 1996/07/09 00:54:44 cgd Exp $ */ 3 4 /* 5 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 6 * All rights reserved. 7 * 8 * Author: Chris G. Demetriou 9 * 10 * Permission to use, copy, modify and distribute this software and 11 * its documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 /* 32 * 21171 Chipset registers and constants. 33 * 34 * Taken from XXX 35 */ 36 37 #define REGVAL(r) (*(int32_t *)ALPHA_PHYS_TO_K0SEG(r)) 38 39 /* 40 * Base addresses 41 */ 42 #define CIA_PCI_SMEM1 0x8000000000L 43 #define CIA_PCI_SMEM2 0x8400000000L 44 #define CIA_PCI_SMEM3 0x8500000000L 45 #define CIA_PCI_SIO1 0x8580000000L 46 #define CIA_PCI_SIO2 0x85c0000000L 47 #define CIA_PCI_DENSE 0x8600000000L 48 #define CIA_PCI_CONF 0x8700000000L 49 #define CIA_PCI_IACK 0x8720000000L 50 #define CIA_CSRS 0x8740000000L 51 #define CIA_PCI_MC_CSRS 0x8750000000L 52 #define CIA_PCI_ATRANS 0x8760000000L 53 54 /* 55 * General CSRs 56 */ 57 58 #define CIA_CSR_HAE_MEM (CIA_CSRS + 0x400) 59 60 #define HAE_MEM_REG1_START(x) (((u_int32_t)(x) & 0xe0000000) << 0) 61 #define HAE_MEM_REG1_MASK 0x1fffffff 62 #define HAE_MEM_REG2_START(x) (((u_int32_t)(x) & 0x0000f800) << 16) 63 #define HAE_MEM_REG2_MASK 0x07ffffff 64 #define HAE_MEM_REG3_START(x) (((u_int32_t)(x) & 0x000000fc) << 16) 65 #define HAE_MEM_REG3_MASK 0x03ffffff 66 67 #define CIA_CSR_HAE_IO (CIA_CSRS + 0x440) 68 69 #define HAE_IO_REG1_START(x) 0 70 #define HAE_IO_REG1_MASK 0x01ffffff 71 #define HAE_IO_REG2_START(x) (((u_int32_t)(x) & 0xfe000000) << 0) 72 #define HAE_IO_REG2_MASK 0x01ffffff 73