1 /* $OpenBSD: pci_eb164.c,v 1.28 2017/09/08 05:36:51 deraadt Exp $ */ 2 /* $NetBSD: pci_eb164.c,v 1.27 2000/06/06 00:50:15 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 36 * All rights reserved. 37 * 38 * Author: Chris G. Demetriou 39 * 40 * Permission to use, copy, modify and distribute this software and 41 * its documentation is hereby granted, provided that both the copyright 42 * notice and this permission notice appear in all copies of the 43 * software, derivative works or modified versions, and any portions 44 * thereof, and that both notices appear in supporting documentation. 45 * 46 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 47 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 48 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 49 * 50 * Carnegie Mellon requests users of this software to return to 51 * 52 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 53 * School of Computer Science 54 * Carnegie Mellon University 55 * Pittsburgh PA 15213-3890 56 * 57 * any improvements or extensions that they make and grant Carnegie the 58 * rights to redistribute these changes. 59 */ 60 61 #include <sys/param.h> 62 #include <sys/time.h> 63 #include <sys/systm.h> 64 #include <sys/errno.h> 65 #include <sys/malloc.h> 66 #include <sys/device.h> 67 #include <sys/syslog.h> 68 69 #include <machine/autoconf.h> 70 #include <machine/rpb.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/ppbreg.h> 75 #include <dev/pci/pciidereg.h> 76 #include <dev/pci/pciidevar.h> 77 78 #include <alpha/pci/ciareg.h> 79 #include <alpha/pci/ciavar.h> 80 81 #include <alpha/pci/pci_eb164.h> 82 83 #include "sio.h" 84 #if NSIO 85 #include <alpha/pci/siovar.h> 86 #endif 87 88 int dec_eb164_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 89 const char *dec_eb164_intr_string(void *, pci_intr_handle_t); 90 int dec_eb164_intr_line(void *, pci_intr_handle_t); 91 void *dec_eb164_intr_establish(void *, pci_intr_handle_t, 92 int, int (*func)(void *), void *, const char *); 93 void dec_eb164_intr_disestablish(void *, void *); 94 95 void *dec_eb164_pciide_compat_intr_establish(void *, struct device *, 96 struct pci_attach_args *, int, int (*)(void *), void *); 97 void dec_eb164_pciide_compat_intr_disestablish(void *, void *); 98 99 #define EB164_SIO_IRQ 4 100 #define EB164_MAX_IRQ 24 101 #define PCI_STRAY_MAX 5 102 103 struct alpha_shared_intr *eb164_pci_intr; 104 105 bus_space_tag_t eb164_intrgate_iot; 106 bus_space_handle_t eb164_intrgate_ioh; 107 108 void eb164_iointr(void *arg, unsigned long vec); 109 extern void eb164_intr_enable(int irq); /* pci_eb164_intr.S */ 110 extern void eb164_intr_disable(int irq); /* pci_eb164_intr.S */ 111 112 void 113 pci_eb164_pickintr(ccp) 114 struct cia_config *ccp; 115 { 116 bus_space_tag_t iot = &ccp->cc_iot; 117 pci_chipset_tag_t pc = &ccp->cc_pc; 118 int i; 119 120 pc->pc_intr_v = ccp; 121 pc->pc_intr_map = dec_eb164_intr_map; 122 pc->pc_intr_string = dec_eb164_intr_string; 123 pc->pc_intr_line = dec_eb164_intr_line; 124 pc->pc_intr_establish = dec_eb164_intr_establish; 125 pc->pc_intr_disestablish = dec_eb164_intr_disestablish; 126 127 pc->pc_pciide_compat_intr_establish = 128 dec_eb164_pciide_compat_intr_establish; 129 pc->pc_pciide_compat_intr_disestablish = 130 dec_eb164_pciide_compat_intr_disestablish; 131 132 eb164_intrgate_iot = iot; 133 if (bus_space_map(eb164_intrgate_iot, 0x804, 3, 0, 134 &eb164_intrgate_ioh) != 0) 135 panic("pci_eb164_pickintr: couldn't map interrupt PLD"); 136 for (i = 0; i < EB164_MAX_IRQ; i++) 137 eb164_intr_disable(i); 138 139 eb164_pci_intr = alpha_shared_intr_alloc(EB164_MAX_IRQ); 140 for (i = 0; i < EB164_MAX_IRQ; i++) { 141 /* 142 * Systems with a Pyxis seem to have problems with 143 * stray interrupts, so just ignore them. Sigh, 144 * I hate buggy hardware. 145 */ 146 alpha_shared_intr_set_maxstrays(eb164_pci_intr, i, 147 (ccp->cc_flags & CCF_ISPYXIS) ? 0 : PCI_STRAY_MAX); 148 } 149 150 #if NSIO 151 sio_intr_setup(pc, iot); 152 eb164_intr_enable(EB164_SIO_IRQ); 153 #endif 154 } 155 156 int 157 dec_eb164_intr_map(pa, ihp) 158 struct pci_attach_args *pa; 159 pci_intr_handle_t *ihp; 160 { 161 int buspin, line = pa->pa_intrline; 162 u_int64_t variation; 163 164 /* 165 * 166 * The AlphaPC 164 and AlphaPC 164LX have a CMD PCI IDE controller 167 * at bus 0 device 11. These are wired to compatibility mode, 168 * so do not map their interrupts. 169 * 170 * The AlphaPC 164SX has PCI IDE on functions 1 and 2 of the 171 * Cypress PCI-ISA bridge at bus 0 device 8. These, too, are 172 * wired to compatibility mode. 173 * 174 * Real EB164s have ISA IDE on the Super I/O chip. 175 */ 176 variation = hwrpb->rpb_variation & SV_ST_MASK; 177 if (pa->pa_bus == 0) { 178 if (variation >= SV_ST_ALPHAPC164_366 && 179 variation <= SV_ST_ALPHAPC164LX_600) { 180 if (pa->pa_device == 8) 181 panic("dec_eb164_intr_map: SIO device"); 182 if (pa->pa_device == 11) 183 return (1); 184 } else if (variation >= SV_ST_ALPHAPC164SX_400 && 185 variation <= SV_ST_ALPHAPC164SX_600) { 186 if (pa->pa_device == 8) { 187 if (pa->pa_function == 0) 188 panic("dec_eb164_intr_map: SIO device"); 189 return (1); 190 } 191 } else { 192 if (pa->pa_device == 8) 193 panic("dec_eb164_intr_map: SIO device"); 194 } 195 } 196 197 /* 198 * The console places the interrupt mapping in the "line" value. 199 * We trust it whenever possible. 200 */ 201 if (line >= 0 && line < EB164_MAX_IRQ) { 202 *ihp = line; 203 return 0; 204 } 205 206 if (pa->pa_bridgetag) { 207 buspin = PPB_INTERRUPT_SWIZZLE(pa->pa_rawintrpin, 208 pa->pa_device); 209 if (pa->pa_bridgeih[buspin - 1] != 0) { 210 *ihp = pa->pa_bridgeih[buspin - 1]; 211 return 0; 212 } 213 } 214 215 return 1; 216 } 217 218 const char * 219 dec_eb164_intr_string(ccv, ih) 220 void *ccv; 221 pci_intr_handle_t ih; 222 { 223 #if 0 224 struct cia_config *ccp = ccv; 225 #endif 226 static char irqstr[15]; /* 11 + 2 + NULL + sanity */ 227 228 if (ih >= EB164_MAX_IRQ) 229 panic("dec_eb164_intr_string: bogus eb164 IRQ 0x%lx", ih); 230 snprintf(irqstr, sizeof irqstr, "eb164 irq %ld", ih); 231 return (irqstr); 232 } 233 234 int 235 dec_eb164_intr_line(ccv, ih) 236 void *ccv; 237 pci_intr_handle_t ih; 238 { 239 return (ih); 240 } 241 242 void * 243 dec_eb164_intr_establish(ccv, ih, level, func, arg, name) 244 void *ccv, *arg; 245 pci_intr_handle_t ih; 246 int level; 247 int (*func)(void *); 248 const char *name; 249 { 250 #if 0 251 struct cia_config *ccp = ccv; 252 #endif 253 void *cookie; 254 255 if (ih >= EB164_MAX_IRQ) 256 panic("dec_eb164_intr_establish: bogus eb164 IRQ 0x%lx", ih); 257 258 cookie = alpha_shared_intr_establish(eb164_pci_intr, ih, IST_LEVEL, 259 level, func, arg, name); 260 261 if (cookie != NULL && 262 alpha_shared_intr_firstactive(eb164_pci_intr, ih)) { 263 scb_set(0x900 + SCB_IDXTOVEC(ih), eb164_iointr, NULL); 264 eb164_intr_enable(ih); 265 } 266 return (cookie); 267 } 268 269 void 270 dec_eb164_intr_disestablish(ccv, cookie) 271 void *ccv, *cookie; 272 { 273 #if 0 274 struct cia_config *ccp = ccv; 275 #endif 276 struct alpha_shared_intrhand *ih = cookie; 277 unsigned int irq = ih->ih_num; 278 int s; 279 280 s = splhigh(); 281 282 alpha_shared_intr_disestablish(eb164_pci_intr, cookie); 283 if (alpha_shared_intr_isactive(eb164_pci_intr, irq) == 0) { 284 eb164_intr_disable(irq); 285 alpha_shared_intr_set_dfltsharetype(eb164_pci_intr, irq, 286 IST_NONE); 287 scb_free(0x900 + SCB_IDXTOVEC(irq)); 288 } 289 290 splx(s); 291 } 292 293 void * 294 dec_eb164_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 295 void *v; 296 struct device *dev; 297 struct pci_attach_args *pa; 298 int chan; 299 int (*func)(void *); 300 void *arg; 301 { 302 pci_chipset_tag_t pc = pa->pa_pc; 303 void *cookie = NULL; 304 int bus, irq; 305 306 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 307 308 /* 309 * If this isn't PCI bus #0, all bets are off. 310 */ 311 if (bus != 0) 312 return (NULL); 313 314 irq = PCIIDE_COMPAT_IRQ(chan); 315 #if NSIO 316 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 317 func, arg, dev->dv_xname); 318 if (cookie == NULL) 319 return (NULL); 320 #endif 321 return (cookie); 322 } 323 324 void 325 dec_eb164_pciide_compat_intr_disestablish(void *v, void *cookie) 326 { 327 sio_intr_disestablish(NULL, cookie); 328 } 329 330 void 331 eb164_iointr(arg, vec) 332 void *arg; 333 unsigned long vec; 334 { 335 int irq; 336 337 irq = SCB_VECTOIDX(vec - 0x900); 338 339 if (!alpha_shared_intr_dispatch(eb164_pci_intr, irq)) { 340 alpha_shared_intr_stray(eb164_pci_intr, irq, 341 "eb164 irq"); 342 if (ALPHA_SHARED_INTR_DISABLE(eb164_pci_intr, irq)) 343 eb164_intr_disable(irq); 344 } else 345 alpha_shared_intr_reset_strays(eb164_pci_intr, irq); 346 } 347 348 #if 0 /* THIS DOES NOT WORK! see pci_eb164_intr.S. */ 349 u_int8_t eb164_intr_mask[3] = { 0xff, 0xff, 0xff }; 350 351 void 352 eb164_intr_enable(irq) 353 int irq; 354 { 355 int byte = (irq / 8), bit = (irq % 8); 356 357 #if 1 358 printf("eb164_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 359 #endif 360 eb164_intr_mask[byte] &= ~(1 << bit); 361 362 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 363 eb164_intr_mask[byte]); 364 } 365 366 void 367 eb164_intr_disable(irq) 368 int irq; 369 { 370 int byte = (irq / 8), bit = (irq % 8); 371 372 #if 1 373 printf("eb164_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 374 #endif 375 eb164_intr_mask[byte] |= (1 << bit); 376 377 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 378 eb164_intr_mask[byte]); 379 } 380 #endif 381