1 /* $OpenBSD: tc_3000_500.c,v 1.15 2008/08/09 16:42:29 miod Exp $ */ 2 /* $NetBSD: tc_3000_500.c,v 1.24 2001/07/27 00:25:21 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 6 * All rights reserved. 7 * 8 * Author: Chris G. Demetriou 9 * 10 * Permission to use, copy, modify and distribute this software and 11 * its documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 #include <sys/malloc.h> 35 36 #include <machine/autoconf.h> 37 #include <machine/pte.h> 38 #include <machine/rpb.h> 39 40 #include <dev/tc/tcvar.h> 41 #include <alpha/tc/tc_conf.h> 42 #include <alpha/tc/tc_3000_500.h> 43 44 #include "wsdisplay.h" 45 #include "sfb.h" 46 47 #if NSFB > 0 48 extern int sfb_cnattach(tc_addr_t); 49 #endif 50 51 int tc_3000_500_intrnull(void *); 52 int tc_3000_500_fb_cnattach(u_int64_t); 53 54 #define C(x) ((void *)(u_long)x) 55 #define KV(x) (ALPHA_PHYS_TO_K0SEG(x)) 56 57 struct tc_slotdesc tc_3000_500_slots[] = { 58 { KV(0x100000000), C(TC_3000_500_DEV_OPT0), }, /* 0 - opt slot 0 */ 59 { KV(0x120000000), C(TC_3000_500_DEV_OPT1), }, /* 1 - opt slot 1 */ 60 { KV(0x140000000), C(TC_3000_500_DEV_OPT2), }, /* 2 - opt slot 2 */ 61 { KV(0x160000000), C(TC_3000_500_DEV_OPT3), }, /* 3 - opt slot 3 */ 62 { KV(0x180000000), C(TC_3000_500_DEV_OPT4), }, /* 4 - opt slot 4 */ 63 { KV(0x1a0000000), C(TC_3000_500_DEV_OPT5), }, /* 5 - opt slot 5 */ 64 { KV(0x1c0000000), C(TC_3000_500_DEV_BOGUS), }, /* 6 - TCDS ASIC */ 65 { KV(0x1e0000000), C(TC_3000_500_DEV_BOGUS), }, /* 7 - IOCTL ASIC */ 66 }; 67 int tc_3000_500_nslots = 68 sizeof(tc_3000_500_slots) / sizeof(tc_3000_500_slots[0]); 69 70 struct tc_builtin tc_3000_500_graphics_builtins[] = { 71 { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), }, 72 { "PMAGB-BA", 7, 0x02000000, C(TC_3000_500_DEV_CXTURBO), }, 73 { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), }, 74 }; 75 int tc_3000_500_graphics_nbuiltins = sizeof(tc_3000_500_graphics_builtins) / 76 sizeof(tc_3000_500_graphics_builtins[0]); 77 78 struct tc_builtin tc_3000_500_nographics_builtins[] = { 79 { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), }, 80 { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), }, 81 }; 82 int tc_3000_500_nographics_nbuiltins = sizeof(tc_3000_500_nographics_builtins) / 83 sizeof(tc_3000_500_nographics_builtins[0]); 84 85 u_int32_t tc_3000_500_intrbits[TC_3000_500_NCOOKIES] = { 86 TC_3000_500_IR_OPT0, 87 TC_3000_500_IR_OPT1, 88 TC_3000_500_IR_OPT2, 89 TC_3000_500_IR_OPT3, 90 TC_3000_500_IR_OPT4, 91 TC_3000_500_IR_OPT5, 92 TC_3000_500_IR_TCDS, 93 TC_3000_500_IR_IOASIC, 94 TC_3000_500_IR_CXTURBO, 95 }; 96 97 struct tcintr { 98 int (*tci_func)(void *); 99 void *tci_arg; 100 struct evcount tci_count; 101 } tc_3000_500_intr[TC_3000_500_NCOOKIES]; 102 103 u_int32_t tc_3000_500_imask; /* intrs we want to ignore; mirrors IMR. */ 104 105 void 106 tc_3000_500_intr_setup() 107 { 108 u_long i; 109 110 /* 111 * Disable all slot interrupts. Note that this cannot 112 * actually disable CXTurbo, TCDS, and IOASIC interrupts. 113 */ 114 tc_3000_500_imask = *(volatile u_int32_t *)TC_3000_500_IMR_READ; 115 for (i = 0; i < TC_3000_500_NCOOKIES; i++) 116 tc_3000_500_imask |= tc_3000_500_intrbits[i]; 117 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask; 118 tc_mb(); 119 120 /* 121 * Set up interrupt handlers. 122 */ 123 for (i = 0; i < TC_3000_500_NCOOKIES; i++) { 124 tc_3000_500_intr[i].tci_func = tc_3000_500_intrnull; 125 tc_3000_500_intr[i].tci_arg = (void *)i; 126 } 127 } 128 129 void 130 tc_3000_500_intr_establish(tcadev, cookie, level, func, arg, name) 131 struct device *tcadev; 132 void *cookie, *arg; 133 int level; 134 int (*func)(void *); 135 const char *name; 136 { 137 u_long dev = (u_long)cookie; 138 139 #ifdef DIAGNOSTIC 140 /* XXX bounds-check cookie. */ 141 #endif 142 143 if (tc_3000_500_intr[dev].tci_func != tc_3000_500_intrnull) 144 panic("tc_3000_500_intr_establish: cookie %lu twice", dev); 145 146 tc_3000_500_intr[dev].tci_func = func; 147 tc_3000_500_intr[dev].tci_arg = arg; 148 if (name != NULL) 149 evcount_attach(&tc_3000_500_intr[dev].tci_count, 150 name, NULL, &evcount_intr); 151 152 tc_3000_500_imask &= ~tc_3000_500_intrbits[dev]; 153 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask; 154 tc_mb(); 155 } 156 157 void 158 tc_3000_500_intr_disestablish(tcadev, cookie) 159 struct device *tcadev; 160 void *cookie; 161 { 162 u_long dev = (u_long)cookie; 163 164 #ifdef DIAGNOSTIC 165 /* XXX bounds-check cookie. */ 166 #endif 167 168 if (tc_3000_500_intr[dev].tci_func == tc_3000_500_intrnull) 169 panic("tc_3000_500_intr_disestablish: cookie %lu bad intr", 170 dev); 171 172 tc_3000_500_imask |= tc_3000_500_intrbits[dev]; 173 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask; 174 tc_mb(); 175 176 tc_3000_500_intr[dev].tci_func = tc_3000_500_intrnull; 177 tc_3000_500_intr[dev].tci_arg = (void *)dev; 178 if (tc_3000_500_intr[dev].tci_count.ec_parent != NULL) 179 evcount_detach(&tc_3000_500_intr[dev].tci_count); 180 } 181 182 int 183 tc_3000_500_intrnull(val) 184 void *val; 185 { 186 187 panic("tc_3000_500_intrnull: uncaught TC intr for cookie %ld", 188 (u_long)val); 189 } 190 191 void 192 tc_3000_500_iointr(arg, vec) 193 void *arg; 194 unsigned long vec; 195 { 196 u_int32_t ir; 197 int ifound; 198 199 #ifdef DIAGNOSTIC 200 int s; 201 if (vec != 0x800) 202 panic("INVALID ASSUMPTION: vec 0x%lx, not 0x800", vec); 203 s = splhigh(); 204 if (s != ALPHA_PSL_IPL_IO) 205 panic("INVALID ASSUMPTION: IPL %d, not %d", s, 206 ALPHA_PSL_IPL_IO); 207 splx(s); 208 #endif 209 210 do { 211 tc_syncbus(); 212 ir = *(volatile u_int32_t *)TC_3000_500_IR_CLEAR; 213 214 /* Ignore interrupts that we haven't enabled. */ 215 ir &= ~(tc_3000_500_imask & 0x1ff); 216 217 ifound = 0; 218 219 #define CHECKINTR(slot) \ 220 if (ir & tc_3000_500_intrbits[slot]) { \ 221 ifound = 1; \ 222 tc_3000_500_intr[slot].tci_count.ec_count++; \ 223 (*tc_3000_500_intr[slot].tci_func) \ 224 (tc_3000_500_intr[slot].tci_arg); \ 225 } 226 /* Do them in order of priority; highest slot # first. */ 227 CHECKINTR(TC_3000_500_DEV_CXTURBO); 228 CHECKINTR(TC_3000_500_DEV_IOASIC); 229 CHECKINTR(TC_3000_500_DEV_TCDS); 230 CHECKINTR(TC_3000_500_DEV_OPT5); 231 CHECKINTR(TC_3000_500_DEV_OPT4); 232 CHECKINTR(TC_3000_500_DEV_OPT3); 233 CHECKINTR(TC_3000_500_DEV_OPT2); 234 CHECKINTR(TC_3000_500_DEV_OPT1); 235 CHECKINTR(TC_3000_500_DEV_OPT0); 236 #undef CHECKINTR 237 238 #ifdef DIAGNOSTIC 239 #define PRINTINTR(msg, bits) \ 240 if (ir & bits) \ 241 printf(msg); 242 PRINTINTR("Second error occurred\n", TC_3000_500_IR_ERR2); 243 PRINTINTR("DMA buffer error\n", TC_3000_500_IR_DMABE); 244 PRINTINTR("DMA cross 2K boundary\n", TC_3000_500_IR_DMA2K); 245 PRINTINTR("TC reset in progress\n", TC_3000_500_IR_TCRESET); 246 PRINTINTR("TC parity error\n", TC_3000_500_IR_TCPAR); 247 PRINTINTR("DMA tag error\n", TC_3000_500_IR_DMATAG); 248 PRINTINTR("Single-bit error\n", TC_3000_500_IR_DMASBE); 249 PRINTINTR("Double-bit error\n", TC_3000_500_IR_DMADBE); 250 PRINTINTR("TC I/O timeout\n", TC_3000_500_IR_TCTIMEOUT); 251 PRINTINTR("DMA block too long\n", TC_3000_500_IR_DMABLOCK); 252 PRINTINTR("Invalid I/O address\n", TC_3000_500_IR_IOADDR); 253 PRINTINTR("DMA scatter/gather invalid\n", TC_3000_500_IR_DMASG); 254 PRINTINTR("Scatter/gather parity error\n", 255 TC_3000_500_IR_SGPAR); 256 #undef PRINTINTR 257 #endif 258 } while (ifound); 259 } 260 261 #if NWSDISPLAY > 0 262 /* 263 * tc_3000_500_fb_cnattach -- 264 * Attempt to map the CTB output device to a slot and attach the 265 * framebuffer as the output side of the console. 266 */ 267 int 268 tc_3000_500_fb_cnattach(turbo_slot) 269 u_int64_t turbo_slot; 270 { 271 u_int32_t output_slot; 272 273 output_slot = turbo_slot & 0xffffffff; 274 275 if (output_slot >= tc_3000_500_nslots) { 276 return EINVAL; 277 } 278 279 if (hwrpb->rpb_variation & SV_GRAPHICS) { 280 if (output_slot == 0) { 281 #if NSFB > 0 282 sfb_cnattach(KV(0x1e0000000) + 0x02000000); 283 return 0; 284 #else 285 return ENXIO; 286 #endif 287 } 288 } else { 289 /* 290 * Slots 0-2 in the tc_3000_500_slots array are only 291 * on the 500 models that also have the CXTurbo 292 * (500/800/900) and a total of 6 TC slots. For the 293 * 400/600/700, slots 0-2 are in table locations 3-5, so 294 * offset the CTB slot by 3 to get the address in our table. 295 */ 296 output_slot += 3; 297 } 298 return tc_fb_cnattach(tc_3000_500_slots[output_slot-1].tcs_addr); 299 } 300 #endif /* NWSDISPLAY */ 301 302 #if 0 303 /* 304 * tc_3000_500_ioslot -- 305 * Set the PBS bits for devices on the TC. 306 */ 307 void 308 tc_3000_500_ioslot(slot, flags, set) 309 u_int32_t slot, flags; 310 int set; 311 { 312 volatile u_int32_t *iosp; 313 u_int32_t ios; 314 int s; 315 316 iosp = (volatile u_int32_t *)TC_3000_500_IOSLOT; 317 ios = *iosp; 318 flags <<= (slot * 3); 319 if (set) 320 ios |= flags; 321 else 322 ios &= ~flags; 323 s = splhigh(); 324 *iosp = ios; 325 tc_mb(); 326 splx(s); 327 } 328 #endif 329