1 /* $OpenBSD: cpu.h,v 1.159 2023/08/23 01:55:46 cheloha Exp $ */ 2 /* $NetBSD: cpu.h,v 1.1 2003/04/26 18:39:39 fvdl Exp $ */ 3 4 /*- 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 36 */ 37 38 #ifndef _MACHINE_CPU_H_ 39 #define _MACHINE_CPU_H_ 40 41 /* 42 * Definitions unique to x86-64 cpu support. 43 */ 44 #ifdef _KERNEL 45 #include <machine/frame.h> 46 #include <machine/segments.h> /* USERMODE */ 47 #include <machine/intrdefs.h> 48 #endif /* _KERNEL */ 49 50 #include <sys/clockintr.h> 51 #include <sys/device.h> 52 #include <sys/rwlock.h> 53 #include <sys/sched.h> 54 #include <sys/sensors.h> 55 #include <sys/srp.h> 56 57 #ifdef _KERNEL 58 59 /* VMXON region (Intel) */ 60 struct vmxon_region { 61 uint32_t vr_revision; 62 }; 63 64 /* 65 * VMX for Intel CPUs 66 */ 67 struct vmx { 68 uint64_t vmx_cr0_fixed0; 69 uint64_t vmx_cr0_fixed1; 70 uint64_t vmx_cr4_fixed0; 71 uint64_t vmx_cr4_fixed1; 72 uint32_t vmx_vmxon_revision; 73 uint32_t vmx_msr_table_size; 74 uint32_t vmx_cr3_tgt_count; 75 uint64_t vmx_vm_func; 76 uint8_t vmx_has_l1_flush_msr; 77 }; 78 79 /* 80 * SVM for AMD CPUs 81 */ 82 struct svm { 83 uint32_t svm_max_asid; 84 uint8_t svm_flush_by_asid; 85 uint8_t svm_vmcb_clean; 86 uint8_t svm_decode_assist; 87 }; 88 89 union vmm_cpu_cap { 90 struct vmx vcc_vmx; 91 struct svm vcc_svm; 92 }; 93 94 /* 95 * Locks used to protect struct members in this file: 96 * I immutable after creation 97 * a atomic operations 98 * o owned (read/modified only) by this CPU 99 */ 100 struct x86_64_tss; 101 struct cpu_info { 102 /* 103 * The beginning of this structure in mapped in the userspace "u-k" 104 * page tables, so that these first couple members can be accessed 105 * from the trampoline code. The ci_PAGEALIGN member defines where 106 * the part that is *not* visible begins, so don't put anything 107 * above it that must be kept hidden from userspace! 108 */ 109 u_int64_t ci_kern_cr3; /* [o] U+K page table */ 110 u_int64_t ci_scratch; /* [o] for U<-->K transition */ 111 112 #define ci_PAGEALIGN ci_dev 113 struct device *ci_dev; /* [I] */ 114 struct cpu_info *ci_self; /* [I] */ 115 struct cpu_info *ci_next; /* [I] */ 116 117 u_int ci_cpuid; /* [I] */ 118 u_int ci_apicid; /* [I] */ 119 u_int ci_acpi_proc_id; /* [I] */ 120 u_int32_t ci_randseed; /* [o] */ 121 122 u_int64_t ci_kern_rsp; /* [o] kernel-only stack */ 123 u_int64_t ci_intr_rsp; /* [o] U<-->K trampoline stack */ 124 u_int64_t ci_user_cr3; /* [o] U-K page table */ 125 126 /* bits for mitigating Micro-architectural Data Sampling */ 127 char ci_mds_tmp[32]; /* [o] 32byte aligned */ 128 void *ci_mds_buf; /* [I] */ 129 130 struct proc *ci_curproc; /* [o] */ 131 struct schedstate_percpu ci_schedstate; /* scheduler state */ 132 133 struct pmap *ci_proc_pmap; /* last userspace pmap */ 134 struct pcb *ci_curpcb; /* [o] */ 135 struct pcb *ci_idle_pcb; /* [o] */ 136 137 u_int ci_pflags; /* [o] */ 138 #define CPUPF_USERSEGS 0x01 /* CPU has curproc's segs and FS.base */ 139 #define CPUPF_USERXSTATE 0x02 /* CPU has curproc's xsave state */ 140 141 struct intrsource *ci_isources[MAX_INTR_SOURCES]; 142 u_int64_t ci_ipending; 143 int ci_ilevel; 144 int ci_idepth; 145 int ci_handled_intr_level; 146 u_int64_t ci_imask[NIPL]; 147 u_int64_t ci_iunmask[NIPL]; 148 #ifdef DIAGNOSTIC 149 int ci_mutex_level; 150 #endif 151 152 volatile u_int ci_flags; /* [a] */ 153 u_int32_t ci_ipis; /* [a] */ 154 155 u_int32_t ci_feature_flags; /* [I] */ 156 u_int32_t ci_feature_eflags; /* [I] */ 157 u_int32_t ci_feature_sefflags_ebx;/* [I] */ 158 u_int32_t ci_feature_sefflags_ecx;/* [I] */ 159 u_int32_t ci_feature_sefflags_edx;/* [I] */ 160 u_int32_t ci_feature_amdspec_ebx; /* [I] */ 161 u_int32_t ci_feature_tpmflags; /* [I] */ 162 u_int32_t ci_pnfeatset; /* [I] */ 163 u_int32_t ci_efeature_eax; /* [I] */ 164 u_int32_t ci_efeature_ecx; /* [I] */ 165 u_int32_t ci_brand[12]; /* [I] */ 166 u_int32_t ci_signature; /* [I] */ 167 u_int32_t ci_family; /* [I] */ 168 u_int32_t ci_model; /* [I] */ 169 u_int32_t ci_cflushsz; /* [I] */ 170 171 int ci_inatomic; /* [o] */ 172 173 #define __HAVE_CPU_TOPOLOGY 174 u_int32_t ci_smt_id; /* [I] */ 175 u_int32_t ci_core_id; /* [I] */ 176 u_int32_t ci_pkg_id; /* [I] */ 177 178 struct cpu_functions *ci_func; /* [I] */ 179 void (*cpu_setup)(struct cpu_info *); /* [I] */ 180 181 struct device *ci_acpicpudev; /* [I] */ 182 volatile u_int ci_mwait; /* [a] */ 183 #define MWAIT_IN_IDLE 0x1 /* don't need IPI to wake */ 184 #define MWAIT_KEEP_IDLING 0x2 /* cleared by other cpus to wake me */ 185 #define MWAIT_ONLY 0x4 /* set if all idle states use mwait */ 186 #define MWAIT_IDLING (MWAIT_IN_IDLE | MWAIT_KEEP_IDLING) 187 188 int ci_want_resched; 189 190 struct x86_64_tss *ci_tss; /* [o] */ 191 void *ci_gdt; /* [o] */ 192 193 volatile int ci_ddb_paused; 194 #define CI_DDB_RUNNING 0 195 #define CI_DDB_SHOULDSTOP 1 196 #define CI_DDB_STOPPED 2 197 #define CI_DDB_ENTERDDB 3 198 #define CI_DDB_INDDB 4 199 200 #ifdef MULTIPROCESSOR 201 struct srp_hazard ci_srp_hazards[SRP_HAZARD_NUM]; 202 #endif 203 204 struct ksensordev ci_sensordev; 205 struct ksensor ci_sensor; 206 struct ksensor ci_hz_sensor; 207 u_int64_t ci_hz_mperf; 208 u_int64_t ci_hz_aperf; 209 #if defined(GPROF) || defined(DDBPROF) 210 struct gmonparam *ci_gmon; 211 struct clockintr *ci_gmonclock; 212 #endif 213 u_int32_t ci_vmm_flags; 214 #define CI_VMM_VMX (1 << 0) 215 #define CI_VMM_SVM (1 << 1) 216 #define CI_VMM_RVI (1 << 2) 217 #define CI_VMM_EPT (1 << 3) 218 #define CI_VMM_DIS (1 << 4) 219 union vmm_cpu_cap ci_vmm_cap; 220 paddr_t ci_vmxon_region_pa; 221 struct vmxon_region *ci_vmxon_region; 222 223 char ci_panicbuf[512]; 224 225 paddr_t ci_vmcs_pa; 226 struct rwlock ci_vmcs_lock; 227 228 struct clockintr_queue ci_queue; 229 }; 230 231 #define CPUF_BSP 0x0001 /* CPU is the original BSP */ 232 #define CPUF_AP 0x0002 /* CPU is an AP */ 233 #define CPUF_SP 0x0004 /* CPU is only processor */ 234 #define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */ 235 236 #define CPUF_IDENTIFY 0x0010 /* CPU may now identify */ 237 #define CPUF_IDENTIFIED 0x0020 /* CPU has been identified */ 238 239 #define CPUF_CONST_TSC 0x0040 /* CPU has constant TSC */ 240 #define CPUF_INVAR_TSC 0x0100 /* CPU has invariant TSC */ 241 242 #define CPUF_PRESENT 0x1000 /* CPU is present */ 243 #define CPUF_RUNNING 0x2000 /* CPU is running */ 244 #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ 245 #define CPUF_GO 0x8000 /* CPU should start running */ 246 #define CPUF_PARK 0x10000 /* CPU should self-park in real mode */ 247 #define CPUF_VMM 0x20000 /* CPU is executing in VMM mode */ 248 249 #define PROC_PC(p) ((p)->p_md.md_regs->tf_rip) 250 #define PROC_STACK(p) ((p)->p_md.md_regs->tf_rsp) 251 252 struct cpu_info_full; 253 extern struct cpu_info_full cpu_info_full_primary; 254 #define cpu_info_primary (*(struct cpu_info *)((char *)&cpu_info_full_primary + 4096*2 - offsetof(struct cpu_info, ci_PAGEALIGN))) 255 256 extern struct cpu_info *cpu_info_list; 257 258 #define CPU_INFO_ITERATOR int 259 #define CPU_INFO_FOREACH(cii, ci) for (cii = 0, ci = cpu_info_list; \ 260 ci != NULL; ci = ci->ci_next) 261 262 #define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0) 263 264 /* 265 * Preempt the current process if in interrupt from user mode, 266 * or after the current trap/syscall if in system mode. 267 */ 268 extern void need_resched(struct cpu_info *); 269 #define clear_resched(ci) (ci)->ci_want_resched = 0 270 271 #if defined(MULTIPROCESSOR) 272 273 #define MAXCPUS 64 /* bitmask */ 274 275 #define CPU_STARTUP(_ci) ((_ci)->ci_func->start(_ci)) 276 #define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci)) 277 #define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci)) 278 279 #define curcpu() ({struct cpu_info *__ci; \ 280 asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) \ 281 :"n" (offsetof(struct cpu_info, ci_self))); \ 282 __ci;}) 283 #define cpu_number() (curcpu()->ci_cpuid) 284 285 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 286 #define CPU_IS_RUNNING(ci) ((ci)->ci_flags & CPUF_RUNNING) 287 288 extern struct cpu_info *cpu_info[MAXCPUS]; 289 290 void cpu_boot_secondary_processors(void); 291 292 void cpu_kick(struct cpu_info *); 293 void cpu_unidle(struct cpu_info *); 294 295 #define CPU_BUSY_CYCLE() __asm volatile("pause": : : "memory") 296 297 #else /* !MULTIPROCESSOR */ 298 299 #define MAXCPUS 1 300 301 #ifdef _KERNEL 302 #define curcpu() (&cpu_info_primary) 303 304 #define cpu_kick(ci) 305 #define cpu_unidle(ci) 306 307 #define CPU_BUSY_CYCLE() do {} while (0) 308 309 #endif 310 311 /* 312 * definitions of cpu-dependent requirements 313 * referenced in generic code 314 */ 315 #define cpu_number() 0 316 #define CPU_IS_PRIMARY(ci) 1 317 #define CPU_IS_RUNNING(ci) 1 318 319 #endif /* MULTIPROCESSOR */ 320 321 #include <machine/cpufunc.h> 322 #include <machine/psl.h> 323 324 static inline unsigned int 325 cpu_rnd_messybits(void) 326 { 327 unsigned int hi, lo; 328 329 __asm volatile("rdtsc" : "=d" (hi), "=a" (lo)); 330 331 return (hi ^ lo); 332 } 333 334 #endif /* _KERNEL */ 335 336 #ifdef MULTIPROCESSOR 337 #include <sys/mplock.h> 338 #endif 339 340 #define aston(p) ((p)->p_md.md_astpending = 1) 341 342 #define curpcb curcpu()->ci_curpcb 343 344 /* 345 * Arguments to hardclock, softclock and statclock 346 * encapsulate the previous machine state in an opaque 347 * clockframe; for now, use generic intrframe. 348 */ 349 #define clockframe intrframe 350 351 #define CLKF_USERMODE(frame) USERMODE((frame)->if_cs, (frame)->if_rflags) 352 #define CLKF_PC(frame) ((frame)->if_rip) 353 #define CLKF_INTR(frame) (curcpu()->ci_idepth > 1) 354 355 /* 356 * Give a profiling tick to the current process when the user profiling 357 * buffer pages are invalid. On the i386, request an ast to send us 358 * through usertrap(), marking the proc as needing a profiling tick. 359 */ 360 #define need_proftick(p) aston(p) 361 362 void signotify(struct proc *); 363 364 /* 365 * We need a machine-independent name for this. 366 */ 367 extern void (*delay_func)(int); 368 void delay_fini(void (*)(int)); 369 void delay_init(void (*)(int), int); 370 struct timeval; 371 372 #define DELAY(x) (*delay_func)(x) 373 #define delay(x) (*delay_func)(x) 374 375 376 #ifdef _KERNEL 377 /* cpu.c */ 378 extern int cpu_feature; 379 extern int cpu_ebxfeature; 380 extern int cpu_ecxfeature; 381 extern int cpu_perf_eax; 382 extern int cpu_perf_ebx; 383 extern int cpu_perf_edx; 384 extern int cpu_apmi_edx; 385 extern int ecpu_ecxfeature; 386 extern int cpu_id; 387 extern char cpu_vendor[]; 388 extern int cpuid_level; 389 extern int cpu_meltdown; 390 extern u_int cpu_mwait_size; 391 extern u_int cpu_mwait_states; 392 393 /* cacheinfo.c */ 394 void x86_print_cacheinfo(struct cpu_info *); 395 396 /* identcpu.c */ 397 void identifycpu(struct cpu_info *); 398 int cpu_amd64speed(int *); 399 extern int cpuspeed; 400 401 /* machdep.c */ 402 void dumpconf(void); 403 void cpu_reset(void); 404 void x86_64_proc0_tss_ldt_init(void); 405 void cpu_proc_fork(struct proc *, struct proc *); 406 int amd64_pa_used(paddr_t); 407 #define cpu_idle_enter() do { /* nothing */ } while (0) 408 extern void (*cpu_idle_cycle_fcn)(void); 409 #define cpu_idle_cycle() (*cpu_idle_cycle_fcn)() 410 #define cpu_idle_leave() do { /* nothing */ } while (0) 411 extern void (*initclock_func)(void); 412 extern void (*startclock_func)(void); 413 414 struct region_descriptor; 415 void lgdt(struct region_descriptor *); 416 417 struct pcb; 418 void savectx(struct pcb *); 419 void switch_exit(struct proc *, void (*)(struct proc *)); 420 void proc_trampoline(void); 421 422 /* clock.c */ 423 void startclocks(void); 424 void rtcinit(void); 425 void rtcstart(void); 426 void rtcstop(void); 427 void i8254_delay(int); 428 void i8254_initclocks(void); 429 void i8254_startclock(void); 430 void i8254_start_both_clocks(void); 431 void i8254_inittimecounter(void); 432 void i8254_inittimecounter_simple(void); 433 434 /* i8259.c */ 435 void i8259_default_setup(void); 436 437 void cpu_init_msrs(struct cpu_info *); 438 void cpu_fix_msrs(struct cpu_info *); 439 void cpu_tsx_disable(struct cpu_info *); 440 441 /* dkcsum.c */ 442 void dkcsumattach(void); 443 444 /* bus_machdep.c */ 445 void x86_bus_space_init(void); 446 void x86_bus_space_mallocok(void); 447 448 /* powernow-k8.c */ 449 void k8_powernow_init(struct cpu_info *); 450 void k8_powernow_setperf(int); 451 452 /* k1x-pstate.c */ 453 void k1x_init(struct cpu_info *); 454 void k1x_setperf(int); 455 456 void est_init(struct cpu_info *); 457 void est_setperf(int); 458 459 #ifdef MULTIPROCESSOR 460 /* mp_setperf.c */ 461 void mp_setperf_init(void); 462 #endif 463 464 #endif /* _KERNEL */ 465 466 /* 467 * CTL_MACHDEP definitions. 468 */ 469 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 470 #define CPU_BIOS 2 /* BIOS variables */ 471 #define CPU_BLK2CHR 3 /* convert blk maj into chr one */ 472 #define CPU_CHR2BLK 4 /* convert chr maj into blk one */ 473 #define CPU_ALLOWAPERTURE 5 /* allow mmap of /dev/xf86 */ 474 #define CPU_CPUVENDOR 6 /* cpuid vendor string */ 475 #define CPU_CPUID 7 /* cpuid */ 476 #define CPU_CPUFEATURE 8 /* cpuid features */ 477 #define CPU_KBDRESET 10 /* keyboard reset under pcvt */ 478 #define CPU_XCRYPT 12 /* supports VIA xcrypt in userland */ 479 #define CPU_LIDACTION 14 /* action caused by lid close */ 480 #define CPU_FORCEUKBD 15 /* Force ukbd(4) as console keyboard */ 481 #define CPU_TSCFREQ 16 /* TSC frequency */ 482 #define CPU_INVARIANTTSC 17 /* has invariant TSC */ 483 #define CPU_PWRACTION 18 /* action caused by power button */ 484 #define CPU_MAXID 19 /* number of valid machdep ids */ 485 486 #define CTL_MACHDEP_NAMES { \ 487 { 0, 0 }, \ 488 { "console_device", CTLTYPE_STRUCT }, \ 489 { "bios", CTLTYPE_INT }, \ 490 { "blk2chr", CTLTYPE_STRUCT }, \ 491 { "chr2blk", CTLTYPE_STRUCT }, \ 492 { "allowaperture", CTLTYPE_INT }, \ 493 { "cpuvendor", CTLTYPE_STRING }, \ 494 { "cpuid", CTLTYPE_INT }, \ 495 { "cpufeature", CTLTYPE_INT }, \ 496 { 0, 0 }, \ 497 { "kbdreset", CTLTYPE_INT }, \ 498 { 0, 0 }, \ 499 { "xcrypt", CTLTYPE_INT }, \ 500 { 0, 0 }, \ 501 { "lidaction", CTLTYPE_INT }, \ 502 { "forceukbd", CTLTYPE_INT }, \ 503 { "tscfreq", CTLTYPE_QUAD }, \ 504 { "invarianttsc", CTLTYPE_INT }, \ 505 { "pwraction", CTLTYPE_INT }, \ 506 } 507 508 #endif /* !_MACHINE_CPU_H_ */ 509