xref: /openbsd/sys/arch/amd64/include/i82093var.h (revision e5dd7070)
1 /*	$OpenBSD: i82093var.h,v 1.5 2016/05/04 14:30:00 kettenis Exp $	*/
2 /* $NetBSD: i82093var.h,v 1.1 2003/02/26 21:26:10 fvdl Exp $ */
3 
4 /*-
5  * Copyright (c) 2000 The NetBSD Foundation, Inc.
6  * All rights reserved.
7  *
8  * This code is derived from software contributed to The NetBSD Foundation
9  * by RedBack Networks Inc.
10  *
11  * Author: Bill Sommerfeld
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  * 1. Redistributions of source code must retain the above copyright
17  *    notice, this list of conditions and the following disclaimer.
18  * 2. Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the distribution.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
23  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
24  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
25  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32  * POSSIBILITY OF SUCH DAMAGE.
33  */
34 
35 #ifndef _MACHINE_I82093VAR_H_
36 #define _MACHINE_I82093VAR_H_
37 
38 #include <machine/apicvar.h>
39 
40 struct ioapic_pin
41 {
42 	struct ioapic_pin	*ip_next;	/* next pin on this vector */
43 	struct mp_intr_map 	*ip_map;
44 	int			ip_vector;	/* IDT vector */
45 	int			ip_type;
46 	struct cpu_info		*ip_cpu;	/* target CPU */
47 };
48 
49 struct ioapic_softc {
50 	struct pic		sc_pic;
51 	struct ioapic_softc	*sc_next;
52 	int			sc_apicid;
53 	int			sc_apic_vers;
54 	int			sc_apic_vecbase; /* global int base if ACPI */
55 	int			sc_apic_sz;	/* apic size*/
56 	int			sc_flags;
57 	paddr_t			sc_pa;		/* PA of ioapic */
58 	volatile u_int32_t	*sc_reg;	/* KVA of ioapic addr */
59 	volatile u_int32_t	*sc_data;	/* KVA of ioapic data */
60 	struct ioapic_pin	*sc_pins;	/* sc_apic_sz entries */
61 };
62 
63 /*
64  * MP: intr_handle_t is bitfielded.
65  * ih&0xff -> legacy irq number.
66  * ih&0x10000000 -> if 0, old-style isa irq; if 1, routed via ioapic.
67  * (ih&0xff0000)>>16 -> ioapic id.
68  * (ih&0x00ff00)>>8 -> ioapic pin.
69  */
70 
71 #define APIC_INT_VIA_APIC	0x10000000
72 #define APIC_INT_VIA_MSG	0x20000000
73 #define APIC_INT_VIA_MSGX	0x40000000
74 #define APIC_INT_APIC_MASK	0x00ff0000
75 #define APIC_INT_APIC_SHIFT	16
76 #define APIC_INT_PIN_MASK	0x0000ff00
77 #define APIC_INT_PIN_SHIFT	8
78 
79 #define APIC_IRQ_APIC(x) ((x & APIC_INT_APIC_MASK) >> APIC_INT_APIC_SHIFT)
80 #define APIC_IRQ_PIN(x) ((x & APIC_INT_PIN_MASK) >> APIC_INT_PIN_SHIFT)
81 #define APIC_IRQ_ISLEGACY(x) (!((x) & APIC_INT_VIA_APIC))
82 #define APIC_IRQ_LEGACY_IRQ(x) ((x) & 0xff)
83 
84 void *apic_intr_establish(int, int, int, int (*)(void *), void *);
85 void apic_intr_disestablish(void *);
86 
87 void ioapic_print_redir(struct ioapic_softc *, char *, int);
88 void ioapic_format_redir(char *, char *, int, u_int32_t, u_int32_t);
89 struct ioapic_softc *ioapic_find(int);
90 struct ioapic_softc *ioapic_find_bybase(int);
91 
92 void ioapic_enable(void);
93 void lapic_vectorset(void); /* XXX */
94 
95 extern int ioapic_bsp_id;
96 extern int nioapics;
97 extern struct ioapic_softc *ioapics;
98 
99 #endif /* !_MACHINE_I82093VAR_H_ */
100