1 /* $OpenBSD: intrdefs.h,v 1.2 2004/06/25 17:27:01 andreas Exp $ */ 2 /* $NetBSD: intrdefs.h,v 1.2 2003/05/04 22:01:56 fvdl Exp $ */ 3 4 #ifndef _i386_INTRDEFS_H 5 #define _i386_INTRDEFS_H 6 7 /* 8 * Interrupt priority levels. 9 * 10 * There are tty, network and disk drivers that use free() at interrupt 11 * time, so imp > (tty | net | bio). 12 * 13 * Since run queues may be manipulated by both the statclock and tty, 14 * network, and disk drivers, clock > imp. 15 * 16 * IPL_HIGH must block everything that can manipulate a run queue. 17 * 18 * We need serial drivers to run at the absolute highest priority to 19 * avoid overruns, so serial > high. 20 * 21 * The level numbers are picked to fit into APIC vector priorities. 22 * 23 */ 24 #define IPL_NONE 0x0 /* nothing */ 25 #define IPL_SOFTCLOCK 0x4 /* timeouts */ 26 #define IPL_SOFTNET 0x5 /* protocol stacks */ 27 #define IPL_BIO 0x6 /* block I/O */ 28 #define IPL_NET 0x7 /* network */ 29 #define IPL_SOFTSERIAL 0x8 /* serial */ 30 #define IPL_TTY 0x9 /* terminal */ 31 #define IPL_VM 0xa /* memory allocation */ 32 #define IPL_IMP IPL_VM 33 #define IPL_AUDIO 0xb /* audio */ 34 #define IPL_CLOCK 0xc /* clock */ 35 #define IPL_SCHED IPL_CLOCK 36 #define IPL_STATCLOCK IPL_CLOCK 37 #define IPL_HIGH 0xd /* everything */ 38 #define IPL_SERIAL 0xd /* serial */ 39 #define IPL_IPI 0xe /* inter-processor interrupts */ 40 #define NIPL 16 41 42 /* Interrupt sharing types. */ 43 #define IST_NONE 0 /* none */ 44 #define IST_PULSE 1 /* pulsed */ 45 #define IST_EDGE 2 /* edge-triggered */ 46 #define IST_LEVEL 3 /* level-triggered */ 47 48 /* 49 * Local APIC masks. Must not conflict with SIR_* above, and must 50 * be >= NUM_LEGACY_IRQs. Note that LIR_IPI must be first. 51 */ 52 #define LIR_IPI 31 53 #define LIR_TIMER 30 54 55 /* Soft interrupt masks. */ 56 #define SIR_CLOCK 29 57 #define SIR_NET 28 58 #define SIR_SERIAL 27 59 60 61 /* 62 * Maximum # of interrupt sources per CPU. 32 to fit in one word. 63 * ioapics can theoretically produce more, but it's not likely to 64 * happen. For multiple ioapics, things can be routed to different 65 * CPUs. 66 */ 67 #define MAX_INTR_SOURCES 32 68 #define NUM_LEGACY_IRQS 16 69 70 /* 71 * Low and high boundaries between which interrupt gates will 72 * be allocated in the IDT. 73 */ 74 #define IDT_INTR_LOW (0x20 + NUM_LEGACY_IRQS) 75 #define IDT_INTR_HIGH 0xef 76 77 #define X86_IPI_HALT 0x00000001 78 #define X86_IPI_MICROSET 0x00000002 79 #define X86_IPI_FLUSH_FPU 0x00000004 80 #define X86_IPI_SYNCH_FPU 0x00000008 81 #define X86_IPI_TLB 0x00000010 82 #define X86_IPI_MTRR 0x00000020 83 #define X86_IPI_GDT 0x00000040 84 #define X86_IPI_DDB 0x00000080 85 86 #define X86_NIPI 8 87 88 #define X86_IPI_NAMES { "halt IPI", "timeset IPI", "FPU flush IPI", \ 89 "FPU synch IPI", "TLB shootdown IPI", \ 90 "MTRR update IPI", "GDT update IPI", "ddb IPI" } 91 92 #define IREENT_MAGIC 0x18041969 93 94 #endif /* _X86_INTRDEFS_H */ 95