1 /* $OpenBSD: intrdefs.h,v 1.11 2013/06/01 22:22:13 mlarkin Exp $ */ 2 /* $NetBSD: intrdefs.h,v 1.2 2003/05/04 22:01:56 fvdl Exp $ */ 3 4 #ifndef _AMD64_INTRDEFS_H 5 #define _AMD64_INTRDEFS_H 6 7 /* 8 * Interrupt priority levels. 9 * 10 * There are tty, network and disk drivers that use free() at interrupt 11 * time, so imp > (tty | net | bio). 12 * 13 * Since run queues may be manipulated by both the statclock and tty, 14 * network, and disk drivers, clock > imp. 15 * 16 * IPL_HIGH must block everything that can manipulate a run queue. 17 * 18 * The level numbers are picked to fit into APIC vector priorities. 19 * 20 */ 21 #define IPL_NONE 0x0 /* nothing */ 22 #define IPL_SOFTCLOCK 0x4 /* timeouts */ 23 #define IPL_SOFTNET 0x5 /* protocol stacks */ 24 #define IPL_BIO 0x6 /* block I/O */ 25 #define IPL_NET 0x7 /* network */ 26 #define IPL_SOFTTTY 0x8 /* delayed terminal handling */ 27 #define IPL_TTY 0x9 /* terminal */ 28 #define IPL_VM 0xa /* memory allocation */ 29 #define IPL_AUDIO 0xb /* audio */ 30 #define IPL_CLOCK 0xc /* clock */ 31 #define IPL_SCHED IPL_CLOCK 32 #define IPL_STATCLOCK IPL_CLOCK 33 #define IPL_HIGH 0xd /* everything */ 34 #define IPL_IPI 0xe /* inter-processor interrupts */ 35 #define NIPL 16 36 37 #define IPL_MPSAFE 0x100 38 39 /* Interrupt sharing types. */ 40 #define IST_NONE 0 /* none */ 41 #define IST_PULSE 1 /* pulsed */ 42 #define IST_EDGE 2 /* edge-triggered */ 43 #define IST_LEVEL 3 /* level-triggered */ 44 45 /* 46 * Local APIC masks. Must not conflict with SIR_* above, and must 47 * be >= NUM_LEGACY_IRQs. Note that LIR_IPI must be first. 48 */ 49 #define LIR_IPI 63 50 #define LIR_TIMER 62 51 52 /* Soft interrupt masks. */ 53 #define SIR_CLOCK 61 54 #define SIR_NET 60 55 #define SIR_TTY 59 56 57 58 /* 59 * Maximum # of interrupt sources per CPU. 64 to fit in one word. 60 * ioapics can theoretically produce more, but it's not likely to 61 * happen. For multiple ioapics, things can be routed to different 62 * CPUs. 63 */ 64 #define MAX_INTR_SOURCES 64 65 #define NUM_LEGACY_IRQS 16 66 67 /* 68 * Low and high boundaries between which interrupt gates will 69 * be allocated in the IDT. 70 */ 71 #define IDT_INTR_LOW (0x20 + NUM_LEGACY_IRQS) 72 #define IDT_INTR_HIGH 0xef 73 74 #define X86_IPI_HALT 0x00000001 75 #define X86_IPI_NOP 0x00000002 76 #define X86_IPI_FLUSH_FPU 0x00000004 77 #define X86_IPI_SYNCH_FPU 0x00000008 78 #define X86_IPI_TLB 0x00000010 79 #define X86_IPI_MTRR 0x00000020 80 #define X86_IPI_SETPERF 0x00000040 81 #define X86_IPI_DDB 0x00000080 82 #define X86_IPI_HALT_REALMODE 0x00000100 83 84 #define X86_NIPI 9 85 86 #define X86_IPI_NAMES { "halt IPI", "nop IPI", "FPU flush IPI", \ 87 "FPU synch IPI", "TLB shootdown IPI", \ 88 "MTRR update IPI", "setperf IPI", "ddb IPI", \ 89 "realmode halt IPI" } 90 91 #define IREENT_MAGIC 0x18041969 92 93 #endif /* _AMD64_INTRDEFS_H */ 94