1 /* $OpenBSD: specialreg.h,v 1.24 2012/11/10 09:45:05 mglocker Exp $ */ 2 /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */ 3 /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */ 4 5 /*- 6 * Copyright (c) 1991 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 34 */ 35 36 /* 37 * Bits in 386 special registers: 38 */ 39 #define CR0_PE 0x00000001 /* Protected mode Enable */ 40 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 41 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 44 #define CR0_PG 0x80000000 /* PaGing enable */ 45 46 /* 47 * Bits in 486 special registers: 48 */ 49 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 50 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52 #define CR0_NW 0x20000000 /* Not Write-through */ 53 #define CR0_CD 0x40000000 /* Cache Disable */ 54 55 /* 56 * Cyrix 486 DLC special registers, accessible as IO ports. 57 */ 58 #define CCR0 0xc0 /* configuration control register 0 */ 59 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 60 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 61 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 62 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 63 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 64 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 65 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 66 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 67 68 #define CCR1 0xc1 /* configuration control register 1 */ 69 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 70 /* the remaining 7 bits of this register are reserved */ 71 72 /* 73 * bits in the pentiums %cr4 register: 74 */ 75 76 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 77 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 78 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */ 79 #define CR4_DE 0x00000008 /* debugging extension */ 80 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 81 #define CR4_PAE 0x00000020 /* physical address extension enable */ 82 #define CR4_MCE 0x00000040 /* machine check enable */ 83 #define CR4_PGE 0x00000080 /* page global enable */ 84 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 85 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 86 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 87 #define CR4_VMXE 0x00002000 /* enable virtual machine operation */ 88 #define CR4_SMXE 0x00004000 /* enable safe mode operation */ 89 #define CR4_PCIDE 0x00020000 /* enable process-context IDs */ 90 #define CR4_OSXSAVE 0x00040000 /* enable XSAVE and extended states */ 91 #define CR4_SMEP 0x00100000 /* supervisor mode exec protection */ 92 #define CR4_SMAP 0x00200000 /* supervisor mode access prevention */ 93 94 /* 95 * CPUID "features" bits (CPUID function 0x1): 96 * EDX bits, then ECX bits 97 */ 98 99 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 100 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 101 #define CPUID_DE 0x00000004 /* has debugging extension */ 102 #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ 103 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 104 #define CPUID_MSR 0x00000020 /* has mode specific registers */ 105 #define CPUID_PAE 0x00000040 /* has phys address extension */ 106 #define CPUID_MCE 0x00000080 /* has machine check exception */ 107 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 108 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 109 #define CPUID_SYS1 0x00000400 /* has SYSCALL/SYSRET inst. (Cyrix) */ 110 #define CPUID_SEP 0x00000800 /* has SYSCALL/SYSRET inst. (AMD/Intel) */ 111 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 112 #define CPUID_PGE 0x00002000 /* has page global extension */ 113 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 114 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 115 #define CPUID_PAT 0x00010000 /* has page attribute table */ 116 #define CPUID_PSE36 0x00020000 /* has 36bit page size extension */ 117 #define CPUID_PSN 0x00040000 /* has processor serial number */ 118 #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */ 119 #define CPUID_B20 0x00100000 /* reserved */ 120 #define CPUID_DS 0x00200000 /* Debug Store */ 121 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 122 #define CPUID_MMX 0x00800000 /* has MMX instructions */ 123 #define CPUID_FXSR 0x01000000 /* has FXRSTOR instruction */ 124 #define CPUID_SSE 0x02000000 /* has streaming SIMD extensions */ 125 #define CPUID_SSE2 0x04000000 /* has streaming SIMD extensions #2 */ 126 #define CPUID_SS 0x08000000 /* self-snoop */ 127 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 128 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 129 #define CPUID_B30 0x40000000 /* reserved */ 130 #define CPUID_PBE 0x80000000 /* Pending Break Enabled restarts clock */ 131 132 #define CPUIDECX_SSE3 0x00000001 /* streaming SIMD extensions #3 */ 133 #define CPUIDECX_PCLMUL 0x00000002 /* Carryless Multiplication */ 134 #define CPUIDECX_DTES64 0x00000004 /* 64bit debug store */ 135 #define CPUIDECX_MWAIT 0x00000008 /* Monitor/Mwait */ 136 #define CPUIDECX_DSCPL 0x00000010 /* CPL Qualified Debug Store */ 137 #define CPUIDECX_VMX 0x00000020 /* Virtual Machine Extensions */ 138 #define CPUIDECX_SMX 0x00000040 /* Safer Mode Extensions */ 139 #define CPUIDECX_EST 0x00000080 /* enhanced SpeedStep */ 140 #define CPUIDECX_TM2 0x00000100 /* thermal monitor 2 */ 141 #define CPUIDECX_SSSE3 0x00000200 /* Supplemental Streaming SIMD Ext. 3 */ 142 #define CPUIDECX_CNXTID 0x00000400 /* Context ID */ 143 #define CPUIDECX_FMA3 0x00001000 /* Fused Multiply Add */ 144 #define CPUIDECX_CX16 0x00002000 /* has CMPXCHG16B instruction */ 145 #define CPUIDECX_XTPR 0x00004000 /* xTPR Update Control */ 146 #define CPUIDECX_PDCM 0x00008000 /* Perfmon and Debug Capability */ 147 #define CPUIDECX_PCID 0x00020000 /* Process-context ID Capability */ 148 #define CPUIDECX_DCA 0x00040000 /* Direct Cache Access */ 149 #define CPUIDECX_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ 150 #define CPUIDECX_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ 151 #define CPUIDECX_X2APIC 0x00200000 /* Extended xAPIC Support */ 152 #define CPUIDECX_MOVBE 0x00400000 /* MOVBE Instruction */ 153 #define CPUIDECX_POPCNT 0x00800000 /* POPCNT Instruction */ 154 #define CPUIDECX_DEADLINE 0x01000000 /* APIC one-shot via deadline */ 155 #define CPUIDECX_AES 0x02000000 /* AES Instruction */ 156 #define CPUIDECX_XSAVE 0x04000000 /* XSAVE/XSTOR States */ 157 #define CPUIDECX_OSXSAVE 0x08000000 /* OSXSAVE */ 158 #define CPUIDECX_AVX 0x10000000 /* Advanced Vector Extensions */ 159 #define CPUIDECX_F16C 0x20000000 /* 16bit fp conversion */ 160 #define CPUIDECX_RDRAND 0x40000000 /* RDRAND instruction */ 161 162 /* 163 * "Structured Extended Feature Flags Parameters" (CPUID function 0x7, leaf 0) 164 * EBX bits 165 */ 166 167 #define SEFF0EBX_FSGSBASE 0x00000001 /* {RD,WR}[FG]SBASE instructions */ 168 #define SEFF0EBX_BMI1 0x00000008 /* advanced bit manipulation */ 169 #define SEFF0EBX_HLE 0x00000010 /* Hardware Lock Elision */ 170 #define SEFF0EBX_AVX2 0x00000020 /* Advanced Vector Extensions 2 */ 171 #define SEFF0EBX_SMEP 0x00000080 /* Supervisor mode exec protection */ 172 #define SEFF0EBX_BMI2 0x00000100 /* advanced bit manipulation */ 173 #define SEFF0EBX_ERMS 0x00000200 /* Enhanced REP MOVSB/STOSB */ 174 #define SEFF0EBX_INVPCID 0x00000400 /* INVPCID instruction */ 175 #define SEFF0EBX_RTM 0x00000800 /* Restricted Transactional Memory */ 176 #define SEFF0EBX_RDSEED 0x00040000 /* RDSEED instruction */ 177 #define SEFF0EBX_ADX 0x00080000 /* ADCX/ADOX instructions */ 178 #define SEFF0EBX_SMAP 0x00100000 /* Supervisor mode access prevent */ 179 180 /* 181 * "Architectural Performance Monitoring" bits (CPUID function 0x0a): 182 * EAX bits, EBX bits, EDX bits. 183 */ 184 185 #define CPUIDEAX_VERID 0x000000ff /* Version ID */ 186 #define CPUIDEAX_NUM_GC(cpuid) (((cpuid) >> 8) & 0x000000ff) 187 #define CPUIDEAX_BIT_GC(cpuid) (((cpuid) >> 16) & 0x000000ff) 188 #define CPUIDEAX_LEN_EBX(cpuid) (((cpuid) >> 24) & 0x000000ff) 189 190 #define CPUIDEBX_EVT_CORE (1 << 0) /* Core cycle */ 191 #define CPUIDEBX_EVT_INST (1 << 1) /* Instruction retired */ 192 #define CPUIDEBX_EVT_REFR (1 << 2) /* Reference cycles */ 193 #define CPUIDEBX_EVT_CACHE_REF (1 << 3) /* Last-level cache ref. */ 194 #define CPUIDEBX_EVT_CACHE_MIS (1 << 4) /* Last-level cache miss. */ 195 #define CPUIDEBX_EVT_BRANCH_INST (1 << 5) /* Branch instruction ret. */ 196 #define CPUIDEBX_EVT_BRANCH_MISP (1 << 6) /* Branch mispredict ret. */ 197 198 #define CPUIDEDX_NUM_FC(cpuid) (((cpuid) >> 0) & 0x0000001f) 199 #define CPUIDEDX_BIT_FC(cpuid) (((cpuid) >> 5) & 0x000000ff) 200 201 /* 202 * CPUID "extended features" bits (CPUID function 0x80000001): 203 * EDX bits, then ECX bits 204 */ 205 206 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 207 #define CPUID_NXE 0x00100000 /* No-Execute Extension */ 208 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 209 #define CPUID_FFXSR 0x02000000 /* fast FP/MMX save/restore */ 210 #define CPUID_LONG 0x20000000 /* long mode */ 211 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 212 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 213 214 #define CPUIDECX_LAHF 0x00000001 /* LAHF and SAHF instructions */ 215 #define CPUIDECX_CMPLEG 0x00000002 /* Core MP legacy mode */ 216 #define CPUIDECX_SVM 0x00000004 /* Secure Virtual Machine */ 217 #define CPUIDECX_EAPICSP 0x00000008 /* Extended APIC space */ 218 #define CPUIDECX_AMCR8 0x00000010 /* LOCK MOV CR0 means MOV CR8 */ 219 #define CPUIDECX_ABM 0x00000020 /* LZCNT instruction */ 220 #define CPUIDECX_SSE4A 0x00000040 /* SSE4-A instruction set */ 221 #define CPUIDECX_MASSE 0x00000080 /* Misaligned SSE mode */ 222 #define CPUIDECX_3DNOWP 0x00000100 /* 3DNowPrefetch */ 223 #define CPUIDECX_OSVW 0x00000200 /* OS visible workaround */ 224 #define CPUIDECX_IBS 0x00000400 /* Instruction based sampling */ 225 #define CPUIDECX_XOP 0x00000800 /* Extended operating support */ 226 #define CPUIDECX_SKINIT 0x00001000 /* SKINIT and STGI are supported */ 227 #define CPUIDECX_WDT 0x00002000 /* Watchdog timer */ 228 /* Reserved 0x00004000 */ 229 #define CPUIDECX_LWP 0x00008000 /* Lightweight profiling support */ 230 #define CPUIDECX_FMA4 0x00010000 /* 4-operand FMA instructions */ 231 /* Reserved 0x00020000 */ 232 /* Reserved 0x00040000 */ 233 #define CPUIDECX_NODEID 0x00080000 /* Support for MSRC001C */ 234 /* Reserved 0x00100000 */ 235 #define CPUIDECX_TBM 0x00200000 /* Trailing bit manipulation instruction */ 236 #define CPUIDECX_TOPEXT 0x00400000 /* Topology extensions support */ 237 238 /* 239 * "Advanced Power Management Information" bits (CPUID function 0x80000007): 240 * EDX bits. 241 */ 242 243 #define CPUIDEDX_ITSC (1 << 8) /* Invariant TSC */ 244 245 #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 15) 246 #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 15) 247 #define CPUID2STEPPING(cpuid) ((cpuid) & 15) 248 249 #define CPUID(code, eax, ebx, ecx, edx) \ 250 __asm("cpuid" \ 251 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \ 252 : "a" (code)); 253 #define CPUID_LEAF(code, leaf, eax, ebx, ecx, edx) \ 254 __asm("cpuid" \ 255 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \ 256 : "a" (code), "c" (leaf)); 257 258 259 /* 260 * Model-specific registers for the i386 family 261 */ 262 #define MSR_P5_MC_ADDR 0x000 /* P5 only */ 263 #define MSR_P5_MC_TYPE 0x001 /* P5 only */ 264 #define MSR_TSC 0x010 265 #define MSR_CESR 0x011 /* P5 only (trap on P6) */ 266 #define MSR_CTR0 0x012 /* P5 only (trap on P6) */ 267 #define MSR_CTR1 0x013 /* P5 only (trap on P6) */ 268 #define MSR_APICBASE 0x01b 269 #define MSR_EBL_CR_POWERON 0x02a 270 #define MSR_EBC_FREQUENCY_ID 0x02c /* Pentium 4 only */ 271 #define MSR_TEST_CTL 0x033 272 #define MSR_BIOS_UPDT_TRIG 0x079 273 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ 274 #define MSR_BBL_CR_D1 0x089 /* PII+ only */ 275 #define MSR_BBL_CR_D2 0x08a /* PII+ only */ 276 #define MSR_BIOS_SIGN 0x08b 277 #define MSR_PERFCTR0 0x0c1 278 #define MSR_PERFCTR1 0x0c2 279 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 280 /* not documented anywhere, see intelcore_update_sensor() */ 281 #define MSR_TEMPERATURE_TARGET 0x0ee 282 #define MSR_TEMPERATURE_TARGET_LOW_BIT 0x40000000 283 #define MSR_MTRRcap 0x0fe 284 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ 285 #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ 286 #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ 287 #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ 288 #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ 289 #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ 290 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 291 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 292 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 293 #define MSR_MCG_CAP 0x179 294 #define MSR_MCG_STATUS 0x17a 295 #define MSR_MCG_CTL 0x17b 296 #define MSR_EVNTSEL0 0x186 297 #define MSR_EVNTSEL1 0x187 298 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 299 #define MSR_PERF_CTL 0x199 /* Pentium M */ 300 #define MSR_THERM_CONTROL 0x19a 301 #define MSR_THERM_INTERRUPT 0x19b 302 #define MSR_THERM_STATUS 0x19c 303 #define MSR_THERM_STATUS_VALID_BIT 0x80000000 304 #define MSR_THERM_STATUS_TEMP(msr) ((msr >> 16) & 0x7f) 305 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 306 #define MSR_DEBUGCTLMSR 0x1d9 307 #define MSR_LASTBRANCHFROMIP 0x1db 308 #define MSR_LASTBRANCHTOIP 0x1dc 309 #define MSR_LASTINTFROMIP 0x1dd 310 #define MSR_LASTINTTOIP 0x1de 311 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 312 #define MSR_MTRRphysBase0 0x200 313 #define MSR_MTRRphysMask0 0x201 314 #define MSR_MTRRphysBase1 0x202 315 #define MSR_MTRRphysMask1 0x203 316 #define MSR_MTRRphysBase2 0x204 317 #define MSR_MTRRphysMask2 0x205 318 #define MSR_MTRRphysBase3 0x206 319 #define MSR_MTRRphysMask3 0x207 320 #define MSR_MTRRphysBase4 0x208 321 #define MSR_MTRRphysMask4 0x209 322 #define MSR_MTRRphysBase5 0x20a 323 #define MSR_MTRRphysMask5 0x20b 324 #define MSR_MTRRphysBase6 0x20c 325 #define MSR_MTRRphysMask6 0x20d 326 #define MSR_MTRRphysBase7 0x20e 327 #define MSR_MTRRphysMask7 0x20f 328 #define MSR_MTRRfix64K_00000 0x250 329 #define MSR_MTRRfix16K_80000 0x258 330 #define MSR_MTRRfix16K_A0000 0x259 331 #define MSR_MTRRfix4K_C0000 0x268 332 #define MSR_MTRRfix4K_C8000 0x269 333 #define MSR_MTRRfix4K_D0000 0x26a 334 #define MSR_MTRRfix4K_D8000 0x26b 335 #define MSR_MTRRfix4K_E0000 0x26c 336 #define MSR_MTRRfix4K_E8000 0x26d 337 #define MSR_MTRRfix4K_F0000 0x26e 338 #define MSR_MTRRfix4K_F8000 0x26f 339 #define MSR_CR_PAT 0x277 340 #define MSR_MTRRdefType 0x2ff 341 #define MSR_PERF_FIXED_CTR1 0x30a /* CPU_CLK_Unhalted.Core */ 342 #define MSR_PERF_FIXED_CTR2 0x30b /* CPU_CLK.Unhalted.Ref */ 343 #define MSR_PERF_FIXED_CTR_CTRL 0x38d 344 #define MSR_PERF_FIXED_CTR1_EN (1 << 4) 345 #define MSR_PERF_FIXED_CTR2_EN (1 << 8) 346 #define MSR_PERF_GLOBAL_CTRL 0x38f 347 #define MSR_PERF_GLOBAL_CTR1_EN (1ULL << 33) 348 #define MSR_PERF_GLOBAL_CTR2_EN (1ULL << 34) 349 #define MSR_MC0_CTL 0x400 350 #define MSR_MC0_STATUS 0x401 351 #define MSR_MC0_ADDR 0x402 352 #define MSR_MC0_MISC 0x403 353 #define MSR_MC1_CTL 0x404 354 #define MSR_MC1_STATUS 0x405 355 #define MSR_MC1_ADDR 0x406 356 #define MSR_MC1_MISC 0x407 357 #define MSR_MC2_CTL 0x408 358 #define MSR_MC2_STATUS 0x409 359 #define MSR_MC2_ADDR 0x40a 360 #define MSR_MC2_MISC 0x40b 361 #define MSR_MC4_CTL 0x40c 362 #define MSR_MC4_STATUS 0x40d 363 #define MSR_MC4_ADDR 0x40e 364 #define MSR_MC4_MISC 0x40f 365 #define MSR_MC3_CTL 0x410 366 #define MSR_MC3_STATUS 0x411 367 #define MSR_MC3_ADDR 0x412 368 #define MSR_MC3_MISC 0x413 369 370 /* VIA MSR */ 371 #define MSR_CENT_TMTEMPERATURE 0x1423 /* Thermal monitor temperature */ 372 373 /* 374 * AMD K6/K7 MSRs. 375 */ 376 #define MSR_K6_UWCCR 0xc0000085 377 #define MSR_K7_EVNTSEL0 0xc0010000 378 #define MSR_K7_EVNTSEL1 0xc0010001 379 #define MSR_K7_EVNTSEL2 0xc0010002 380 #define MSR_K7_EVNTSEL3 0xc0010003 381 #define MSR_K7_PERFCTR0 0xc0010004 382 #define MSR_K7_PERFCTR1 0xc0010005 383 #define MSR_K7_PERFCTR2 0xc0010006 384 #define MSR_K7_PERFCTR3 0xc0010007 385 386 /* 387 * AMD K8 (Opteron) MSRs. 388 */ 389 #define MSR_SYSCFG 0xc0000010 390 391 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 392 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 393 #define EFER_LME 0x00000100 /* Long Mode Active */ 394 #define EFER_LMA 0x00000400 /* Long Mode Enabled */ 395 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 396 397 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 398 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 399 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 400 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 401 402 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 403 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 404 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 405 #define MSR_INT_PEN_MSG 0xc0010055 /* Interrupt pending message */ 406 407 #define MSR_DE_CFG 0xc0011029 /* Decode Configuration */ 408 #define DE_CFG_721 0x00000001 /* errata 721 */ 409 410 #define IPM_C1E_CMP_HLT 0x10000000 411 #define IPM_SMI_CMP_HLT 0x08000000 412 413 /* 414 * These require a 'passcode' for access. See cpufunc.h. 415 */ 416 #define MSR_HWCR 0xc0010015 417 #define HWCR_FFDIS 0x00000040 418 419 #define MSR_NB_CFG 0xc001001f 420 #define NB_CFG_DISIOREQLOCK 0x0000000000000004ULL 421 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 422 423 #define MSR_LS_CFG 0xc0011020 424 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 425 426 #define MSR_IC_CFG 0xc0011021 427 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 428 429 #define MSR_DC_CFG 0xc0011022 430 #define DC_CFG_DIS_CNV_WC_SSO 0x00000004 431 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 432 433 #define MSR_BU_CFG 0xc0011023 434 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 435 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 436 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 437 438 /* 439 * Constants related to MTRRs 440 */ 441 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 442 #define MTRR_N16K 16 443 #define MTRR_N4K 64 444 445 /* 446 * the following four 3-byte registers control the non-cacheable regions. 447 * These registers must be written as three separate bytes. 448 * 449 * NCRx+0: A31-A24 of starting address 450 * NCRx+1: A23-A16 of starting address 451 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 452 * 453 * The non-cacheable region's starting address must be aligned to the 454 * size indicated by the NCR_SIZE_xx field. 455 */ 456 #define NCR1 0xc4 457 #define NCR2 0xc7 458 #define NCR3 0xca 459 #define NCR4 0xcd 460 461 #define NCR_SIZE_0K 0 462 #define NCR_SIZE_4K 1 463 #define NCR_SIZE_8K 2 464 #define NCR_SIZE_16K 3 465 #define NCR_SIZE_32K 4 466 #define NCR_SIZE_64K 5 467 #define NCR_SIZE_128K 6 468 #define NCR_SIZE_256K 7 469 #define NCR_SIZE_512K 8 470 #define NCR_SIZE_1M 9 471 #define NCR_SIZE_2M 10 472 #define NCR_SIZE_4M 11 473 #define NCR_SIZE_8M 12 474 #define NCR_SIZE_16M 13 475 #define NCR_SIZE_32M 14 476 #define NCR_SIZE_4G 15 477 478 /* 479 * Performance monitor events. 480 * 481 * Note that 586-class and 686-class CPUs have different performance 482 * monitors available, and they are accessed differently: 483 * 484 * 686-class: `rdpmc' instruction 485 * 586-class: `rdmsr' instruction, CESR MSR 486 * 487 * The descriptions of these events are too lenghy to include here. 488 * See Appendix A of "Intel Architecture Software Developer's 489 * Manual, Volume 3: System Programming" for more information. 490 */ 491 492 /* 493 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits 494 * is CTR1. 495 */ 496 497 #define PMC5_CESR_EVENT 0x003f 498 #define PMC5_CESR_OS 0x0040 499 #define PMC5_CESR_USR 0x0080 500 #define PMC5_CESR_E 0x0100 501 #define PMC5_CESR_P 0x0200 502 503 #define PMC5_DATA_READ 0x00 504 #define PMC5_DATA_WRITE 0x01 505 #define PMC5_DATA_TLB_MISS 0x02 506 #define PMC5_DATA_READ_MISS 0x03 507 #define PMC5_DATA_WRITE_MISS 0x04 508 #define PMC5_WRITE_M_E 0x05 509 #define PMC5_DATA_LINES_WBACK 0x06 510 #define PMC5_DATA_CACHE_SNOOP 0x07 511 #define PMC5_DATA_CACHE_SNOOP_HIT 0x08 512 #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09 513 #define PMC5_BANK_CONFLICTS 0x0a 514 #define PMC5_MISALIGNED_DATA 0x0b 515 #define PMC5_INST_READ 0x0c 516 #define PMC5_INST_TLB_MISS 0x0d 517 #define PMC5_INST_CACHE_MISS 0x0e 518 #define PMC5_SEGMENT_REG_LOAD 0x0f 519 #define PMC5_BRANCHES 0x12 520 #define PMC5_BTB_HITS 0x13 521 #define PMC5_BRANCH_TAKEN 0x14 522 #define PMC5_PIPELINE_FLUSH 0x15 523 #define PMC5_INST_EXECUTED 0x16 524 #define PMC5_INST_EXECUTED_V_PIPE 0x17 525 #define PMC5_BUS_UTILIZATION 0x18 526 #define PMC5_WRITE_BACKUP_STALL 0x19 527 #define PMC5_DATA_READ_STALL 0x1a 528 #define PMC5_WRITE_E_M_STALL 0x1b 529 #define PMC5_LOCKED_BUS 0x1c 530 #define PMC5_IO_CYCLE 0x1d 531 #define PMC5_NONCACHE_MEM_READ 0x1e 532 #define PMC5_AGI_STALL 0x1f 533 #define PMC5_FLOPS 0x22 534 #define PMC5_BP0_MATCH 0x23 535 #define PMC5_BP1_MATCH 0x24 536 #define PMC5_BP2_MATCH 0x25 537 #define PMC5_BP3_MATCH 0x26 538 #define PMC5_HARDWARE_INTR 0x27 539 #define PMC5_DATA_RW 0x28 540 #define PMC5_DATA_RW_MISS 0x29 541 542 /* 543 * 686-class Event Selector MSR format. 544 */ 545 546 #define PMC6_EVTSEL_EVENT 0x000000ff 547 #define PMC6_EVTSEL_UNIT 0x0000ff00 548 #define PMC6_EVTSEL_UNIT_SHIFT 8 549 #define PMC6_EVTSEL_USR (1 << 16) 550 #define PMC6_EVTSEL_OS (1 << 17) 551 #define PMC6_EVTSEL_E (1 << 18) 552 #define PMC6_EVTSEL_PC (1 << 19) 553 #define PMC6_EVTSEL_INT (1 << 20) 554 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ 555 #define PMC6_EVTSEL_INV (1 << 23) 556 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 557 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 558 559 /* Data Cache Unit */ 560 #define PMC6_DATA_MEM_REFS 0x43 561 #define PMC6_DCU_LINES_IN 0x45 562 #define PMC6_DCU_M_LINES_IN 0x46 563 #define PMC6_DCU_M_LINES_OUT 0x47 564 #define PMC6_DCU_MISS_OUTSTANDING 0x48 565 566 /* Instruction Fetch Unit */ 567 #define PMC6_IFU_IFETCH 0x80 568 #define PMC6_IFU_IFETCH_MISS 0x81 569 #define PMC6_ITLB_MISS 0x85 570 #define PMC6_IFU_MEM_STALL 0x86 571 #define PMC6_ILD_STALL 0x87 572 573 /* L2 Cache */ 574 #define PMC6_L2_IFETCH 0x28 575 #define PMC6_L2_LD 0x29 576 #define PMC6_L2_ST 0x2a 577 #define PMC6_L2_LINES_IN 0x24 578 #define PMC6_L2_LINES_OUT 0x26 579 #define PMC6_L2_M_LINES_INM 0x25 580 #define PMC6_L2_M_LINES_OUTM 0x27 581 #define PMC6_L2_RQSTS 0x2e 582 #define PMC6_L2_ADS 0x21 583 #define PMC6_L2_DBUS_BUSY 0x22 584 #define PMC6_L2_DBUS_BUSY_RD 0x23 585 586 /* External Bus Logic */ 587 #define PMC6_BUS_DRDY_CLOCKS 0x62 588 #define PMC6_BUS_LOCK_CLOCKS 0x63 589 #define PMC6_BUS_REQ_OUTSTANDING 0x60 590 #define PMC6_BUS_TRAN_BRD 0x65 591 #define PMC6_BUS_TRAN_RFO 0x66 592 #define PMC6_BUS_TRANS_WB 0x67 593 #define PMC6_BUS_TRAN_IFETCH 0x68 594 #define PMC6_BUS_TRAN_INVAL 0x69 595 #define PMC6_BUS_TRAN_PWR 0x6a 596 #define PMC6_BUS_TRANS_P 0x6b 597 #define PMC6_BUS_TRANS_IO 0x6c 598 #define PMC6_BUS_TRAN_DEF 0x6d 599 #define PMC6_BUS_TRAN_BURST 0x6e 600 #define PMC6_BUS_TRAN_ANY 0x70 601 #define PMC6_BUS_TRAN_MEM 0x6f 602 #define PMC6_BUS_DATA_RCV 0x64 603 #define PMC6_BUS_BNR_DRV 0x61 604 #define PMC6_BUS_HIT_DRV 0x7a 605 #define PMC6_BUS_HITM_DRDV 0x7b 606 #define PMC6_BUS_SNOOP_STALL 0x7e 607 608 /* Floating Point Unit */ 609 #define PMC6_FLOPS 0xc1 610 #define PMC6_FP_COMP_OPS_EXE 0x10 611 #define PMC6_FP_ASSIST 0x11 612 #define PMC6_MUL 0x12 613 #define PMC6_DIV 0x12 614 #define PMC6_CYCLES_DIV_BUSY 0x14 615 616 /* Memory Ordering */ 617 #define PMC6_LD_BLOCKS 0x03 618 #define PMC6_SB_DRAINS 0x04 619 #define PMC6_MISALIGN_MEM_REF 0x05 620 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ 621 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ 622 623 /* Instruction Decoding and Retirement */ 624 #define PMC6_INST_RETIRED 0xc0 625 #define PMC6_UOPS_RETIRED 0xc2 626 #define PMC6_INST_DECODED 0xd0 627 #define PMC6_EMON_KNI_INST_RETIRED 0xd8 628 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 629 630 /* Interrupts */ 631 #define PMC6_HW_INT_RX 0xc8 632 #define PMC6_CYCLES_INT_MASKED 0xc6 633 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 634 635 /* Branches */ 636 #define PMC6_BR_INST_RETIRED 0xc4 637 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 638 #define PMC6_BR_TAKEN_RETIRED 0xc9 639 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 640 #define PMC6_BR_INST_DECODED 0xe0 641 #define PMC6_BTB_MISSES 0xe2 642 #define PMC6_BR_BOGUS 0xe4 643 #define PMC6_BACLEARS 0xe6 644 645 /* Stalls */ 646 #define PMC6_RESOURCE_STALLS 0xa2 647 #define PMC6_PARTIAL_RAT_STALLS 0xd2 648 649 /* Segment Register Loads */ 650 #define PMC6_SEGMENT_REG_LOADS 0x06 651 652 /* Clocks */ 653 #define PMC6_CPU_CLK_UNHALTED 0x79 654 655 /* MMX Unit */ 656 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ 657 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ 658 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ 659 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ 660 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ 661 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ 662 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ 663 664 /* Segment Register Renaming */ 665 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ 666 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ 667 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ 668 669 /* 670 * AMD K7 Event Selector MSR format. 671 */ 672 673 #define K7_EVTSEL_EVENT 0x000000ff 674 #define K7_EVTSEL_UNIT 0x0000ff00 675 #define K7_EVTSEL_UNIT_SHIFT 8 676 #define K7_EVTSEL_USR (1 << 16) 677 #define K7_EVTSEL_OS (1 << 17) 678 #define K7_EVTSEL_E (1 << 18) 679 #define K7_EVTSEL_PC (1 << 19) 680 #define K7_EVTSEL_INT (1 << 20) 681 #define K7_EVTSEL_EN (1 << 22) 682 #define K7_EVTSEL_INV (1 << 23) 683 #define K7_EVTSEL_COUNTER_MASK 0xff000000 684 #define K7_EVTSEL_COUNTER_MASK_SHIFT 24 685 686 /* Segment Register Loads */ 687 #define K7_SEGMENT_REG_LOADS 0x20 688 689 #define K7_STORES_TO_ACTIVE_INST_STREAM 0x21 690 691 /* Data Cache Unit */ 692 #define K7_DATA_CACHE_ACCESS 0x40 693 #define K7_DATA_CACHE_MISS 0x41 694 #define K7_DATA_CACHE_REFILL 0x42 695 #define K7_DATA_CACHE_REFILL_SYSTEM 0x43 696 #define K7_DATA_CACHE_WBACK 0x44 697 #define K7_L2_DTLB_HIT 0x45 698 #define K7_L2_DTLB_MISS 0x46 699 #define K7_MISALIGNED_DATA_REF 0x47 700 #define K7_SYSTEM_REQUEST 0x64 701 #define K7_SYSTEM_REQUEST_TYPE 0x65 702 703 #define K7_SNOOP_HIT 0x73 704 #define K7_SINGLE_BIT_ECC_ERROR 0x74 705 #define K7_CACHE_LINE_INVAL 0x75 706 #define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76 707 #define K7_L2_REQUEST 0x79 708 #define K7_L2_REQUEST_BUSY 0x7a 709 710 /* Instruction Fetch Unit */ 711 #define K7_IFU_IFETCH 0x80 712 #define K7_IFU_IFETCH_MISS 0x81 713 #define K7_IFU_REFILL_FROM_L2 0x82 714 #define K7_IFU_REFILL_FROM_SYSTEM 0x83 715 #define K7_ITLB_L1_MISS 0x84 716 #define K7_ITLB_L2_MISS 0x85 717 #define K7_SNOOP_RESYNC 0x86 718 #define K7_IFU_STALL 0x87 719 720 #define K7_RETURN_STACK_HITS 0x88 721 #define K7_RETURN_STACK_OVERFLOW 0x89 722 723 /* Retired */ 724 #define K7_RETIRED_INST 0xc0 725 #define K7_RETIRED_OPS 0xc1 726 #define K7_RETIRED_BRANCHES 0xc2 727 #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3 728 #define K7_RETIRED_TAKEN_BRANCH 0xc4 729 #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5 730 #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6 731 #define K7_RETIRED_RESYNC_BRANCH 0xc7 732 #define K7_RETIRED_NEAR_RETURNS 0xc8 733 #define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9 734 #define K7_RETIRED_INDIRECT_MISPREDICTED 0xca 735 736 /* Interrupts */ 737 #define K7_CYCLES_INT_MASKED 0xcd 738 #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce 739 #define K7_HW_INTR_RECV 0xcf 740 741 #define K7_INSTRUCTION_DECODER_EMPTY 0xd0 742 #define K7_DISPATCH_STALLS 0xd1 743 #define K7_BRANCH_ABORTS_TO_RETIRE 0xd2 744 #define K7_SERIALIZE 0xd3 745 #define K7_SEGMENT_LOAD_STALL 0xd4 746 #define K7_ICU_FULL 0xd5 747 #define K7_RESERVATION_STATIONS_FULL 0xd6 748 #define K7_FPU_FULL 0xd7 749 #define K7_LS_FULL 0xd8 750 #define K7_ALL_QUIET_STALL 0xd9 751 #define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda 752 753 #define K7_BP0_MATCH 0xdc 754 #define K7_BP1_MATCH 0xdd 755 #define K7_BP2_MATCH 0xde 756 #define K7_BP3_MATCH 0xdf 757 758 /* VIA C3 crypto featureset: for i386_has_xcrypt */ 759 #define C3_HAS_AES 1 /* cpu has AES */ 760 #define C3_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 761 #define C3_HAS_MM 4 /* cpu has RSA instructions */ 762 #define C3_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 763 764 /* Centaur Extended Feature flags */ 765 #define C3_CPUID_HAS_RNG 0x000004 766 #define C3_CPUID_DO_RNG 0x000008 767 #define C3_CPUID_HAS_ACE 0x000040 768 #define C3_CPUID_DO_ACE 0x000080 769 #define C3_CPUID_HAS_ACE2 0x000100 770 #define C3_CPUID_DO_ACE2 0x000200 771 #define C3_CPUID_HAS_PHE 0x000400 772 #define C3_CPUID_DO_PHE 0x000800 773 #define C3_CPUID_HAS_PMM 0x001000 774 #define C3_CPUID_DO_PMM 0x002000 775 776 /* VIA C3 xcrypt-* instruction context control options */ 777 #define C3_CRYPT_CWLO_ROUND_M 0x0000000f 778 #define C3_CRYPT_CWLO_ALG_M 0x00000070 779 #define C3_CRYPT_CWLO_ALG_AES 0x00000000 780 #define C3_CRYPT_CWLO_KEYGEN_M 0x00000080 781 #define C3_CRYPT_CWLO_KEYGEN_HW 0x00000000 782 #define C3_CRYPT_CWLO_KEYGEN_SW 0x00000080 783 #define C3_CRYPT_CWLO_NORMAL 0x00000000 784 #define C3_CRYPT_CWLO_INTERMEDIATE 0x00000100 785 #define C3_CRYPT_CWLO_ENCRYPT 0x00000000 786 #define C3_CRYPT_CWLO_DECRYPT 0x00000200 787 #define C3_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 788 #define C3_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 789 #define C3_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 790