1 /* $OpenBSD: pci_machdep.c,v 1.75 2020/06/17 06:14:52 dlg Exp $ */ 2 /* $NetBSD: pci_machdep.c,v 1.3 2003/05/07 21:33:58 fvdl Exp $ */ 3 4 /*- 5 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Charles M. Hannum. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Machine-specific functions for PCI autoconfiguration. 66 */ 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/extent.h> 71 #include <sys/malloc.h> 72 73 #include <machine/bus.h> 74 75 #include <machine/pio.h> 76 #include <machine/intr.h> 77 #include <machine/biosvar.h> 78 79 #include <dev/isa/isareg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcireg.h> 82 #include <dev/pci/pcidevs.h> 83 #include <dev/pci/ppbreg.h> 84 85 #include "ioapic.h" 86 87 #if NIOAPIC > 0 88 #include <machine/i82093var.h> 89 #include <machine/mpbiosvar.h> 90 #endif 91 92 /* 93 * Memory Mapped Configuration space access. 94 * 95 * Since mapping the whole configuration space will cost us up to 96 * 256MB of kernel virtual memory, we use seperate mappings per bus. 97 * The mappings are created on-demand, such that we only use kernel 98 * virtual memory for busses that are actually present. 99 */ 100 bus_addr_t pci_mcfg_addr; 101 int pci_mcfg_min_bus, pci_mcfg_max_bus; 102 bus_space_tag_t pci_mcfgt; 103 bus_space_handle_t pci_mcfgh[256]; 104 105 struct mutex pci_conf_lock = MUTEX_INITIALIZER(IPL_HIGH); 106 107 #define PCI_CONF_LOCK() \ 108 do { \ 109 mtx_enter(&pci_conf_lock); \ 110 } while (0) 111 112 #define PCI_CONF_UNLOCK() \ 113 do { \ 114 mtx_leave(&pci_conf_lock); \ 115 } while (0) 116 117 #define PCI_MODE1_ENABLE 0x80000000UL 118 #define PCI_MODE1_ADDRESS_REG 0x0cf8 119 #define PCI_MODE1_DATA_REG 0x0cfc 120 121 /* 122 * PCI doesn't have any special needs; just use the generic versions 123 * of these functions. 124 */ 125 struct bus_dma_tag pci_bus_dma_tag = { 126 NULL, /* _may_bounce */ 127 _bus_dmamap_create, 128 _bus_dmamap_destroy, 129 _bus_dmamap_load, 130 _bus_dmamap_load_mbuf, 131 _bus_dmamap_load_uio, 132 _bus_dmamap_load_raw, 133 _bus_dmamap_unload, 134 _bus_dmamap_sync, 135 _bus_dmamem_alloc, 136 _bus_dmamem_alloc_range, 137 _bus_dmamem_free, 138 _bus_dmamem_map, 139 _bus_dmamem_unmap, 140 _bus_dmamem_mmap, 141 }; 142 143 void 144 pci_mcfg_init(bus_space_tag_t iot, bus_addr_t addr, int segment, 145 int min_bus, int max_bus) 146 { 147 if (segment == 0) { 148 pci_mcfgt = iot; 149 pci_mcfg_addr = addr; 150 pci_mcfg_min_bus = min_bus; 151 pci_mcfg_max_bus = max_bus; 152 } 153 } 154 155 pci_chipset_tag_t 156 pci_lookup_segment(int segment) 157 { 158 KASSERT(segment == 0); 159 return NULL; 160 } 161 162 void 163 pci_attach_hook(struct device *parent, struct device *self, 164 struct pcibus_attach_args *pba) 165 { 166 } 167 168 int 169 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 170 { 171 return (32); 172 } 173 174 pcitag_t 175 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 176 { 177 if (bus >= 256 || device >= 32 || function >= 8) 178 panic("pci_make_tag: bad request"); 179 180 return (PCI_MODE1_ENABLE | 181 (bus << 16) | (device << 11) | (function << 8)); 182 } 183 184 void 185 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp) 186 { 187 if (bp != NULL) 188 *bp = (tag >> 16) & 0xff; 189 if (dp != NULL) 190 *dp = (tag >> 11) & 0x1f; 191 if (fp != NULL) 192 *fp = (tag >> 8) & 0x7; 193 } 194 195 int 196 pci_conf_size(pci_chipset_tag_t pc, pcitag_t tag) 197 { 198 int bus; 199 200 if (pci_mcfg_addr) { 201 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 202 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) 203 return PCIE_CONFIG_SPACE_SIZE; 204 } 205 206 return PCI_CONFIG_SPACE_SIZE; 207 } 208 209 void 210 pci_mcfg_map_bus(int bus) 211 { 212 if (pci_mcfgh[bus]) 213 return; 214 215 if (bus_space_map(pci_mcfgt, pci_mcfg_addr + (bus << 20), 1 << 20, 216 0, &pci_mcfgh[bus])) 217 panic("pci_conf_read: cannot map mcfg space"); 218 } 219 220 pcireg_t 221 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 222 { 223 pcireg_t data; 224 int bus; 225 226 KASSERT((reg & 0x3) == 0); 227 228 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) { 229 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 230 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) { 231 pci_mcfg_map_bus(bus); 232 data = bus_space_read_4(pci_mcfgt, pci_mcfgh[bus], 233 (tag & 0x000ff00) << 4 | reg); 234 return data; 235 } 236 } 237 238 PCI_CONF_LOCK(); 239 outl(PCI_MODE1_ADDRESS_REG, tag | reg); 240 data = inl(PCI_MODE1_DATA_REG); 241 outl(PCI_MODE1_ADDRESS_REG, 0); 242 PCI_CONF_UNLOCK(); 243 244 return data; 245 } 246 247 void 248 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 249 { 250 int bus; 251 252 KASSERT((reg & 0x3) == 0); 253 254 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) { 255 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 256 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) { 257 pci_mcfg_map_bus(bus); 258 bus_space_write_4(pci_mcfgt, pci_mcfgh[bus], 259 (tag & 0x000ff00) << 4 | reg, data); 260 return; 261 } 262 } 263 264 PCI_CONF_LOCK(); 265 outl(PCI_MODE1_ADDRESS_REG, tag | reg); 266 outl(PCI_MODE1_DATA_REG, data); 267 outl(PCI_MODE1_ADDRESS_REG, 0); 268 PCI_CONF_UNLOCK(); 269 } 270 271 int 272 pci_msix_table_map(pci_chipset_tag_t pc, pcitag_t tag, 273 bus_space_tag_t memt, bus_space_handle_t *memh) 274 { 275 bus_addr_t base; 276 pcireg_t reg, table, type; 277 int bir, offset; 278 int off, tblsz; 279 280 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0) 281 panic("%s: no msix capability", __func__); 282 283 table = pci_conf_read(pc, tag, off + PCI_MSIX_TABLE); 284 bir = (table & PCI_MSIX_TABLE_BIR); 285 offset = (table & PCI_MSIX_TABLE_OFF); 286 tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1; 287 288 bir = PCI_MAPREG_START + bir * 4; 289 type = pci_mapreg_type(pc, tag, bir); 290 if (pci_mapreg_info(pc, tag, bir, type, &base, NULL, NULL) || 291 _bus_space_map(memt, base + offset, tblsz * 16, 0, memh)) 292 return -1; 293 294 return 0; 295 } 296 297 void 298 pci_msix_table_unmap(pci_chipset_tag_t pc, pcitag_t tag, 299 bus_space_tag_t memt, bus_space_handle_t memh) 300 { 301 pcireg_t reg; 302 int tblsz; 303 304 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0) 305 panic("%s: no msix capability", __func__); 306 307 tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1; 308 _bus_space_unmap(memt, memh, tblsz * 16, NULL); 309 } 310 311 void msi_hwmask(struct pic *, int); 312 void msi_hwunmask(struct pic *, int); 313 void msi_addroute(struct pic *, struct cpu_info *, int, int, int); 314 void msi_delroute(struct pic *, struct cpu_info *, int, int, int); 315 316 struct pic msi_pic = { 317 {0, {NULL}, NULL, 0, "msi", NULL, 0, 0}, 318 PIC_MSI, 319 #ifdef MULTIPROCESSOR 320 {}, 321 #endif 322 msi_hwmask, 323 msi_hwunmask, 324 msi_addroute, 325 msi_delroute, 326 NULL, 327 ioapic_edge_stubs 328 }; 329 330 void 331 msi_hwmask(struct pic *pic, int pin) 332 { 333 } 334 335 void 336 msi_hwunmask(struct pic *pic, int pin) 337 { 338 } 339 340 void 341 msi_addroute(struct pic *pic, struct cpu_info *ci, int pin, int vec, int type) 342 { 343 pci_chipset_tag_t pc = NULL; /* XXX */ 344 pcitag_t tag = pin; 345 pcireg_t reg, addr; 346 int off; 347 348 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0) 349 panic("%s: no msi capability", __func__); 350 351 addr = 0xfee00000UL | (ci->ci_apicid << 12); 352 353 if (reg & PCI_MSI_MC_C64) { 354 pci_conf_write(pc, tag, off + PCI_MSI_MA, addr); 355 pci_conf_write(pc, tag, off + PCI_MSI_MAU32, 0); 356 pci_conf_write(pc, tag, off + PCI_MSI_MD64, vec); 357 } else { 358 pci_conf_write(pc, tag, off + PCI_MSI_MA, addr); 359 pci_conf_write(pc, tag, off + PCI_MSI_MD32, vec); 360 } 361 pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE); 362 } 363 364 void 365 msi_delroute(struct pic *pic, struct cpu_info *ci, int pin, int vec, int type) 366 { 367 pci_chipset_tag_t pc = NULL; /* XXX */ 368 pcitag_t tag = pin; 369 pcireg_t reg; 370 int off; 371 372 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) 373 pci_conf_write(pc, tag, off, reg & ~PCI_MSI_MC_MSIE); 374 } 375 376 int 377 pci_intr_map_msi(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 378 { 379 pci_chipset_tag_t pc = pa->pa_pc; 380 pcitag_t tag = pa->pa_tag; 381 382 if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 || mp_busses == NULL || 383 pci_get_capability(pc, tag, PCI_CAP_MSI, NULL, NULL) == 0) 384 return 1; 385 386 ihp->tag = tag; 387 ihp->line = APIC_INT_VIA_MSG; 388 ihp->pin = 0; 389 return 0; 390 } 391 392 void msix_hwmask(struct pic *, int); 393 void msix_hwunmask(struct pic *, int); 394 void msix_addroute(struct pic *, struct cpu_info *, int, int, int); 395 void msix_delroute(struct pic *, struct cpu_info *, int, int, int); 396 397 struct pic msix_pic = { 398 {0, {NULL}, NULL, 0, "msix", NULL, 0, 0}, 399 PIC_MSI, 400 #ifdef MULTIPROCESSOR 401 {}, 402 #endif 403 msix_hwmask, 404 msix_hwunmask, 405 msix_addroute, 406 msix_delroute, 407 NULL, 408 ioapic_edge_stubs 409 }; 410 411 /* 412 * We pack the MSI-X vector number into the lower 8 bits of the PCI 413 * tag and use that as the MSI-X "PIC" pin number. This allows us to 414 * address 256 MSI-X vectors which ought to be enough for anybody. 415 */ 416 #define PCI_MSIX_VEC_MASK 0xff 417 #define PCI_MSIX_VEC(pin) ((pin) & PCI_MSIX_VEC_MASK) 418 #define PCI_MSIX_TAG(pin) ((pin) & ~PCI_MSIX_VEC_MASK) 419 #define PCI_MSIX_PIN(tag, vec) ((tag) | (vec)) 420 421 void 422 msix_hwmask(struct pic *pic, int pin) 423 { 424 } 425 426 void 427 msix_hwunmask(struct pic *pic, int pin) 428 { 429 } 430 431 void 432 msix_addroute(struct pic *pic, struct cpu_info *ci, int pin, int vec, int type) 433 { 434 pci_chipset_tag_t pc = NULL; /* XXX */ 435 bus_space_tag_t memt = X86_BUS_SPACE_MEM; /* XXX */ 436 bus_space_handle_t memh; 437 pcitag_t tag = PCI_MSIX_TAG(pin); 438 int entry = PCI_MSIX_VEC(pin); 439 pcireg_t reg, addr; 440 uint32_t ctrl; 441 int off; 442 443 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0) 444 panic("%s: no msix capability", __func__); 445 446 KASSERT(entry <= PCI_MSIX_MC_TBLSZ(reg)); 447 448 if (pci_msix_table_map(pc, tag, memt, &memh)) 449 panic("%s: cannot map registers", __func__); 450 451 addr = 0xfee00000UL | (ci->ci_apicid << 12); 452 453 bus_space_write_4(memt, memh, PCI_MSIX_MA(entry), addr); 454 bus_space_write_4(memt, memh, PCI_MSIX_MAU32(entry), 0); 455 bus_space_write_4(memt, memh, PCI_MSIX_MD(entry), vec); 456 bus_space_barrier(memt, memh, PCI_MSIX_MA(entry), 16, 457 BUS_SPACE_BARRIER_WRITE); 458 ctrl = bus_space_read_4(memt, memh, PCI_MSIX_VC(entry)); 459 bus_space_write_4(memt, memh, PCI_MSIX_VC(entry), 460 ctrl & ~PCI_MSIX_VC_MASK); 461 462 pci_msix_table_unmap(pc, tag, memt, memh); 463 464 pci_conf_write(pc, tag, off, reg | PCI_MSIX_MC_MSIXE); 465 } 466 467 void 468 msix_delroute(struct pic *pic, struct cpu_info *ci, int pin, int vec, int type) 469 { 470 pci_chipset_tag_t pc = NULL; /* XXX */ 471 bus_space_tag_t memt = X86_BUS_SPACE_MEM; /* XXX */ 472 bus_space_handle_t memh; 473 pcitag_t tag = PCI_MSIX_TAG(pin); 474 int entry = PCI_MSIX_VEC(pin); 475 pcireg_t reg; 476 uint32_t ctrl; 477 478 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0) 479 return; 480 481 KASSERT(entry <= PCI_MSIX_MC_TBLSZ(reg)); 482 483 if (pci_msix_table_map(pc, tag, memt, &memh)) 484 return; 485 486 ctrl = bus_space_read_4(memt, memh, PCI_MSIX_VC(entry)); 487 bus_space_write_4(memt, memh, PCI_MSIX_VC(entry), 488 ctrl | PCI_MSIX_VC_MASK); 489 490 pci_msix_table_unmap(pc, tag, memt, memh); 491 } 492 493 int 494 pci_intr_map_msix(struct pci_attach_args *pa, int vec, pci_intr_handle_t *ihp) 495 { 496 pci_chipset_tag_t pc = pa->pa_pc; 497 pcitag_t tag = pa->pa_tag; 498 pcireg_t reg; 499 500 KASSERT(PCI_MSIX_VEC(vec) == vec); 501 502 if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 || mp_busses == NULL || 503 pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0) 504 return 1; 505 506 if (vec > PCI_MSIX_MC_TBLSZ(reg)) 507 return 1; 508 509 ihp->tag = PCI_MSIX_PIN(tag, vec); 510 ihp->line = APIC_INT_VIA_MSGX; 511 ihp->pin = 0; 512 return 0; 513 } 514 515 int 516 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 517 { 518 int pin = pa->pa_rawintrpin; 519 int line = pa->pa_intrline; 520 #if NIOAPIC > 0 521 struct mp_intr_map *mip; 522 int bus, dev, func; 523 #endif 524 525 if (pin == 0) { 526 /* No IRQ used. */ 527 goto bad; 528 } 529 530 if (pin > PCI_INTERRUPT_PIN_MAX) { 531 printf("pci_intr_map: bad interrupt pin %d\n", pin); 532 goto bad; 533 } 534 535 ihp->tag = pa->pa_tag; 536 ihp->line = line; 537 ihp->pin = pin; 538 539 #if NIOAPIC > 0 540 pci_decompose_tag(pa->pa_pc, pa->pa_tag, &bus, &dev, &func); 541 542 if (mp_busses != NULL) { 543 int mpspec_pin = (dev << 2) | (pin - 1); 544 545 if (bus < mp_nbusses) { 546 for (mip = mp_busses[bus].mb_intrs; 547 mip != NULL; mip = mip->next) { 548 if (&mp_busses[bus] == mp_isa_bus || 549 &mp_busses[bus] == mp_eisa_bus) 550 continue; 551 if (mip->bus_pin == mpspec_pin) { 552 ihp->line = mip->ioapic_ih | line; 553 return 0; 554 } 555 } 556 } 557 558 if (pa->pa_bridgetag) { 559 int swizpin = PPB_INTERRUPT_SWIZZLE(pin, dev); 560 if (pa->pa_bridgeih[swizpin - 1].line != -1) { 561 ihp->line = pa->pa_bridgeih[swizpin - 1].line; 562 ihp->line |= line; 563 return 0; 564 } 565 } 566 /* 567 * No explicit PCI mapping found. This is not fatal, 568 * we'll try the ISA (or possibly EISA) mappings next. 569 */ 570 } 571 #endif 572 573 /* 574 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 575 * `unknown' or `no connection' on a PC. We assume that a device with 576 * `no connection' either doesn't have an interrupt (in which case the 577 * pin number should be 0, and would have been noticed above), or 578 * wasn't configured by the BIOS (in which case we punt, since there's 579 * no real way we can know how the interrupt lines are mapped in the 580 * hardware). 581 * 582 * XXX 583 * Since IRQ 0 is only used by the clock, and we can't actually be sure 584 * that the BIOS did its job, we also recognize that as meaning that 585 * the BIOS has not configured the device. 586 */ 587 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) 588 goto bad; 589 590 if (line >= NUM_LEGACY_IRQS) { 591 printf("pci_intr_map: bad interrupt line %d\n", line); 592 goto bad; 593 } 594 if (line == 2) { 595 printf("pci_intr_map: changed line 2 to line 9\n"); 596 line = 9; 597 } 598 599 #if NIOAPIC > 0 600 if (mp_busses != NULL) { 601 if (mip == NULL && mp_isa_bus) { 602 for (mip = mp_isa_bus->mb_intrs; mip != NULL; 603 mip = mip->next) { 604 if (mip->bus_pin == line) { 605 ihp->line = mip->ioapic_ih | line; 606 return 0; 607 } 608 } 609 } 610 #if NEISA > 0 611 if (mip == NULL && mp_eisa_bus) { 612 for (mip = mp_eisa_bus->mb_intrs; mip != NULL; 613 mip = mip->next) { 614 if (mip->bus_pin == line) { 615 ihp->line = mip->ioapic_ih | line; 616 return 0; 617 } 618 } 619 } 620 #endif 621 if (mip == NULL) { 622 printf("pci_intr_map: " 623 "bus %d dev %d func %d pin %d; line %d\n", 624 bus, dev, func, pin, line); 625 printf("pci_intr_map: no MP mapping found\n"); 626 } 627 } 628 #endif 629 630 return 0; 631 632 bad: 633 ihp->line = -1; 634 return 1; 635 } 636 637 const char * 638 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 639 { 640 static char irqstr[64]; 641 642 if (ih.line == 0) 643 panic("pci_intr_string: bogus handle 0x%x", ih.line); 644 645 if (ih.line & APIC_INT_VIA_MSG) 646 return ("msi"); 647 if (ih.line & APIC_INT_VIA_MSGX) 648 return ("msix"); 649 650 #if NIOAPIC > 0 651 if (ih.line & APIC_INT_VIA_APIC) 652 snprintf(irqstr, sizeof(irqstr), "apic %d int %d", 653 APIC_IRQ_APIC(ih.line), APIC_IRQ_PIN(ih.line)); 654 else 655 snprintf(irqstr, sizeof(irqstr), "irq %d", 656 pci_intr_line(pc, ih)); 657 #else 658 snprintf(irqstr, sizeof(irqstr), "irq %d", pci_intr_line(pc, ih)); 659 #endif 660 return (irqstr); 661 } 662 663 #include "acpiprt.h" 664 #if NACPIPRT > 0 665 void acpiprt_route_interrupt(int bus, int dev, int pin); 666 #endif 667 668 void * 669 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 670 int (*func)(void *), void *arg, const char *what) 671 { 672 return pci_intr_establish_cpu(pc, ih, level, NULL, func, arg, what); 673 } 674 675 void * 676 pci_intr_establish_cpu(pci_chipset_tag_t pc, pci_intr_handle_t ih, 677 int level, struct cpu_info *ci, 678 int (*func)(void *), void *arg, const char *what) 679 { 680 int pin, irq; 681 int bus, dev; 682 pcitag_t tag = ih.tag; 683 struct pic *pic; 684 685 if (ih.line & APIC_INT_VIA_MSG) { 686 return intr_establish(-1, &msi_pic, tag, IST_PULSE, level, 687 ci, func, arg, what); 688 } 689 if (ih.line & APIC_INT_VIA_MSGX) { 690 return intr_establish(-1, &msix_pic, tag, IST_PULSE, level, 691 ci, func, arg, what); 692 } 693 694 pci_decompose_tag(pc, ih.tag, &bus, &dev, NULL); 695 #if NACPIPRT > 0 696 acpiprt_route_interrupt(bus, dev, ih.pin); 697 #endif 698 699 pic = &i8259_pic; 700 pin = irq = ih.line; 701 702 #if NIOAPIC > 0 703 if (ih.line & APIC_INT_VIA_APIC) { 704 pic = (struct pic *)ioapic_find(APIC_IRQ_APIC(ih.line)); 705 if (pic == NULL) { 706 printf("pci_intr_establish: bad ioapic %d\n", 707 APIC_IRQ_APIC(ih.line)); 708 return NULL; 709 } 710 pin = APIC_IRQ_PIN(ih.line); 711 irq = APIC_IRQ_LEGACY_IRQ(ih.line); 712 if (irq < 0 || irq >= NUM_LEGACY_IRQS) 713 irq = -1; 714 } 715 #endif 716 717 return intr_establish(irq, pic, pin, IST_LEVEL, level, ci, 718 func, arg, what); 719 } 720 721 void 722 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 723 { 724 intr_disestablish(cookie); 725 } 726 727 struct extent *pciio_ex; 728 struct extent *pcimem_ex; 729 struct extent *pcibus_ex; 730 731 void 732 pci_init_extents(void) 733 { 734 bios_memmap_t *bmp; 735 u_int64_t size; 736 737 if (pciio_ex == NULL) { 738 /* 739 * We only have 64K of addressable I/O space. 740 * However, since BARs may contain garbage, we cover 741 * the full 32-bit address space defined by PCI of 742 * which we only make the first 64K available. 743 */ 744 pciio_ex = extent_create("pciio", 0, 0xffffffff, M_DEVBUF, 745 NULL, 0, EX_NOWAIT | EX_FILLED); 746 if (pciio_ex == NULL) 747 return; 748 extent_free(pciio_ex, 0, 0x10000, EX_NOWAIT); 749 } 750 751 if (pcimem_ex == NULL) { 752 /* 753 * Cover the 36-bit address space addressable by PAE 754 * here. As long as vendors continue to support 755 * 32-bit operating systems, we should never see BARs 756 * outside that region. 757 * 758 * Dell 13G servers have important devices outside the 759 * 36-bit address space. Until we can extract the address 760 * ranges from ACPI, expand the allowed range to suit. 761 */ 762 pcimem_ex = extent_create("pcimem", 0, 0xffffffffffffffffUL, 763 M_DEVBUF, NULL, 0, EX_NOWAIT); 764 if (pcimem_ex == NULL) 765 return; 766 extent_alloc_region(pcimem_ex, 0x40000000000UL, 767 0xfffffc0000000000UL, EX_NOWAIT); 768 769 for (bmp = bios_memmap; bmp->type != BIOS_MAP_END; bmp++) { 770 /* 771 * Ignore address space beyond 4G. 772 */ 773 if (bmp->addr >= 0x100000000ULL) 774 continue; 775 size = bmp->size; 776 if (bmp->addr + size >= 0x100000000ULL) 777 size = 0x100000000ULL - bmp->addr; 778 779 /* Ignore zero-sized regions. */ 780 if (size == 0) 781 continue; 782 783 if (extent_alloc_region(pcimem_ex, bmp->addr, size, 784 EX_NOWAIT)) 785 printf("memory map conflict 0x%llx/0x%llx\n", 786 bmp->addr, bmp->size); 787 } 788 789 /* Take out the video buffer area and BIOS areas. */ 790 extent_alloc_region(pcimem_ex, IOM_BEGIN, IOM_SIZE, 791 EX_CONFLICTOK | EX_NOWAIT); 792 } 793 794 if (pcibus_ex == NULL) { 795 pcibus_ex = extent_create("pcibus", 0, 0xff, M_DEVBUF, 796 NULL, 0, EX_NOWAIT); 797 } 798 } 799 800 #include "acpi.h" 801 #if NACPI > 0 802 void acpi_pci_match(struct device *, struct pci_attach_args *); 803 pcireg_t acpi_pci_min_powerstate(pci_chipset_tag_t, pcitag_t); 804 void acpi_pci_set_powerstate(pci_chipset_tag_t, pcitag_t, int, int); 805 #endif 806 807 void 808 pci_dev_postattach(struct device *dev, struct pci_attach_args *pa) 809 { 810 #if NACPI > 0 811 acpi_pci_match(dev, pa); 812 #endif 813 } 814 815 pcireg_t 816 pci_min_powerstate(pci_chipset_tag_t pc, pcitag_t tag) 817 { 818 #if NACPI > 0 819 return acpi_pci_min_powerstate(pc, tag); 820 #else 821 return pci_get_powerstate(pc, tag); 822 #endif 823 } 824 825 void 826 pci_set_powerstate_md(pci_chipset_tag_t pc, pcitag_t tag, int state, int pre) 827 { 828 #if NACPI > 0 829 acpi_pci_set_powerstate(pc, tag, state, pre); 830 #endif 831 } 832