xref: /openbsd/sys/arch/arm/include/profile.h (revision e1753c98)
1*e1753c98Skettenis /*	$OpenBSD: profile.h,v 1.5 2016/09/21 11:33:05 kettenis Exp $	*/
2e1e4f5b1Sdrahn /*	$NetBSD: profile.h,v 1.5 2002/03/24 15:49:40 bjh21 Exp $	*/
3e1e4f5b1Sdrahn 
4e1e4f5b1Sdrahn /*
5e1e4f5b1Sdrahn  * Copyright (c) 2001 Ben Harris
6e1e4f5b1Sdrahn  * Copyright (c) 1995-1996 Mark Brinicombe
7e1e4f5b1Sdrahn  *
8e1e4f5b1Sdrahn  * Redistribution and use in source and binary forms, with or without
9e1e4f5b1Sdrahn  * modification, are permitted provided that the following conditions
10e1e4f5b1Sdrahn  * are met:
11e1e4f5b1Sdrahn  * 1. Redistributions of source code must retain the above copyright
12e1e4f5b1Sdrahn  *    notice, this list of conditions and the following disclaimer.
13e1e4f5b1Sdrahn  * 2. Redistributions in binary form must reproduce the above copyright
14e1e4f5b1Sdrahn  *    notice, this list of conditions and the following disclaimer in the
15e1e4f5b1Sdrahn  *    documentation and/or other materials provided with the distribution.
16e1e4f5b1Sdrahn  * 3. All advertising materials mentioning features or use of this software
17e1e4f5b1Sdrahn  *    must display the following acknowledgement:
18e1e4f5b1Sdrahn  *	This product includes software developed by Mark Brinicombe.
19e1e4f5b1Sdrahn  * 4. The name of the author may not be used to endorse or promote products
20e1e4f5b1Sdrahn  *    derived from this software without specific prior written permission.
21e1e4f5b1Sdrahn  *
22e1e4f5b1Sdrahn  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23e1e4f5b1Sdrahn  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24e1e4f5b1Sdrahn  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25e1e4f5b1Sdrahn  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26e1e4f5b1Sdrahn  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27e1e4f5b1Sdrahn  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28e1e4f5b1Sdrahn  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29e1e4f5b1Sdrahn  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30e1e4f5b1Sdrahn  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31e1e4f5b1Sdrahn  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32e1e4f5b1Sdrahn  */
33e1e4f5b1Sdrahn 
34e1e4f5b1Sdrahn #define	_MCOUNT_DECL void _mcount
35e1e4f5b1Sdrahn 
36e1e4f5b1Sdrahn /*
37e1e4f5b1Sdrahn  * Cannot implement mcount in C as GCC will trash the ip register when it
38e1e4f5b1Sdrahn  * pushes a trapframe. Pity we cannot insert assembly before the function
39e1e4f5b1Sdrahn  * prologue.
40e1e4f5b1Sdrahn  */
41e1e4f5b1Sdrahn 
42e1e4f5b1Sdrahn #define MCOUNT_ASM_NAME "__mcount"
4332b97dedSpascal #ifdef __PIC__
44e1e4f5b1Sdrahn #define	PLTSYM		"(PLT)"
45e1e4f5b1Sdrahn #endif
46e1e4f5b1Sdrahn 
47e1e4f5b1Sdrahn #ifndef PLTSYM
48e1e4f5b1Sdrahn #define	PLTSYM
49e1e4f5b1Sdrahn #endif
50e1e4f5b1Sdrahn 
51e1e4f5b1Sdrahn #define	MCOUNT								\
52e1e4f5b1Sdrahn 	__asm__(".text");						\
53*e1753c98Skettenis 	__asm__(".align	2");						\
54e1e4f5b1Sdrahn 	__asm__(".type	" MCOUNT_ASM_NAME ",%function");		\
55e1e4f5b1Sdrahn 	__asm__(".global	" MCOUNT_ASM_NAME);			\
56e1e4f5b1Sdrahn 	__asm__(MCOUNT_ASM_NAME ":");					\
57e1e4f5b1Sdrahn 	/*								\
58e1e4f5b1Sdrahn 	 * Preserve registers that are trashed during mcount		\
59e1e4f5b1Sdrahn 	 */								\
60e1e4f5b1Sdrahn 	__asm__("stmfd	sp!, {r0-r3, ip, lr}");				\
61e1e4f5b1Sdrahn 	/*								\
62e1e4f5b1Sdrahn 	 * find the return address for mcount,				\
63e1e4f5b1Sdrahn 	 * and the return address for mcount's caller.			\
64e1e4f5b1Sdrahn 	 *								\
65e1e4f5b1Sdrahn 	 * frompcindex = pc pushed by call into self.			\
66e1e4f5b1Sdrahn 	 */								\
675ab58429Smiod 	__asm__("mov	r0, ip");					\
68e1e4f5b1Sdrahn 	/*								\
69e1e4f5b1Sdrahn 	 * selfpc = pc pushed by mcount call				\
70e1e4f5b1Sdrahn 	 */								\
715ab58429Smiod 	__asm__("mov	r1, lr");					\
72e1e4f5b1Sdrahn 	/*								\
73e1e4f5b1Sdrahn 	 * Call the real mcount code					\
74e1e4f5b1Sdrahn 	 */								\
75e1e4f5b1Sdrahn 	__asm__("bl	" __STRING(_mcount) PLTSYM);		\
76e1e4f5b1Sdrahn 	/*								\
77e1e4f5b1Sdrahn 	 * Restore registers that were trashed during mcount		\
78e1e4f5b1Sdrahn 	 */								\
79e1e4f5b1Sdrahn 	__asm__("ldmfd	sp!, {r0-r3, lr, pc}");
80e1e4f5b1Sdrahn 
81e1e4f5b1Sdrahn #ifdef _KERNEL
82e1e4f5b1Sdrahn #include <arm/cpufunc.h>
83e1e4f5b1Sdrahn /*
84e1e4f5b1Sdrahn  * splhigh() and splx() are heavyweight, and call mcount().  Therefore
85e1e4f5b1Sdrahn  * we disabled interrupts (IRQ, but not FIQ) directly on the CPU.
86e1e4f5b1Sdrahn  *
87e1e4f5b1Sdrahn  * We're lucky that the CPSR and 's' both happen to be 'int's.
88e1e4f5b1Sdrahn  */
89e1e4f5b1Sdrahn #define	MCOUNT_ENTER	s = __set_cpsr_c(0x0080, 0x0080);	/* kill IRQ */
90e1e4f5b1Sdrahn #define	MCOUNT_EXIT	__set_cpsr_c(0xffffffff, s);	/* restore old value */
91e1e4f5b1Sdrahn #endif /* _KERNEL */
92