1 /* $OpenBSD: smmureg.h,v 1.1 2021/02/28 21:39:31 patrick Exp $ */ 2 /* 3 * Copyright (c) 2021 Patrick Wildt <patrick@blueri.se> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 /* Global Register Space 0 */ 19 #define SMMU_SCR0 0x000 20 #define SMMU_SCR0_CLIENTPD (1 << 0) 21 #define SMMU_SCR0_GFRE (1 << 1) 22 #define SMMU_SCR0_GFIE (1 << 2) 23 #define SMMU_SCR0_EXIDENABLE (1 << 3) 24 #define SMMU_SCR0_GCFGFRE (1 << 4) 25 #define SMMU_SCR0_GCFGFIE (1 << 5) 26 #define SMMU_SCR0_USFCFG (1 << 10) 27 #define SMMU_SCR0_VMIDPNE (1 << 11) 28 #define SMMU_SCR0_PTM (1 << 12) 29 #define SMMU_SCR0_FB (1 << 13) 30 #define SMMU_SCR0_BSU_MASK (0x3 << 14) 31 #define SMMU_SCR0_VMID16EN (1U << 31) 32 #define SMMU_SCR1 0x004 33 #define SMMU_SCR2 0x008 34 #define SMMU_SACR 0x010 35 #define SMMU_SACR_MMU500_SMTNMB_TLBEN (1 << 8) 36 #define SMMU_SACR_MMU500_S2CRB_TLBEN (1 << 10) 37 #define SMMU_SACR_MMU500_CACHE_LOCK (1 << 26) 38 #define SMMU_IDR0 0x020 39 #define SMMU_IDR0_NUMSMRG(x) (((x) >> 0) & 0xff) 40 #define SMMU_IDR0_EXIDS (1 << 8) 41 #define SMMU_IDR0_NUMSIDB(x) (((x) >> 9) & 0xf) 42 #define SMMU_IDR0_BTM (1 << 13) 43 #define SMMU_IDR0_CCTM (1 << 14) 44 #define SMMU_IDR0_EXSMRGS (1 << 15) 45 #define SMMU_IDR0_NUMIRPT(x) (((x) >> 16) & 0xff) 46 #define SMMU_IDR0_PTFS(x) (((x) >> 24) & 0x3) 47 #define SMMU_IDR0_PTFS_AARCH32_SHORT_AND_LONG 0x0 48 #define SMMU_IDR0_PTFS_AARCH32_ONLY_LONG 0x1 49 #define SMMU_IDR0_PTFS_AARCH32_NO 0x2 50 #define SMMU_IDR0_PTFS_AARCH32_RES 0x3 51 #define SMMU_IDR0_ATOSNS (1 << 26) 52 #define SMMU_IDR0_SMS (1 << 27) 53 #define SMMU_IDR0_NTS (1 << 28) 54 #define SMMU_IDR0_S2TS (1 << 29) 55 #define SMMU_IDR0_S1TS (1 << 30) 56 #define SMMU_IDR0_SES (1U << 31) 57 #define SMMU_IDR1 0x024 58 #define SMMU_IDR1_NUMCB(x) (((x) >> 0) & 0xff) 59 #define SMMU_IDR1_NUMSSDNDXB(x) (((x) >> 8) & 0xf) 60 #define SMMU_IDR1_SSDTP(x) (((x) >> 12) & 0x3) 61 #define SMMU_IDR1_SSDTP_UNK 0x0 62 #define SMMU_IDR1_SSDTP_IDX_NUMSSDNDXB 0x1 63 #define SMMU_IDR1_SSDTP_RES 0x2 64 #define SMMU_IDR1_SSDTP_IDX_16BIT 0x3 65 #define SMMU_IDR1_SMCD (1 << 15) 66 #define SMMU_IDR1_NUMS2CB(x) (((x) >> 16) & 0xff) 67 #define SMMU_IDR1_HAFDBS(x) (((x) >> 24) & 0x3) 68 #define SMMU_IDR1_HAFDBS_NO 0x0 69 #define SMMU_IDR1_HAFDBS_AF 0x1 70 #define SMMU_IDR1_HAFDBS_RES 0x2 71 #define SMMU_IDR1_HAFDBS_AFDB 0x3 72 #define SMMU_IDR1_NUMPAGENDXB(x) (((x) >> 28) & 0x7) 73 #define SMMU_IDR1_PAGESIZE_4K (0U << 31) 74 #define SMMU_IDR1_PAGESIZE_64K (1U << 31) 75 #define SMMU_IDR2 0x028 76 #define SMMU_IDR2_IAS(x) (((x) >> 0) & 0xf) 77 #define SMMU_IDR2_IAS_32BIT 0x0 78 #define SMMU_IDR2_IAS_36BIT 0x1 79 #define SMMU_IDR2_IAS_40BIT 0x2 80 #define SMMU_IDR2_IAS_42BIT 0x3 81 #define SMMU_IDR2_IAS_44BIT 0x4 82 #define SMMU_IDR2_IAS_48BIT 0x5 83 #define SMMU_IDR2_OAS(x) (((x) >> 4) & 0xf) 84 #define SMMU_IDR2_OAS_32BIT 0x0 85 #define SMMU_IDR2_OAS_36BIT 0x1 86 #define SMMU_IDR2_OAS_40BIT 0x2 87 #define SMMU_IDR2_OAS_42BIT 0x3 88 #define SMMU_IDR2_OAS_44BIT 0x4 89 #define SMMU_IDR2_OAS_48BIT 0x5 90 #define SMMU_IDR2_UBS(x) (((x) >> 8) & 0xf) 91 #define SMMU_IDR2_UBS_32BIT 0x0 92 #define SMMU_IDR2_UBS_36BIT 0x1 93 #define SMMU_IDR2_UBS_40BIT 0x2 94 #define SMMU_IDR2_UBS_42BIT 0x3 95 #define SMMU_IDR2_UBS_44BIT 0x4 96 #define SMMU_IDR2_UBS_49BIT 0x5 97 #define SMMU_IDR2_UBS_64BIT 0xf 98 #define SMMU_IDR2_PTFSV8_4KB (1 << 12) 99 #define SMMU_IDR2_PTFSV8_16KB (1 << 13) 100 #define SMMU_IDR2_PTFSV8_64KB (1 << 14) 101 #define SMMU_IDR2_VMID16S (1 << 15) 102 #define SMMU_IDR2_EXNUMSMRG (((x) >> 16) & 0x7ff) 103 #define SMMU_IDR2_E2HS (1 << 27) 104 #define SMMU_IDR2_HADS (1 << 28) 105 #define SMMU_IDR2_COMPINDEXS (1 << 29) 106 #define SMMU_IDR2_DIPANS (1 << 30) 107 #define SMMU_IDR3 0x02c 108 #define SMMU_IDR4 0x030 109 #define SMMU_IDR5 0x034 110 #define SMMU_IDR6 0x038 111 #define SMMU_IDR7 0x03c 112 #define SMMU_IDR7_MINOR(x) (((x) >> 0) & 0xf) 113 #define SMMU_IDR7_MAJOR(x) (((x) >> 4) & 0xf) 114 #define SMMU_SGFSR 0x048 115 #define SMMU_SGFSYNR0 0x050 116 #define SMMU_SGFSYNR1 0x054 117 #define SMMU_SGFSYNR2 0x058 118 #define SMMU_TLBIVMID 0x064 119 #define SMMU_TLBIALLNSNH 0x068 120 #define SMMU_TLBIALLH 0x06c 121 #define SMMU_STLBGSYNC 0x070 122 #define SMMU_STLBGSTATUS 0x074 123 #define SMMU_STLBGSTATUS_GSACTIVE (1 << 0) 124 #define SMMU_SMR(x) (0x800 + (x) * 0x4) /* 0 - 127 */ 125 #define SMMU_SMR_VALID (1U << 31) 126 #define SMMU_SMR_MASK (0x7fff << 16) 127 #define SMMU_S2CR(x) (0xc00 + (x) * 0x4) /* 0 - 127 */ 128 #define SMMU_S2CR_EXIDVALID (1 << 10) 129 #define SMMU_S2CR_TYPE_TRANS (0 << 16) 130 #define SMMU_S2CR_TYPE_BYPASS (1 << 16) 131 #define SMMU_S2CR_TYPE_FAULT (2 << 16) 132 #define SMMU_S2CR_TYPE_MASK (0x3 << 16) 133 134 /* Global Register Space 1 */ 135 #define SMMU_CBAR(x) (0x000 + (x) * 0x4) 136 #define SMMU_CBAR_VMID_SHIFT 0 137 #define SMMU_CBAR_BPSHCFG_RES (0x0 << 8) 138 #define SMMU_CBAR_BPSHCFG_OSH (0x1 << 8) 139 #define SMMU_CBAR_BPSHCFG_ISH (0x2 << 8) 140 #define SMMU_CBAR_BPSHCFG_NSH (0x3 << 8) 141 #define SMMU_CBAR_MEMATTR_WB (0xf << 12) 142 #define SMMU_CBAR_TYPE_S2_TRANS (0x0 << 16) 143 #define SMMU_CBAR_TYPE_S1_TRANS_S2_BYPASS (0x1 << 16) 144 #define SMMU_CBAR_TYPE_S1_TRANS_S2_FAULT (0x2 << 16) 145 #define SMMU_CBAR_TYPE_S1_TRANS_S2_TRANS (0x3 << 16) 146 #define SMMU_CBAR_TYPE_MASK (0x3 << 16) 147 #define SMMU_CBAR_IRPTNDX_SHIFT 24 148 #define SMMU_CBFRSYNRA(x) (0x400 + (x) * 0x4) 149 #define SMMU_CBA2R(x) (0x800 + (x) * 0x4) 150 #define SMMU_CBA2R_VA64 (1 << 0) 151 #define SMMU_CBA2R_MONC (1 << 1) 152 #define SMMU_CBA2R_VMID16_SHIFT 16 153 154 /* Context Bank Format */ 155 #define SMMU_CB_SCTLR 0x000 156 #define SMMU_CB_SCTLR_M (1 << 0) 157 #define SMMU_CB_SCTLR_TRE (1 << 1) 158 #define SMMU_CB_SCTLR_AFE (1 << 2) 159 #define SMMU_CB_SCTLR_CFRE (1 << 5) 160 #define SMMU_CB_SCTLR_CFIE (1 << 6) 161 #define SMMU_CB_SCTLR_ASIDPNE (1 << 12) 162 #define SMMU_CB_ACTLR 0x004 163 #define SMMU_CB_ACTLR_CPRE (1 << 1) 164 #define SMMU_CB_TCR2 0x010 165 #define SMMU_CB_TCR2_PASIZE_32BIT (0x0 << 0) 166 #define SMMU_CB_TCR2_PASIZE_36BIT (0x1 << 0) 167 #define SMMU_CB_TCR2_PASIZE_40BIT (0x2 << 0) 168 #define SMMU_CB_TCR2_PASIZE_42BIT (0x3 << 0) 169 #define SMMU_CB_TCR2_PASIZE_44BIT (0x4 << 0) 170 #define SMMU_CB_TCR2_PASIZE_48BIT (0x5 << 0) 171 #define SMMU_CB_TCR2_PASIZE_MASK (0x7 << 0) 172 #define SMMU_CB_TCR2_AS (1 << 4) 173 #define SMMU_CB_TCR2_SEP_UPSTREAM (0x7 << 15) 174 #define SMMU_CB_TTBR0 0x020 175 #define SMMU_CB_TTBR1 0x028 176 #define SMMU_CB_TTBR_ASID_SHIFT 48 177 #define SMMU_CB_TCR 0x030 178 #define SMMU_CB_TCR_T0SZ(x) ((x) << 0) 179 #define SMMU_CB_TCR_EPD0 (1 << 7) 180 #define SMMU_CB_TCR_IRGN0_NC (0x0 << 8) 181 #define SMMU_CB_TCR_IRGN0_WBWA (0x1 << 8) 182 #define SMMU_CB_TCR_IRGN0_WT (0x2 << 8) 183 #define SMMU_CB_TCR_IRGN0_WB (0x3 << 8) 184 #define SMMU_CB_TCR_ORGN0_NC (0x0 << 10) 185 #define SMMU_CB_TCR_ORGN0_WBWA (0x1 << 10) 186 #define SMMU_CB_TCR_ORGN0_WT (0x2 << 10) 187 #define SMMU_CB_TCR_ORGN0_WB (0x3 << 10) 188 #define SMMU_CB_TCR_SH0_NSH (0x0 << 12) 189 #define SMMU_CB_TCR_SH0_OSH (0x2 << 12) 190 #define SMMU_CB_TCR_SH0_ISH (0x3 << 12) 191 #define SMMU_CB_TCR_TG0_4KB (0x0 << 14) 192 #define SMMU_CB_TCR_TG0_64KB (0x1 << 14) 193 #define SMMU_CB_TCR_TG0_16KB (0x2 << 14) 194 #define SMMU_CB_TCR_TG0_MASK (0x3 << 14) 195 #define SMMU_CB_TCR_T1SZ(x) ((x) << 16) 196 #define SMMU_CB_TCR_EPD1 (1 << 23) 197 #define SMMU_CB_TCR_IRGN1_NC (0x0 << 24) 198 #define SMMU_CB_TCR_IRGN1_WBWA (0x1 << 24) 199 #define SMMU_CB_TCR_IRGN1_WT (0x2 << 24) 200 #define SMMU_CB_TCR_IRGN1_WB (0x3 << 24) 201 #define SMMU_CB_TCR_ORGN1_NC (0x0 << 26) 202 #define SMMU_CB_TCR_ORGN1_WBWA (0x1 << 26) 203 #define SMMU_CB_TCR_ORGN1_WT (0x2 << 26) 204 #define SMMU_CB_TCR_ORGN1_WB (0x3 << 26) 205 #define SMMU_CB_TCR_SH1_NSH (0x0 << 28) 206 #define SMMU_CB_TCR_SH1_OSH (0x2 << 28) 207 #define SMMU_CB_TCR_SH1_ISH (0x3 << 28) 208 #define SMMU_CB_TCR_TG1_16KB (0x1 << 30) 209 #define SMMU_CB_TCR_TG1_4KB (0x2 << 30) 210 #define SMMU_CB_TCR_TG1_64KB (0x3 << 30) 211 #define SMMU_CB_TCR_TG1_MASK (0x3 << 30) 212 #define SMMU_CB_TCR_S2_SL0_4KB_L2 (0x0 << 6) 213 #define SMMU_CB_TCR_S2_SL0_4KB_L1 (0x1 << 6) 214 #define SMMU_CB_TCR_S2_SL0_4KB_L0 (0x2 << 6) 215 #define SMMU_CB_TCR_S2_SL0_16KB_L3 (0x0 << 6) 216 #define SMMU_CB_TCR_S2_SL0_16KB_L2 (0x1 << 6) 217 #define SMMU_CB_TCR_S2_SL0_16KB_L1 (0x2 << 6) 218 #define SMMU_CB_TCR_S2_SL0_64KB_L3 (0x0 << 6) 219 #define SMMU_CB_TCR_S2_SL0_64KB_L2 (0x1 << 6) 220 #define SMMU_CB_TCR_S2_SL0_64KB_L1 (0x2 << 6) 221 #define SMMU_CB_TCR_S2_SL0_MASK (0x3 << 6) 222 #define SMMU_CB_TCR_S2_PASIZE_32BIT (0x0 << 16) 223 #define SMMU_CB_TCR_S2_PASIZE_36BIT (0x1 << 16) 224 #define SMMU_CB_TCR_S2_PASIZE_40BIT (0x2 << 16) 225 #define SMMU_CB_TCR_S2_PASIZE_42BIT (0x3 << 16) 226 #define SMMU_CB_TCR_S2_PASIZE_44BIT (0x4 << 16) 227 #define SMMU_CB_TCR_S2_PASIZE_48BIT (0x5 << 16) 228 #define SMMU_CB_TCR_S2_PASIZE_MASK (0x7 << 16) 229 #define SMMU_CB_MAIR0 0x038 230 #define SMMU_CB_MAIR1 0x03c 231 #define SMMU_CB_MAIR_MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 232 #define SMMU_CB_MAIR_DEVICE_nGnRnE 0x00 233 #define SMMU_CB_MAIR_DEVICE_nGnRE 0x04 234 #define SMMU_CB_MAIR_DEVICE_NC 0x44 235 #define SMMU_CB_MAIR_DEVICE_WB 0xff 236 #define SMMU_CB_MAIR_DEVICE_WT 0x88 237 #define SMMU_CB_FSR 0x058 238 #define SMMU_CB_FSR_TF (1 << 1) 239 #define SMMU_CB_FSR_AFF (1 << 2) 240 #define SMMU_CB_FSR_PF (1 << 3) 241 #define SMMU_CB_FSR_EF (1 << 4) 242 #define SMMU_CB_FSR_TLBMCF (1 << 5) 243 #define SMMU_CB_FSR_TLBLKF (1 << 6) 244 #define SMMU_CB_FSR_ASF (1 << 7) 245 #define SMMU_CB_FSR_UUT (1 << 8) 246 #define SMMU_CB_FSR_SS (1 << 30) 247 #define SMMU_CB_FSR_MULTI (1U << 31) 248 #define SMMU_CB_FSR_MASK (SMMU_CB_FSR_TF | \ 249 SMMU_CB_FSR_AFF | \ 250 SMMU_CB_FSR_PF | \ 251 SMMU_CB_FSR_EF | \ 252 SMMU_CB_FSR_TLBMCF | \ 253 SMMU_CB_FSR_TLBLKF | \ 254 SMMU_CB_FSR_ASF | \ 255 SMMU_CB_FSR_UUT | \ 256 SMMU_CB_FSR_SS | \ 257 SMMU_CB_FSR_MULTI) 258 #define SMMU_CB_FAR 0x060 259 #define SMMU_CB_FSYNR0 0x068 260 #define SMMU_CB_IPAFAR 0x070 261 #define SMMU_CB_TLBIVA 0x600 262 #define SMMU_CB_TLBIVAA 0x608 263 #define SMMU_CB_TLBIASID 0x610 264 #define SMMU_CB_TLBIALL 0x618 265 #define SMMU_CB_TLBIVAL 0x620 266 #define SMMU_CB_TLBIVAAL 0x628 267 #define SMMU_CB_TLBIIPAS2 0x630 268 #define SMMU_CB_TLBIIPAS2L 0x638 269 #define SMMU_CB_TLBSYNC 0x7f0 270 #define SMMU_CB_TLBSTATUS 0x7f4 271 #define SMMU_CB_TLBSTATUS_SACTIVE (1 << 0) 272