1 /* $OpenBSD: ti_iic.c,v 1.5 2016/06/26 07:25:05 jsg Exp $ */ 2 /* $NetBSD: ti_iic.c,v 1.4 2013/04/25 13:04:27 rkujawa Exp $ */ 3 4 /* 5 * Copyright (c) 2013 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /*- 29 * Copyright (c) 2012 Jared D. McNeill <jmcneill@invisible.ca> 30 * All rights reserved. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. The name of the author may not be used to endorse or promote products 38 * derived from this software without specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 41 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 42 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 43 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 44 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 45 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 46 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 47 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 */ 52 53 #include <sys/cdefs.h> 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/device.h> 57 #include <sys/kernel.h> 58 #include <sys/rwlock.h> 59 60 #include <machine/bus.h> 61 #include <machine/intr.h> 62 #include <machine/fdt.h> 63 64 #include <dev/i2c/i2cvar.h> 65 66 #include <armv7/armv7/armv7var.h> 67 #include <armv7/omap/prcmvar.h> 68 #include <armv7/omap/sitara_cm.h> 69 #include <armv7/omap/sitara_cmreg.h> 70 #include <armv7/omap/ti_iicreg.h> 71 72 #include <dev/ofw/openfirm.h> 73 74 #ifndef AM335X_I2C_SLAVE_ADDR 75 #define AM335X_I2C_SLAVE_ADDR 0x01 76 #endif 77 78 #ifdef I2CDEBUG 79 #define DPRINTF(args) printf args 80 #else 81 #define DPRINTF(args) 82 #endif 83 84 /* operation in progress */ 85 typedef enum { 86 TI_I2CREAD, 87 TI_I2CWRITE, 88 TI_I2CDONE, 89 TI_I2CERROR 90 } ti_i2cop_t; 91 92 struct ti_iic_softc { 93 struct device sc_dev; 94 struct i2c_controller sc_ic; 95 struct rwlock sc_buslock; 96 struct device *sc_i2cdev; 97 98 bus_space_tag_t sc_iot; 99 bus_space_handle_t sc_ioh; 100 101 void *sc_ih; 102 int sc_node; 103 ti_i2cop_t sc_op; 104 int sc_buflen; 105 int sc_bufidx; 106 char *sc_buf; 107 108 int sc_rxthres; 109 int sc_txthres; 110 }; 111 112 113 #define I2C_READ_REG(sc, reg) \ 114 bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, (reg)) 115 #define I2C_READ_DATA(sc) \ 116 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, AM335X_I2C_DATA); 117 #define I2C_WRITE_REG(sc, reg, val) \ 118 bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 119 #define I2C_WRITE_DATA(sc, val) \ 120 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, AM335X_I2C_DATA, (val)) 121 122 #define DEVNAME(sc) ((sc)->sc_dev.dv_xname) 123 124 int ti_iic_match(struct device *, void *, void *); 125 void ti_iic_attach(struct device *, struct device *, void *); 126 int ti_iic_intr(void *); 127 128 int ti_iic_acquire_bus(void *, int); 129 void ti_iic_release_bus(void *, int); 130 int ti_iic_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, void *, 131 size_t, int); 132 void ti_iic_scan(struct device *, struct i2cbus_attach_args *, void *); 133 134 int ti_iic_reset(struct ti_iic_softc *); 135 int ti_iic_op(struct ti_iic_softc *, i2c_addr_t, ti_i2cop_t, uint8_t *, 136 size_t, int); 137 void ti_iic_handle_intr(struct ti_iic_softc *, uint32_t); 138 void ti_iic_do_read(struct ti_iic_softc *, uint32_t); 139 void ti_iic_do_write(struct ti_iic_softc *, uint32_t); 140 141 int ti_iic_wait(struct ti_iic_softc *, uint16_t, uint16_t, int); 142 uint32_t ti_iic_stat(struct ti_iic_softc *, uint32_t); 143 int ti_iic_flush(struct ti_iic_softc *); 144 145 struct cfattach tiiic_ca = { 146 sizeof (struct ti_iic_softc), ti_iic_match, ti_iic_attach 147 }; 148 149 struct cfdriver tiiic_cd = { 150 NULL, "tiiic", DV_DULL 151 }; 152 153 int 154 ti_iic_match(struct device *parent, void *match, void *aux) 155 { 156 struct fdt_attach_args *faa = aux; 157 158 return OF_is_compatible(faa->fa_node, "ti,omap4-i2c"); 159 } 160 161 void 162 ti_iic_attach(struct device *parent, struct device *self, void *aux) 163 { 164 struct ti_iic_softc *sc = (struct ti_iic_softc *)self; 165 struct fdt_attach_args *faa = aux; 166 struct i2cbus_attach_args iba; 167 uint16_t rev; 168 const char *mode; 169 u_int state; 170 int irq, unit, len; 171 char buf[20]; 172 char hwmods[128]; 173 char *pin; 174 /* BBB specific pin names */ 175 char *pins[6] = {"I2C0_SDA", "I2C0_SCL", 176 "SPIO_D1", "SPI0_CS0", 177 "UART1_CTSn", "UART1_RTSn"}; 178 179 if (faa->fa_nreg != 2 || (faa->fa_nintr != 1 && faa->fa_nintr != 3)) 180 return; 181 182 sc->sc_iot = faa->fa_iot; 183 sc->sc_node = faa->fa_node; 184 185 if (faa->fa_nintr == 1) 186 irq = faa->fa_intr[0]; 187 else 188 irq = faa->fa_intr[1]; 189 190 unit = 0; 191 if ((len = OF_getprop(faa->fa_node, "ti,hwmods", hwmods, 192 sizeof(hwmods))) == 5) { 193 if (!strncmp(hwmods, "i2c", 3) && 194 (hwmods[3] > '0') && (hwmods[3] <= '9')) 195 unit = hwmods[3] - '1'; 196 } 197 198 rw_init(&sc->sc_buslock, "tiiilk"); 199 200 sc->sc_rxthres = sc->sc_txthres = 4; 201 202 if (bus_space_map(sc->sc_iot, faa->fa_reg[0], 203 faa->fa_reg[1], 0, &sc->sc_ioh)) 204 panic("%s: bus_space_map failed!", DEVNAME(sc)); 205 206 sc->sc_ih = arm_intr_establish(irq, IPL_NET, 207 ti_iic_intr, sc, DEVNAME(sc)); 208 209 prcm_enablemodule(PRCM_I2C0 + unit); 210 211 if (board_id == BOARD_ID_AM335X_BEAGLEBONE) { 212 pin = pins[unit * 2]; 213 snprintf(buf, sizeof buf, "I2C%d_SDA", unit); 214 if (sitara_cm_padconf_set(pin, buf, 215 (0x01 << 4) | (0x01 << 5) | (0x01 << 6)) != 0) { 216 printf(": can't switch %s pad\n", buf); 217 return; 218 } 219 if (sitara_cm_padconf_get(pin, &mode, &state) == 0) { 220 printf(": %s state %d ", mode, state); 221 } 222 223 pin = pins[unit * 2 + 1]; 224 snprintf(buf, sizeof buf, "I2C%d_SCL", unit); 225 if (sitara_cm_padconf_set(pin, buf, 226 (0x01 << 4) | (0x01 << 5) | (0x01 << 6)) != 0) { 227 printf(": can't switch %s pad\n", buf); 228 return; 229 } 230 if (sitara_cm_padconf_get(pin, &mode, &state) == 0) { 231 printf(": %s state %d ", mode, state); 232 } 233 } 234 235 rev = I2C_READ_REG(sc, AM335X_I2C_REVNB_LO); 236 printf(" rev %d.%d\n", 237 (int)I2C_REVNB_LO_MAJOR(rev), 238 (int)I2C_REVNB_LO_MINOR(rev)); 239 240 ti_iic_reset(sc); 241 ti_iic_flush(sc); 242 243 sc->sc_ic.ic_cookie = sc; 244 sc->sc_ic.ic_acquire_bus = ti_iic_acquire_bus; 245 sc->sc_ic.ic_release_bus = ti_iic_release_bus; 246 sc->sc_ic.ic_exec = ti_iic_exec; 247 248 bzero(&iba, sizeof iba); 249 iba.iba_name = "iic"; 250 iba.iba_tag = &sc->sc_ic; 251 iba.iba_bus_scan = ti_iic_scan; 252 iba.iba_bus_scan_arg = &sc->sc_node; 253 (void) config_found(&sc->sc_dev, &iba, iicbus_print); 254 } 255 256 int 257 ti_iic_intr(void *arg) 258 { 259 struct ti_iic_softc *sc = arg; 260 uint32_t stat; 261 262 DPRINTF(("ti_iic_intr\n")); 263 stat = I2C_READ_REG(sc, AM335X_I2C_IRQSTATUS); 264 I2C_WRITE_REG(sc, AM335X_I2C_IRQSTATUS, stat); 265 DPRINTF(("ti_iic_intr pre handle sc->sc_op eq %#x\n", sc->sc_op)); 266 267 ti_iic_handle_intr(sc, stat); 268 269 if (sc->sc_op == TI_I2CERROR || sc->sc_op == TI_I2CDONE) { 270 DPRINTF(("ti_iic_intr post handle sc->sc_op %#x\n", sc->sc_op)); 271 wakeup(&sc->sc_dev); 272 } 273 274 DPRINTF(("ti_iic_intr status 0x%x\n", stat)); 275 276 return 1; 277 } 278 279 int 280 ti_iic_acquire_bus(void *opaque, int flags) 281 { 282 struct ti_iic_softc *sc = opaque; 283 284 if (flags & I2C_F_POLL) 285 return 0; 286 287 return (rw_enter(&sc->sc_buslock, RW_WRITE)); 288 } 289 290 void 291 ti_iic_release_bus(void *opaque, int flags) 292 { 293 struct ti_iic_softc *sc = opaque; 294 295 if (flags & I2C_F_POLL) 296 return; 297 298 rw_exit(&sc->sc_buslock); 299 } 300 301 int 302 ti_iic_exec(void *opaque, i2c_op_t op, i2c_addr_t addr, 303 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 304 { 305 struct ti_iic_softc *sc = opaque; 306 int err; 307 308 309 DPRINTF(("ti_iic_exec: op 0x%x cmdlen %zd len %zd flags 0x%x\n", 310 op, cmdlen, len, flags)); 311 312 #define __UNCONST(a) ((void *)(unsigned long)(const void *)(a)) 313 if (cmdlen > 0) { 314 err = ti_iic_op(sc, addr, TI_I2CWRITE, __UNCONST(cmdbuf), 315 cmdlen, (I2C_OP_READ_P(op) ? 0 : I2C_F_STOP) | flags); 316 if (err) 317 goto done; 318 } 319 if (I2C_OP_STOP_P(op)) 320 flags |= I2C_F_STOP; 321 322 /* 323 * I2C controller doesn't allow for zero-byte transfers. 324 */ 325 if (len == 0) 326 goto done; 327 328 if (I2C_OP_READ_P(op)) 329 err = ti_iic_op(sc, addr, TI_I2CREAD, buf, len, flags); 330 else 331 err = ti_iic_op(sc, addr, TI_I2CWRITE, buf, len, flags); 332 333 done: 334 if (err) 335 ti_iic_reset(sc); 336 337 ti_iic_flush(sc); 338 339 DPRINTF(("ti_iic_exec: done %d\n", err)); 340 return err; 341 } 342 343 int 344 ti_iic_reset(struct ti_iic_softc *sc) 345 { 346 uint32_t psc, scll, sclh; 347 int i; 348 349 DPRINTF(("ti_iic_reset\n")); 350 351 /* Disable */ 352 I2C_WRITE_REG(sc, AM335X_I2C_CON, 0); 353 /* Soft reset */ 354 I2C_WRITE_REG(sc, AM335X_I2C_SYSC, I2C_SYSC_SRST); 355 delay(1000); 356 /* enable so that we can check for reset complete */ 357 I2C_WRITE_REG(sc, AM335X_I2C_CON, I2C_CON_EN); 358 delay(1000); 359 for (i = 0; i < 1000; i++) { /* 1s delay for reset */ 360 if (I2C_READ_REG(sc, AM335X_I2C_SYSS) & I2C_SYSS_RDONE) 361 break; 362 } 363 /* Disable again */ 364 I2C_WRITE_REG(sc, AM335X_I2C_CON, 0); 365 delay(50000); 366 367 if (i >= 1000) { 368 printf("%s: couldn't reset module\n", DEVNAME(sc)); 369 return 1; 370 } 371 372 /* XXX standard speed only */ 373 psc = 3; 374 scll = 53; 375 sclh = 55; 376 377 /* Clocks */ 378 I2C_WRITE_REG(sc, AM335X_I2C_PSC, psc); 379 I2C_WRITE_REG(sc, AM335X_I2C_SCLL, scll); 380 I2C_WRITE_REG(sc, AM335X_I2C_SCLH, sclh); 381 382 /* Own I2C address */ 383 I2C_WRITE_REG(sc, AM335X_I2C_OA, AM335X_I2C_SLAVE_ADDR); 384 385 /* 5 bytes fifo */ 386 I2C_WRITE_REG(sc, AM335X_I2C_BUF, 387 I2C_BUF_RXTRSH(sc->sc_rxthres) | I2C_BUF_TXTRSH(sc->sc_txthres)); 388 389 /* Enable */ 390 I2C_WRITE_REG(sc, AM335X_I2C_CON, I2C_CON_EN); 391 392 return 0; 393 } 394 395 int 396 ti_iic_op(struct ti_iic_softc *sc, i2c_addr_t addr, ti_i2cop_t op, 397 uint8_t *buf, size_t buflen, int flags) 398 { 399 uint16_t con, stat, mask; 400 int err, retry; 401 402 KASSERT(op == TI_I2CREAD || op == TI_I2CWRITE); 403 DPRINTF(("ti_iic_op: addr %#x op %#x buf %p buflen %#x flags %#x\n", 404 addr, op, buf, (unsigned int) buflen, flags)); 405 406 mask = I2C_IRQSTATUS_ARDY | I2C_IRQSTATUS_NACK | I2C_IRQSTATUS_AL; 407 if (op == TI_I2CREAD) 408 mask |= I2C_IRQSTATUS_RDR | I2C_IRQSTATUS_RRDY; 409 else 410 mask |= I2C_IRQSTATUS_XDR | I2C_IRQSTATUS_XRDY; 411 412 err = ti_iic_wait(sc, I2C_IRQSTATUS_BB, 0, flags); 413 if (err) { 414 DPRINTF(("ti_iic_op: wait error %d\n", err)); 415 return err; 416 } 417 418 con = I2C_CON_EN; 419 con |= I2C_CON_MST; 420 con |= I2C_CON_STT; 421 if (flags & I2C_F_STOP) 422 con |= I2C_CON_STP; 423 if (addr & ~0x7f) 424 con |= I2C_CON_XSA; 425 if (op == TI_I2CWRITE) 426 con |= I2C_CON_TRX; 427 428 sc->sc_op = op; 429 sc->sc_buf = buf; 430 sc->sc_buflen = buflen; 431 sc->sc_bufidx = 0; 432 433 I2C_WRITE_REG(sc, 434 AM335X_I2C_CON, I2C_CON_EN | I2C_CON_MST | I2C_CON_STP); 435 DPRINTF(("ti_iic_op: op %d con 0x%x ", op, con)); 436 I2C_WRITE_REG(sc, AM335X_I2C_CNT, buflen); 437 I2C_WRITE_REG(sc, AM335X_I2C_SA, (addr & I2C_SA_MASK)); 438 DPRINTF(("SA 0x%x len %d\n", 439 I2C_READ_REG(sc, AM335X_I2C_SA), I2C_READ_REG(sc, AM335X_I2C_CNT))); 440 441 if ((flags & I2C_F_POLL) == 0) { 442 /* clear any pending interrupt */ 443 I2C_WRITE_REG(sc, AM335X_I2C_IRQSTATUS, 444 I2C_READ_REG(sc, AM335X_I2C_IRQSTATUS)); 445 /* and enable */ 446 I2C_WRITE_REG(sc, AM335X_I2C_IRQENABLE_SET, mask); 447 } 448 /* start transfer */ 449 I2C_WRITE_REG(sc, AM335X_I2C_CON, con); 450 451 if ((flags & I2C_F_POLL) == 0) { 452 /* and wait for completion */ 453 DPRINTF(("ti_iic_op waiting, op %#x\n", sc->sc_op)); 454 while (sc->sc_op == op) { 455 if (tsleep(&sc->sc_dev, PWAIT, "tiiic", 500) 456 == EWOULDBLOCK) { 457 /* timeout */ 458 op = TI_I2CERROR; 459 } 460 } 461 DPRINTF(("ti_iic_op waiting done, op %#x\n", sc->sc_op)); 462 463 /* disable interrupts */ 464 I2C_WRITE_REG(sc, AM335X_I2C_IRQENABLE_CLR, 0xffff); 465 } else { 466 /* poll for completion */ 467 DPRINTF(("ti_iic_op polling, op %x\n", sc->sc_op)); 468 while (sc->sc_op == op) { 469 stat = ti_iic_stat(sc, mask); 470 DPRINTF(("ti_iic_op stat 0x%x\n", stat)); 471 if (stat == 0) /* timeout */ 472 sc->sc_op = TI_I2CERROR; 473 else 474 ti_iic_handle_intr(sc, stat); 475 I2C_WRITE_REG(sc, AM335X_I2C_IRQSTATUS, stat); 476 } 477 DPRINTF(("ti_iic_op polling done, op now %x\n", sc->sc_op)); 478 } 479 retry = 10000; 480 I2C_WRITE_REG(sc, AM335X_I2C_CON, 0); 481 while (I2C_READ_REG(sc, AM335X_I2C_CON) & I2C_CON_MST) { 482 delay(100); 483 if (--retry == 0) 484 break; 485 } 486 487 return (sc->sc_op == TI_I2CDONE) ? 0 : EIO; 488 } 489 490 void 491 ti_iic_handle_intr(struct ti_iic_softc *sc, uint32_t stat) 492 { 493 KASSERT(stat != 0); 494 DPRINTF(("ti_iic_handle_intr stat %#x\n", stat)); 495 496 if (stat & (I2C_IRQSTATUS_NACK|I2C_IRQSTATUS_AL)) { 497 sc->sc_op = TI_I2CERROR; 498 return; 499 } 500 if (stat & I2C_IRQSTATUS_ARDY) { 501 sc->sc_op = TI_I2CDONE; 502 return; 503 } 504 if (sc->sc_op == TI_I2CREAD) 505 ti_iic_do_read(sc, stat); 506 else if (sc->sc_op == TI_I2CWRITE) 507 ti_iic_do_write(sc, stat); 508 else 509 return; 510 } 511 void 512 ti_iic_do_read(struct ti_iic_softc *sc, uint32_t stat) 513 { 514 int len = 0; 515 516 DPRINTF(("ti_iic_do_read stat %#x\n", stat)); 517 if (stat & I2C_IRQSTATUS_RDR) { 518 len = I2C_READ_REG(sc, AM335X_I2C_BUFSTAT); 519 len = I2C_BUFSTAT_RXSTAT(len); 520 DPRINTF(("ti_iic_do_read receive drain len %d left %d\n", 521 len, I2C_READ_REG(sc, AM335X_I2C_CNT))); 522 } else if (stat & I2C_IRQSTATUS_RRDY) { 523 len = sc->sc_rxthres + 1; 524 DPRINTF(("ti_iic_do_read receive len %d left %d\n", 525 len, I2C_READ_REG(sc, AM335X_I2C_CNT))); 526 } 527 for (; 528 sc->sc_bufidx < sc->sc_buflen && len > 0; 529 sc->sc_bufidx++, len--) { 530 sc->sc_buf[sc->sc_bufidx] = I2C_READ_DATA(sc); 531 DPRINTF(("ti_iic_do_read got b[%d]=0x%x\n", sc->sc_bufidx, 532 sc->sc_buf[sc->sc_bufidx])); 533 } 534 DPRINTF(("ti_iic_do_read done\n")); 535 } 536 537 void 538 ti_iic_do_write(struct ti_iic_softc *sc, uint32_t stat) 539 { 540 int len = 0; 541 542 DPRINTF(("ti_iic_do_write stat %#x\n", stat)); 543 544 if (stat & I2C_IRQSTATUS_XDR) { 545 len = I2C_READ_REG(sc, AM335X_I2C_BUFSTAT); 546 len = I2C_BUFSTAT_TXSTAT(len); 547 DPRINTF(("ti_iic_do_write xmit drain len %d left %d\n", 548 len, I2C_READ_REG(sc, AM335X_I2C_CNT))); 549 } else if (stat & I2C_IRQSTATUS_XRDY) { 550 len = sc->sc_txthres + 1; 551 DPRINTF(("ti_iic_do_write xmit len %d left %d\n", 552 len, I2C_READ_REG(sc, AM335X_I2C_CNT))); 553 } 554 for (; 555 sc->sc_bufidx < sc->sc_buflen && len > 0; 556 sc->sc_bufidx++, len--) { 557 DPRINTF(("ti_iic_do_write send b[%d]=0x%x\n", 558 sc->sc_bufidx, sc->sc_buf[sc->sc_bufidx])); 559 I2C_WRITE_DATA(sc, sc->sc_buf[sc->sc_bufidx]); 560 } 561 DPRINTF(("ti_iic_do_write done\n")); 562 } 563 564 int 565 ti_iic_wait(struct ti_iic_softc *sc, uint16_t mask, uint16_t val, int flags) 566 { 567 int retry = 10; 568 uint16_t v; 569 DPRINTF(("ti_iic_wait mask %#x val %#x flags %#x\n", mask, val, flags)); 570 571 while (((v = I2C_READ_REG(sc, AM335X_I2C_IRQSTATUS_RAW)) & mask) != val) { 572 --retry; 573 if (retry == 0) { 574 printf("%s: wait timeout, mask=%#x val=%#x stat=%#x\n", 575 DEVNAME(sc), mask, val, v); 576 return EBUSY; 577 } 578 if (flags & I2C_F_POLL) 579 delay(50000); 580 else 581 tsleep(&sc->sc_dev, PWAIT, "tiiic", 50); 582 } 583 DPRINTF(("ti_iic_wait done retry %#x\n", retry)); 584 585 return 0; 586 } 587 588 uint32_t 589 ti_iic_stat(struct ti_iic_softc *sc, uint32_t mask) 590 { 591 uint32_t v; 592 int retry = 500; 593 DPRINTF(("ti_iic_wait mask %#x\n", mask)); 594 while (--retry > 0) { 595 v = I2C_READ_REG(sc, AM335X_I2C_IRQSTATUS_RAW) & mask; 596 if (v != 0) 597 break; 598 delay(100); 599 } 600 DPRINTF(("ti_iic_wait done retry %#x\n", retry)); 601 return v; 602 } 603 604 int 605 ti_iic_flush(struct ti_iic_softc *sc) 606 { 607 DPRINTF(("ti_iic_flush\n")); 608 #if 0 609 int retry = 1000; 610 uint16_t v; 611 612 while ((v = 613 I2C_READ_REG(sc, AM335X_I2C_IRQSTATUS_RAW)) & I2C_IRQSTATUS_RRDY) { 614 if (--retry == 0) { 615 printf("%s: flush timeout, stat = %#x\n", DEVNAME(sc), v); 616 return EBUSY; 617 } 618 (void)I2C_READ_DATA(sc); 619 delay(1000); 620 } 621 #endif 622 623 I2C_WRITE_REG(sc, AM335X_I2C_CNT, 0); 624 return 0; 625 } 626 627 void 628 ti_iic_scan(struct device *self, struct i2cbus_attach_args *iba, void *aux) 629 { 630 int iba_node = *(int *)aux; 631 extern int iic_print(void *, const char *); 632 struct i2c_attach_args ia; 633 char name[32]; 634 uint32_t reg[1]; 635 int node; 636 637 for (node = OF_child(iba_node); node; node = OF_peer(node)) { 638 memset(name, 0, sizeof(name)); 639 memset(reg, 0, sizeof(reg)); 640 641 if (OF_getprop(node, "compatible", name, sizeof(name)) == -1) 642 continue; 643 if (name[0] == '\0') 644 continue; 645 646 if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg)) 647 continue; 648 649 memset(&ia, 0, sizeof(ia)); 650 ia.ia_tag = iba->iba_tag; 651 ia.ia_addr = bemtoh32(®[0]); 652 ia.ia_name = name; 653 ia.ia_cookie = &node; 654 655 config_found(self, &ia, iic_print); 656 } 657 } 658