1 /* $OpenBSD: cpu.c,v 1.41 2014/01/19 12:45:35 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 1998-2003 Michael Shalayeff 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/device.h> 32 #include <sys/proc.h> 33 #include <sys/reboot.h> 34 #include <dev/rndvar.h> 35 36 #include <uvm/uvm_extern.h> 37 38 #include <machine/cpufunc.h> 39 #include <machine/pdc.h> 40 #include <machine/reg.h> 41 #include <machine/iomod.h> 42 #include <machine/autoconf.h> 43 44 #include <hppa/dev/cpudevs.h> 45 46 struct cpu_softc { 47 struct device sc_dev; 48 }; 49 50 #ifdef MULTIPROCESSOR 51 struct cpu_info *cpu_hatch_info; 52 static volatile int start_secondary_cpu; 53 #endif 54 55 int cpumatch(struct device *, void *, void *); 56 void cpuattach(struct device *, struct device *, void *); 57 58 struct cfattach cpu_ca = { 59 sizeof(struct cpu_softc), cpumatch, cpuattach 60 }; 61 62 struct cfdriver cpu_cd = { 63 NULL, "cpu", DV_DULL 64 }; 65 66 int 67 cpumatch(struct device *parent, void *cfdata, void *aux) 68 { 69 struct cfdata *cf = cfdata; 70 struct confargs *ca = aux; 71 72 /* probe any 1.0, 1.1 or 2.0 */ 73 if (ca->ca_type.iodc_type != HPPA_TYPE_NPROC || 74 ca->ca_type.iodc_sv_model != HPPA_NPROC_HPPA) 75 return 0; 76 77 if (cf->cf_unit >= MAXCPUS) 78 return 0; 79 80 return 1; 81 } 82 83 void 84 cpuattach(struct device *parent, struct device *self, void *aux) 85 { 86 /* machdep.c */ 87 extern struct pdc_model pdc_model; 88 extern struct pdc_cache pdc_cache; 89 extern struct pdc_btlb pdc_btlb; 90 extern u_int cpu_ticksnum, cpu_ticksdenom; 91 extern u_int fpu_enable; 92 /* clock.c */ 93 extern int cpu_hardclock(void *); 94 /* ipi.c */ 95 extern int hppa_ipi_intr(void *); 96 97 struct confargs *ca = (struct confargs *)aux; 98 struct cpu_info *ci; 99 u_int mhz = 100 * cpu_ticksnum / cpu_ticksdenom; 100 int cpuno = self->dv_unit; 101 struct pglist mlist; 102 struct vm_page *m; 103 const char *p; 104 int error; 105 106 ci = &cpu_info[cpuno]; 107 ci->ci_dev = self; 108 ci->ci_cpuid = cpuno; 109 ci->ci_hpa = ca->ca_hpa; 110 111 /* Allocate stack for spin up and FPU emulation. */ 112 TAILQ_INIT(&mlist); 113 error = uvm_pglistalloc(PAGE_SIZE, 0, -1L, 0, 0, &mlist, 1, 114 UVM_PLA_NOWAIT); 115 if (error) { 116 printf(": unable to allocate CPU stack!\n"); 117 return; 118 } 119 m = TAILQ_FIRST(&mlist); 120 ci->ci_stack = VM_PAGE_TO_PHYS(m); 121 122 printf (": %s ", cpu_typename); 123 if (pdc_model.hvers) { 124 static const char lvls[4][4] = { "0", "1", "1.5", "2" }; 125 126 printf("L%s-%c ", lvls[pdc_model.pa_lvl], "AB"[pdc_model.mc]); 127 } 128 129 printf ("%d", mhz / 100); 130 if (mhz % 100 > 9) 131 printf(".%02d", mhz % 100); 132 printf("MHz"); 133 134 if (fpu_enable) { 135 extern u_int fpu_version; 136 u_int32_t ver[2]; 137 138 mtctl(fpu_enable, CR_CCR); 139 __asm volatile( 140 "fstds %%fr0,0(%0)\n\t" 141 "copr,0,0\n\t" 142 "fstds %%fr0,0(%0)" 143 :: "r" (&ver) : "memory"); 144 mtctl(0, CR_CCR); 145 fpu_version = HPPA_FPUVER(ver[0]); 146 printf(", FPU %s rev %d", 147 hppa_mod_info(HPPA_TYPE_FPU, fpu_version >> 5), 148 fpu_version & 0x1f); 149 } 150 151 printf("\n%s: ", self->dv_xname); 152 p = ""; 153 if (!pdc_cache.dc_conf.cc_sh) { 154 printf("%uK(%db/l) Icache, ", 155 pdc_cache.ic_size / 1024, pdc_cache.ic_conf.cc_line * 16); 156 p = "D"; 157 } 158 159 printf("%uK(%db/l) wr-%s %scache, ", 160 pdc_cache.dc_size / 1024, pdc_cache.dc_conf.cc_line * 16, 161 pdc_cache.dc_conf.cc_wt? "thru" : "back", p); 162 163 p = ""; 164 if (!pdc_cache.dt_conf.tc_sh) { 165 printf("%u ITLB, ", pdc_cache.it_size); 166 p = "D"; 167 } 168 printf("%u %scoherent %sTLB", 169 pdc_cache.dt_size, pdc_cache.dt_conf.tc_cst? "" : "in", p); 170 171 if (pdc_btlb.finfo.num_c) 172 printf(", %u BTLB", pdc_btlb.finfo.num_c); 173 else if (pdc_btlb.finfo.num_i || pdc_btlb.finfo.num_d) 174 printf(", %u/%u D/I BTLBs", 175 pdc_btlb.finfo.num_i, pdc_btlb.finfo.num_d); 176 177 cpu_intr_establish(IPL_CLOCK, 31, cpu_hardclock, NULL, "clock"); 178 #ifdef MULTIPROCESSOR 179 cpu_intr_establish(IPL_IPI, 30, hppa_ipi_intr, NULL, "ipi"); 180 #endif 181 182 printf("\n"); 183 } 184 185 #ifdef MULTIPROCESSOR 186 void 187 cpu_boot_secondary_processors(void) 188 { 189 struct cpu_info *ci; 190 struct iomod *cpu; 191 int i, j; 192 193 /* Initialise primary CPU. */ 194 ci = curcpu(); 195 ci->ci_flags |= CPUF_RUNNING; 196 hppa_ipi_init(ci); 197 198 for (i = 0; i < HPPA_MAXCPUS; i++) { 199 200 ci = &cpu_info[i]; 201 if (ci->ci_cpuid == 0) 202 continue; 203 204 ci->ci_randseed = (arc4random() & 0x7fffffff) + 1; 205 206 sched_init_cpu(ci); 207 208 /* Release the specified CPU by triggering an EIR{0}. */ 209 cpu_hatch_info = ci; 210 cpu = (struct iomod *)(ci->ci_hpa); 211 cpu->io_eir = 0; 212 asm volatile ("sync" ::: "memory"); 213 214 /* Wait for CPU to wake up... */ 215 j = 0; 216 while (!(ci->ci_flags & CPUF_RUNNING) && j++ < 10000) 217 delay(1000); 218 if (!(ci->ci_flags & CPUF_RUNNING)) 219 printf("failed to hatch cpu %i!\n", ci->ci_cpuid); 220 } 221 222 /* Release secondary CPUs. */ 223 start_secondary_cpu = 1; 224 asm volatile ("sync" ::: "memory"); 225 } 226 227 void 228 cpu_hw_init(void) 229 { 230 struct cpu_info *ci = curcpu(); 231 232 /* Purge TLB and flush caches. */ 233 ptlball(); 234 ficacheall(); 235 fdcacheall(); 236 237 /* Enable address translations. */ 238 ci->ci_psw = PSL_I | PSL_Q | PSL_P | PSL_C | PSL_D; 239 ci->ci_psw |= (cpu_info[0].ci_psw & PSL_O); 240 } 241 242 void 243 cpu_hatch(void) 244 { 245 struct cpu_info *ci = curcpu(); 246 extern u_long cpu_hzticks; 247 u_long itmr; 248 int s; 249 250 /* Initialise IPIs. */ 251 hppa_ipi_init(ci); 252 253 /* Initialise clock. */ 254 mtctl((1U << 31), CR_EIRR); 255 mfctl(CR_ITMR, itmr); 256 ci->ci_itmr = itmr; 257 itmr += cpu_hzticks; 258 mtctl(itmr, CR_ITMR); 259 ci->ci_mask |= (1U << 31); 260 261 /* Enable interrupts. */ 262 mtctl(ci->ci_mask, CR_EIEM); 263 264 ncpus++; 265 ci->ci_flags |= CPUF_RUNNING; 266 267 /* Wait for additional CPUs to spinup. */ 268 while (!start_secondary_cpu) 269 ; 270 271 SCHED_LOCK(s); 272 cpu_switchto(NULL, sched_chooseproc()); 273 } 274 275 void 276 cpu_unidle(struct cpu_info *ci) 277 { 278 if (ci != curcpu()) 279 hppa_ipi_send(ci, HPPA_IPI_NOP); 280 } 281 #endif 282 283 void 284 need_resched(struct cpu_info *ci) 285 { 286 ci->ci_want_resched = 1; 287 288 /* There's a risk we'll be called before the idle threads start */ 289 if (ci->ci_curproc) { 290 setsoftast(ci->ci_curproc); 291 cpu_unidle(ci); 292 } 293 } 294