1 /* $OpenBSD: intr.h,v 1.11 2001/06/24 17:05:36 miod Exp $ */ 2 3 /* 4 * Copyright (c) 1990,1991,1992,1994 The University of Utah and 5 * the Computer Systems Laboratory at the University of Utah (CSL). 6 * All rights reserved. 7 * 8 * Permission to use, copy, modify and distribute this software is hereby 9 * granted provided that (1) source code retains these copyright, permission, 10 * and disclaimer notices, and (2) redistributions including binaries 11 * reproduce the notices in supporting documentation, and (3) all advertising 12 * materials mentioning features or use of this software display the following 13 * acknowledgement: ``This product includes software developed by the 14 * Computer Systems Laboratory at the University of Utah.'' 15 * 16 * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS 17 * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF 18 * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * CSL requests users of this software to return to csl-dist@cs.utah.edu any 21 * improvements that they make and grant CSL redistribution rights. 22 * 23 * Utah $Hdr: machspl.h 1.16 94/12/14$ 24 * Author: Jeff Forys, Bob Wheeler, University of Utah CSL 25 */ 26 27 #ifndef _MACHINE_INTR_H_ 28 #define _MACHINE_INTR_H_ 29 30 #include <machine/psl.h> 31 32 #define CPU_NINTS 32 33 #define CPU_INTITMR (0x80000000) 34 35 #define IPL_NONE (0xffffffff) 36 #define IPL_BIO (0x80000000) 37 #define IPL_NET (0x80000000) 38 #define IPL_TTY (0x80000000) 39 #define IPL_IO (IPL_BIO|IPL_NET|IPL_TTY) 40 #define IPL_CLOCK (0) 41 #define IPL_HIGH (0) 42 43 #define IST_NONE 0 44 #define IST_PULSE 1 45 #define IST_EDGE 2 46 #define IST_LEVEL 3 47 48 #if !defined(_LOCORE) 49 /* 50 * Define the machine-independent SPL routines in terms of splx(). 51 */ 52 #define __splhigh(splhval) ({ \ 53 register u_int _ctl_r; \ 54 __asm __volatile("mfctl %%cr15,%0\n\t" \ 55 "mtctl %1,%%cr15" \ 56 : "=&r" (_ctl_r): "r" (splhval)); \ 57 _ctl_r; \ 58 }) 59 60 #define __spllow(spllval) ({ \ 61 register u_int _ctl_r; \ 62 __asm __volatile("mfctl %%cr15,%0\n\t" \ 63 "mtctl %1,%%cr15" \ 64 : "=&r" (_ctl_r): "r" (spllval)); \ 65 _ctl_r; \ 66 }) 67 68 #define splx(splval) ({ \ 69 register u_int _ctl_r; \ 70 __asm __volatile("mfctl %%cr15,%0\n\t" \ 71 "mtctl %1,%%cr15\n\t" \ 72 : "=&r" (_ctl_r): "r" (splval)); \ 73 _ctl_r; \ 74 }) 75 76 #define spl0() __spllow(IPL_NONE) 77 #define splsoft() __spllow(IPL_CLOCK) 78 #define splsoftnet() splsoft() 79 #define spllowersoftclock() splsoft() 80 #define splsoftclock() splsoft() 81 #define splbio() __spllow(IPL_BIO) 82 #define splnet() __spllow(IPL_NET) 83 #define spltty() __spllow(IPL_TTY) 84 #define splimp() __spllow(IPL_CLOCK) 85 #define splclock() __spllow(IPL_CLOCK) 86 #define splstatclock() __spllow(IPL_CLOCK) 87 #define splvm() __spllow(IPL_CLOCK) 88 #define splhigh() __splhigh(IPL_HIGH) 89 90 /* software interrupt register */ 91 extern u_int32_t sir; 92 extern int astpending; 93 94 #define SIR_CLOCK 0x01 95 #define SIR_NET 0x02 96 97 #define setsoftclock() (sir |= SIR_CLOCK) 98 #define setsoftnet() (sir |= SIR_NET) 99 #define setsoftast() (astpending = 1) 100 101 #endif /* !_LOCORE */ 102 #endif /* _MACHINE_INTR_H_ */ 103