1 /* $OpenBSD: opti82c558.c,v 1.9 2023/01/30 10:49:05 jsg Exp $ */ 2 /* $NetBSD: opti82c558.c,v 1.2 2000/07/18 11:24:09 soda Exp $ */ 3 4 /*- 5 * Copyright (c) 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1999, by UCHIYAMA Yasushi 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. The name of the developer may NOT be used to endorse or promote products 44 * derived from this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 */ 58 59 /* 60 * Support for the Opti 82c558 PCI-ISA bridge interrupt controller. 61 */ 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/malloc.h> 66 67 #include <machine/intr.h> 68 #include <machine/bus.h> 69 70 #include <dev/pci/pcivar.h> 71 72 #include <i386/pci/pcibiosvar.h> 73 #include <i386/pci/opti82c558reg.h> 74 75 int opti82c558_getclink(pciintr_icu_handle_t, int, int *); 76 int opti82c558_get_intr(pciintr_icu_handle_t, int, int *); 77 int opti82c558_set_intr(pciintr_icu_handle_t, int, int); 78 int opti82c558_get_trigger(pciintr_icu_handle_t, int, int *); 79 int opti82c558_set_trigger(pciintr_icu_handle_t, int, int); 80 81 const struct pciintr_icu opti82c558_pci_icu = { 82 opti82c558_getclink, 83 opti82c558_get_intr, 84 opti82c558_set_intr, 85 opti82c558_get_trigger, 86 opti82c558_set_trigger, 87 }; 88 89 struct opti82c558_handle { 90 pci_chipset_tag_t ph_pc; 91 pcitag_t ph_tag; 92 }; 93 94 static const int viper_pirq_decode[] = { 95 -1, 5, 9, 10, 11, 12, 14, 15 96 }; 97 98 static const int viper_pirq_encode[] = { 99 -1, /* 0 */ 100 -1, /* 1 */ 101 -1, /* 2 */ 102 -1, /* 3 */ 103 -1, /* 4 */ 104 VIPER_PIRQ_5, /* 5 */ 105 -1, /* 6 */ 106 -1, /* 7 */ 107 -1, /* 8 */ 108 VIPER_PIRQ_9, /* 9 */ 109 VIPER_PIRQ_10, /* 10 */ 110 VIPER_PIRQ_11, /* 11 */ 111 VIPER_PIRQ_12, /* 12 */ 112 -1, /* 13 */ 113 VIPER_PIRQ_14, /* 14 */ 114 VIPER_PIRQ_15, /* 15 */ 115 }; 116 117 int 118 opti82c558_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag, 119 pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp) 120 { 121 struct opti82c558_handle *ph; 122 123 ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT); 124 if (ph == NULL) 125 return (1); 126 127 ph->ph_pc = pc; 128 ph->ph_tag = tag; 129 130 *ptagp = &opti82c558_pci_icu; 131 *phandp = ph; 132 return (0); 133 } 134 135 int 136 opti82c558_getclink(pciintr_icu_handle_t v, int link, int *clinkp) 137 { 138 139 if (VIPER_LEGAL_LINK(link - 1)) { 140 *clinkp = link - 1; 141 return (0); 142 } 143 144 return (1); 145 } 146 147 int 148 opti82c558_get_intr(pciintr_icu_handle_t v, int clink, int *irqp) 149 { 150 struct opti82c558_handle *ph = v; 151 pcireg_t reg; 152 int val; 153 154 if (VIPER_LEGAL_LINK(clink) == 0) 155 return (1); 156 157 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ); 158 val = VIPER_PIRQ(reg, clink); 159 *irqp = (val == VIPER_PIRQ_NONE) ? 0xff : viper_pirq_decode[val]; 160 161 return (0); 162 } 163 164 int 165 opti82c558_set_intr(pciintr_icu_handle_t v, int clink, int irq) 166 { 167 struct opti82c558_handle *ph = v; 168 int shift; 169 pcireg_t reg; 170 171 if (VIPER_LEGAL_LINK(clink) == 0 || VIPER_LEGAL_IRQ(irq) == 0) 172 return (1); 173 174 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ); 175 shift = VIPER_PIRQ_SELECT_SHIFT * clink; 176 reg &= ~(VIPER_PIRQ_SELECT_MASK << shift); 177 reg |= (viper_pirq_encode[irq] << shift); 178 pci_conf_write(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ, reg); 179 180 return (0); 181 } 182 183 int 184 opti82c558_get_trigger(pciintr_icu_handle_t v, int irq, int *triggerp) 185 { 186 struct opti82c558_handle *ph = v; 187 pcireg_t reg; 188 189 if (VIPER_LEGAL_IRQ(irq) == 0) { 190 /* ISA IRQ? */ 191 *triggerp = IST_EDGE; 192 return (0); 193 } 194 195 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ); 196 if ((reg >> (VIPER_CFG_TRIGGER_SHIFT + viper_pirq_encode[irq])) & 1) 197 *triggerp = IST_LEVEL; 198 else 199 *triggerp = IST_EDGE; 200 201 return (0); 202 } 203 204 int 205 opti82c558_set_trigger(pciintr_icu_handle_t v, int irq, int trigger) 206 { 207 struct opti82c558_handle *ph = v; 208 int shift; 209 pcireg_t reg; 210 211 if (VIPER_LEGAL_IRQ(irq) == 0) { 212 /* ISA IRQ? */ 213 return ((trigger != IST_LEVEL) ? 0 : 1); 214 } 215 216 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ); 217 shift = (VIPER_CFG_TRIGGER_SHIFT + viper_pirq_encode[irq]); 218 if (trigger == IST_LEVEL) 219 reg |= (1 << shift); 220 else 221 reg &= ~(1 << shift); 222 pci_conf_write(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ, reg); 223 224 return (0); 225 } 226