1 /* $OpenBSD: pci_intr_fixup.c,v 1.63 2021/03/06 09:20:50 jsg Exp $ */ 2 /* $NetBSD: pci_intr_fixup.c,v 1.10 2000/08/10 21:18:27 soda Exp $ */ 3 4 /* 5 * Copyright (c) 2001 Michael Shalayeff 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 21 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 22 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /*- 30 * Copyright (c) 1999 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 35 * NASA Ames Research Center. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 47 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 48 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 49 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 50 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 51 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 52 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 53 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 54 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 55 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 56 * POSSIBILITY OF SUCH DAMAGE. 57 */ 58 /* 59 * Copyright (c) 1999, by UCHIYAMA Yasushi 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions 64 * are met: 65 * 1. Redistributions of source code must retain the above copyright 66 * notice, this list of conditions and the following disclaimer. 67 * 2. The name of the developer may NOT be used to endorse or promote products 68 * derived from this software without specific prior written permission. 69 * 70 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 71 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 73 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 74 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 75 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 76 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 77 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 78 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 79 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 80 * SUCH DAMAGE. 81 */ 82 83 /* 84 * PCI Interrupt Router support. 85 */ 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/kernel.h> 90 #include <sys/malloc.h> 91 #include <sys/queue.h> 92 #include <sys/device.h> 93 94 #include <machine/bus.h> 95 #include <machine/intr.h> 96 #include <machine/i8259.h> 97 #include <machine/i82093var.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <i386/pci/pcibiosvar.h> 104 105 struct pciintr_link_map { 106 int link, clink, irq, fixup_stage; 107 u_int16_t bitmap; 108 SIMPLEQ_ENTRY(pciintr_link_map) list; 109 }; 110 111 pciintr_icu_tag_t pciintr_icu_tag = NULL; 112 pciintr_icu_handle_t pciintr_icu_handle; 113 114 #ifdef PCIBIOS_IRQS_HINT 115 int pcibios_irqs_hint = PCIBIOS_IRQS_HINT; 116 #endif 117 118 struct pciintr_link_map *pciintr_link_lookup(int); 119 struct pcibios_intr_routing *pciintr_pir_lookup(int, int); 120 int pciintr_bitmap_count_irq(int, int *); 121 122 SIMPLEQ_HEAD(, pciintr_link_map) pciintr_link_map_list; 123 124 const struct pciintr_icu_table { 125 pci_vendor_id_t piit_vendor; 126 pci_product_id_t piit_product; 127 int (*piit_init)(pci_chipset_tag_t, 128 bus_space_tag_t, pcitag_t, pciintr_icu_tag_t *, 129 pciintr_icu_handle_t *); 130 } pciintr_icu_table[] = { 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 132 piix_init }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_LPC, 134 piix_init }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371MX, 136 piix_init }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371AB_ISA, 138 piix_init }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371FB_ISA, 140 piix_init }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371SB_ISA, 142 piix_init }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ISA, 144 piix_init }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 146 piix_init }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 148 piix_init }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 150 piix_init }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 152 piix_init }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 154 piix_init }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 156 piix_init }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 158 piix_init }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 160 piix_init }, 161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 162 piix_init }, 163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 164 piix_init }, 165 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 166 piix_init }, 167 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 168 piix_init }, 169 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_LPC, 170 piix_init }, 171 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 172 piix_init }, 173 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 174 piix_init }, 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 176 piix_init }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 178 piix_init }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 180 piix_init }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 182 piix_init }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 184 piix_init }, 185 186 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C558, 187 opti82c558_init }, 188 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C700, 189 opti82c700_init }, 190 191 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_OSB4, 192 osb4_init }, 193 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_CSB5, 194 osb4_init }, 195 196 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C586_ISA, 197 via82c586_init, }, 198 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C596A, 199 via82c586_init, }, 200 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C686A_ISA, 201 via82c586_init }, 202 203 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8231_ISA, 204 via8231_init }, 205 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8233_ISA, 206 via8231_init }, 207 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8233A_ISA, 208 via8231_init }, 209 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8235_ISA, 210 via8231_init }, 211 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237_ISA, 212 via8231_init }, 213 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237A_ISA, 214 via8231_init }, 215 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237S_ISA, 216 via8231_init }, 217 218 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C503, 219 sis85c503_init }, 220 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_962, 221 sis85c503_init }, 222 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_963, 223 sis85c503_init }, 224 225 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC756_PMC, 226 amd756_init }, 227 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_766_PMC, 228 amd756_init }, 229 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_PMC, 230 amd756_init }, 231 232 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1533, 233 ali1543_init }, 234 235 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1543, 236 ali1543_init }, 237 238 { 0, 0, 239 NULL }, 240 }; 241 242 const struct pciintr_icu_table *pciintr_icu_lookup(pcireg_t); 243 244 const struct pciintr_icu_table * 245 pciintr_icu_lookup(pcireg_t id) 246 { 247 const struct pciintr_icu_table *piit; 248 249 for (piit = pciintr_icu_table; piit->piit_init != NULL; piit++) 250 if (PCI_VENDOR(id) == piit->piit_vendor && 251 PCI_PRODUCT(id) == piit->piit_product) 252 return (piit); 253 254 return (NULL); 255 } 256 257 struct pciintr_link_map * 258 pciintr_link_lookup(int link) 259 { 260 struct pciintr_link_map *l; 261 262 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 263 l = SIMPLEQ_NEXT(l, list)) 264 if (l->link == link) 265 return (l); 266 267 return (NULL); 268 } 269 270 static __inline struct pciintr_link_map * 271 pciintr_link_alloc(pci_chipset_tag_t pc, struct pcibios_intr_routing *pir, int pin) 272 { 273 int link = pir->linkmap[pin].link, clink, irq; 274 struct pciintr_link_map *l, *lstart; 275 276 if (pciintr_icu_tag != NULL) { 277 /* 278 * Get the canonical link value for this entry. 279 */ 280 if (pciintr_icu_getclink(pciintr_icu_tag, pciintr_icu_handle, 281 link, &clink) != 0) { 282 /* 283 * ICU doesn't understand the link value. 284 * Just ignore this PIR entry. 285 */ 286 PCIBIOS_PRINTV(("pciintr_link_alloc: bus %d device %d: " 287 "ignoring link 0x%02x\n", pir->bus, 288 PIR_DEVFUNC_DEVICE(pir->device), link)); 289 return (NULL); 290 } 291 292 /* 293 * Check the link value by asking the ICU for the 294 * canonical link value. 295 * Also, determine if this PIRQ is mapped to an IRQ. 296 */ 297 if (pciintr_icu_get_intr(pciintr_icu_tag, pciintr_icu_handle, 298 clink, &irq) != 0) { 299 /* 300 * ICU doesn't understand the canonical link value. 301 * Just ignore this PIR entry. 302 */ 303 PCIBIOS_PRINTV(("pciintr_link_alloc: " 304 "bus %d device %d link 0x%02x: " 305 "ignoring PIRQ 0x%02x\n", pir->bus, 306 PIR_DEVFUNC_DEVICE(pir->device), link, clink)); 307 return (NULL); 308 } 309 } 310 311 if ((l = malloc(sizeof(*l), M_DEVBUF, M_NOWAIT|M_ZERO)) == NULL) 312 return (NULL); 313 314 l->link = link; 315 l->bitmap = pir->linkmap[pin].bitmap; 316 if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */ 317 l->clink = clink; 318 l->irq = irq; /* maybe I386_PCI_INTERRUPT_LINE_NO_CONNECTION */ 319 } else { 320 l->clink = link; 321 l->irq = I386_PCI_INTERRUPT_LINE_NO_CONNECTION; 322 } 323 324 lstart = SIMPLEQ_FIRST(&pciintr_link_map_list); 325 if (lstart == NULL || lstart->link < l->link) 326 SIMPLEQ_INSERT_TAIL(&pciintr_link_map_list, l, list); 327 else 328 SIMPLEQ_INSERT_HEAD(&pciintr_link_map_list, l, list); 329 330 return (l); 331 } 332 333 struct pcibios_intr_routing * 334 pciintr_pir_lookup(int bus, int device) 335 { 336 struct pcibios_intr_routing *pir; 337 int entry; 338 339 if (pcibios_pir_table == NULL) 340 return (NULL); 341 342 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 343 pir = &pcibios_pir_table[entry]; 344 if (pir->bus == bus && 345 PIR_DEVFUNC_DEVICE(pir->device) == device) 346 return (pir); 347 } 348 349 return (NULL); 350 } 351 352 int 353 pciintr_bitmap_count_irq(int irq_bitmap, int *irqp) 354 { 355 int i, bit, count = 0, irq = I386_PCI_INTERRUPT_LINE_NO_CONNECTION; 356 357 if (irq_bitmap != 0) 358 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) 359 if (irq_bitmap & bit) { 360 irq = i; 361 count++; 362 } 363 364 *irqp = irq; 365 return (count); 366 } 367 368 static __inline int 369 pciintr_link_init(pci_chipset_tag_t pc) 370 { 371 int entry, pin, link; 372 struct pcibios_intr_routing *pir; 373 struct pciintr_link_map *l; 374 375 if (pcibios_pir_table == NULL) { 376 /* No PIR table; can't do anything. */ 377 printf("pciintr_link_init: no PIR table\n"); 378 return (1); 379 } 380 381 SIMPLEQ_INIT(&pciintr_link_map_list); 382 383 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 384 pir = &pcibios_pir_table[entry]; 385 for (pin = 0; pin < PCI_INTERRUPT_PIN_MAX; pin++) { 386 if ((link = pir->linkmap[pin].link) == 0) 387 /* No connection for this pin. */ 388 continue; 389 390 /* 391 * Multiple devices may be wired to the same 392 * interrupt; check to see if we've seen this 393 * one already. If not, allocate a new link 394 * map entry and stuff it in the map. 395 */ 396 if ((l = pciintr_link_lookup(link)) == NULL) 397 pciintr_link_alloc(pc, pir, pin); 398 else if (pir->linkmap[pin].bitmap != l->bitmap) { 399 /* 400 * violates PCI IRQ Routing Table Specification 401 */ 402 PCIBIOS_PRINTV(("pciintr_link_init: " 403 "bus %d device %d link 0x%02x: " 404 "bad irq bitmap 0x%04x, " 405 "should be 0x%04x\n", pir->bus, 406 PIR_DEVFUNC_DEVICE(pir->device), link, 407 pir->linkmap[pin].bitmap, l->bitmap)); 408 /* safer value. */ 409 l->bitmap &= pir->linkmap[pin].bitmap; 410 /* XXX - or, should ignore this entry? */ 411 } 412 } 413 } 414 415 return (0); 416 } 417 418 /* 419 * No compatible PCI ICU found. 420 * Hopes the BIOS already setup the ICU. 421 */ 422 static __inline int 423 pciintr_guess_irq(void) 424 { 425 struct pciintr_link_map *l; 426 int irq, guessed = 0; 427 428 /* 429 * Stage 1: If only one IRQ is available for the link, use it. 430 */ 431 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 432 l = SIMPLEQ_NEXT(l, list)) { 433 if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 434 continue; 435 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 436 l->irq = irq; 437 l->fixup_stage = 1; 438 if (pcibios_flags & PCIBIOS_INTRDEBUG) 439 printf("pciintr_guess_irq (stage 1): " 440 "guessing PIRQ 0x%02x to be IRQ %d\n", 441 l->clink, l->irq); 442 guessed = 1; 443 } 444 } 445 446 return (guessed ? 0 : -1); 447 } 448 449 static __inline int 450 pciintr_link_fixup(void) 451 { 452 struct pciintr_link_map *l; 453 u_int16_t pciirq = 0; 454 int irq; 455 456 /* 457 * First stage: Attempt to connect PIRQs which aren't 458 * yet connected. 459 */ 460 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 461 l = SIMPLEQ_NEXT(l, list)) { 462 if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 463 /* 464 * Interrupt is already connected. Don't do 465 * anything to it. 466 * In this case, l->fixup_stage == 0. 467 */ 468 pciirq |= 1 << l->irq; 469 if (pcibios_flags & PCIBIOS_INTRDEBUG) 470 printf("pciintr_link_fixup: PIRQ 0x%02x is " 471 "already connected to IRQ %d\n", 472 l->clink, l->irq); 473 continue; 474 } 475 /* 476 * Interrupt isn't connected. Attempt to assign it to an IRQ. 477 */ 478 if (pcibios_flags & PCIBIOS_INTRDEBUG) 479 printf("pciintr_link_fixup: PIRQ 0x%02x not connected", 480 l->clink); 481 482 /* 483 * Just do the easy case now; we'll defer the harder ones 484 * to Stage 2. 485 */ 486 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 487 l->irq = irq; 488 l->fixup_stage = 1; 489 pciirq |= 1 << irq; 490 if (pcibios_flags & PCIBIOS_INTRDEBUG) 491 printf(", assigning IRQ %d", l->irq); 492 } 493 if (pcibios_flags & PCIBIOS_INTRDEBUG) 494 printf("\n"); 495 } 496 497 /* 498 * Stage 2: Attempt to connect PIRQs which we didn't 499 * connect in Stage 1. 500 */ 501 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 502 l = SIMPLEQ_NEXT(l, list)) 503 if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION && 504 (irq = ffs(l->bitmap & pciirq)) > 0) { 505 /* 506 * This IRQ is a valid PCI IRQ already 507 * connected to another PIRQ, and also an 508 * IRQ our PIRQ can use; connect it up! 509 */ 510 l->fixup_stage = 2; 511 l->irq = irq - 1; 512 if (pcibios_flags & PCIBIOS_INTRDEBUG) 513 printf("pciintr_link_fixup (stage 2): " 514 "assigning IRQ %d to PIRQ 0x%02x\n", 515 l->irq, l->clink); 516 } 517 518 #ifdef PCIBIOS_IRQS_HINT 519 /* 520 * Stage 3: The worst case. I need configuration hint that 521 * user supplied a mask for the PCI irqs 522 */ 523 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 524 l = SIMPLEQ_NEXT(l, list)) { 525 if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION && 526 (irq = ffs(l->bitmap & pcibios_irqs_hint)) > 0) { 527 l->fixup_stage = 3; 528 l->irq = irq - 1; 529 if (pcibios_flags & PCIBIOS_INTRDEBUG) 530 printf("pciintr_link_fixup (stage 3): " 531 "assigning IRQ %d to PIRQ 0x%02x\n", 532 l->irq, l->clink); 533 } 534 } 535 #endif /* PCIBIOS_IRQS_HINT */ 536 537 if (pcibios_flags & PCIBIOS_INTRDEBUG) 538 printf("pciintr_link_fixup: piirq 0x%04x\n", pciirq); 539 540 return (0); 541 } 542 543 int 544 pci_intr_route_link(pci_chipset_tag_t pc, pci_intr_handle_t *ihp) 545 { 546 struct pciintr_link_map *l; 547 pcireg_t intr; 548 int irq, rv = 1; 549 char *p = NULL; 550 551 if (pcibios_flags & PCIBIOS_INTR_FIXUP) 552 return 1; 553 554 irq = ihp->line & APIC_INT_LINE_MASK; 555 if (irq != 0 && irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 556 pcibios_pir_header.exclusive_irq |= 1 << irq; 557 558 l = ihp->link; 559 if (!l || pciintr_icu_tag == NULL) 560 return (1); 561 562 if (l->fixup_stage == 0) { 563 if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 564 /* Appropriate interrupt was not found. */ 565 if (pcibios_flags & PCIBIOS_INTRDEBUG) 566 printf("pci_intr_route_link: PIRQ 0x%02x: " 567 "no IRQ, try " 568 "\"option PCIBIOS_IRQS_HINT=0x%04x\"\n", 569 l->clink, 570 /* suggest irq 9/10/11, if possible */ 571 (l->bitmap & 0x0e00) ? (l->bitmap & 0x0e00) 572 : l->bitmap); 573 } else 574 p = " preserved BIOS setting"; 575 } else { 576 577 if (pciintr_icu_set_intr(pciintr_icu_tag, pciintr_icu_handle, 578 l->clink, l->irq) != 0 || 579 pciintr_icu_set_trigger(pciintr_icu_tag, pciintr_icu_handle, 580 l->irq, IST_LEVEL) != 0) { 581 p = " failed"; 582 rv = 0; 583 } else 584 p = ""; 585 } 586 if (p && pcibios_flags & PCIBIOS_INTRDEBUG) 587 printf("pci_intr_route_link: route PIRQ 0x%02x -> IRQ %d%s\n", 588 l->clink, l->irq, p); 589 590 if (!rv) 591 return (0); 592 593 /* 594 * IRQs 14 and 15 are reserved for PCI IDE interrupts; don't muck 595 * with them. 596 */ 597 if (irq == 14 || irq == 15) 598 return (1); 599 600 intr = pci_conf_read(pc, ihp->tag, PCI_INTERRUPT_REG); 601 if (irq != PCI_INTERRUPT_LINE(intr)) { 602 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 603 intr |= irq << PCI_INTERRUPT_LINE_SHIFT; 604 pci_conf_write(pc, ihp->tag, PCI_INTERRUPT_REG, intr); 605 } 606 607 return (1); 608 } 609 610 int 611 pci_intr_post_fixup(void) 612 { 613 struct pciintr_link_map *l; 614 int i, pciirq; 615 616 if (pcibios_flags & PCIBIOS_INTR_FIXUP) 617 return 1; 618 619 if (!pciintr_icu_handle) 620 return 0; 621 622 pciirq = pcibios_pir_header.exclusive_irq; 623 if (pcibios_flags & PCIBIOS_INTRDEBUG) 624 printf("pci_intr_post_fixup: PCI IRQs:"); 625 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); 626 l != NULL; l = SIMPLEQ_NEXT(l, list)) 627 if (l->fixup_stage == 0 && l->irq != 0 && 628 l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 629 if (pcibios_flags & PCIBIOS_INTRDEBUG) 630 printf(" %d", l->irq); 631 pciirq |= (1 << l->irq); 632 } 633 634 if (pcibios_flags & PCIBIOS_INTRDEBUG) 635 printf("; ISA IRQs:"); 636 for (i = 0; i < 16; i++) 637 if (!(pciirq & (1 << i))) { 638 if (pcibios_flags & PCIBIOS_INTRDEBUG) 639 printf(" %d", i); 640 pciintr_icu_set_trigger(pciintr_icu_tag, 641 pciintr_icu_handle, i, IST_EDGE); 642 } 643 644 if (pcibios_flags & PCIBIOS_INTRDEBUG) 645 printf("\n"); 646 647 return (0); 648 } 649 650 int 651 pci_intr_header_fixup(pci_chipset_tag_t pc, pcitag_t tag, 652 pci_intr_handle_t *ihp) 653 { 654 struct pcibios_intr_routing *pir; 655 struct pciintr_link_map *l; 656 int irq, link, bus, device, function; 657 char *p = NULL; 658 659 if (pcibios_flags & PCIBIOS_INTR_FIXUP) 660 return 1; 661 662 irq = ihp->line & APIC_INT_LINE_MASK; 663 ihp->link = NULL; 664 pci_decompose_tag(pc, tag, &bus, &device, &function); 665 666 if ((pir = pciintr_pir_lookup(bus, device)) == NULL || 667 (link = pir->linkmap[ihp->pin - 1].link) == 0) { 668 PCIBIOS_PRINTV(("Interrupt not connected; no need to change.")); 669 return 1; 670 } 671 672 if ((l = pciintr_link_lookup(link)) == NULL) { 673 /* 674 * No link map entry. 675 * Probably pciintr_icu_getclink() or pciintr_icu_get_intr() 676 * has failed. 677 */ 678 if (pcibios_flags & PCIBIOS_INTRDEBUG) 679 printf("pci_intr_header_fixup: no entry for link " 680 "0x%02x (%d:%d:%d:%c)\n", 681 link, bus, device, function, '@' + ihp->pin); 682 return 1; 683 } 684 685 ihp->link = l; 686 if (irq == 14 || irq == 15) { 687 p = " WARNING: ignored"; 688 ihp->link = NULL; 689 } else if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 690 691 /* Appropriate interrupt was not found. */ 692 if (pciintr_icu_tag == NULL && irq != 0 && 693 irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 694 /* 695 * Do not print warning, 696 * if no compatible PCI ICU found, 697 * but the irq is already assigned by BIOS. 698 */ 699 p = ""; 700 else 701 p = " WARNING: missing"; 702 } else if (irq == 0 || irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 703 704 p = " fixed up"; 705 ihp->line = irq = l->irq; 706 707 } else if (pcibios_flags & PCIBIOS_FIXUP_FORCE) { 708 /* routed by BIOS, but inconsistent */ 709 /* believe PCI IRQ Routing table */ 710 p = " WARNING: overriding"; 711 ihp->line = irq = l->irq; 712 } else { 713 /* believe PCI Interrupt Configuration Register (default) */ 714 p = " WARNING: preserving"; 715 ihp->line = (l->irq = irq) | (l->clink & PCI_INT_VIA_ISA); 716 } 717 718 if (pcibios_flags & PCIBIOS_INTRDEBUG) { 719 pcireg_t id = pci_conf_read(pc, tag, PCI_ID_REG); 720 721 printf("\n%d:%d:%d %04x:%04x pin %c clink 0x%02x irq %d " 722 "stage %d %s irq %d\n", bus, device, function, 723 PCI_VENDOR(id), PCI_PRODUCT(id), '@' + ihp->pin, l->clink, 724 ((l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION)? 725 -1 : l->irq), l->fixup_stage, p, irq); 726 } 727 728 return (1); 729 } 730 731 int 732 pci_intr_fixup(struct pcibios_softc *sc, pci_chipset_tag_t pc, 733 bus_space_tag_t iot) 734 { 735 struct pcibios_pir_header *pirh = &pcibios_pir_header; 736 const struct pciintr_icu_table *piit = NULL; 737 pcitag_t icutag; 738 739 /* 740 * Attempt to initialize our PCI interrupt router. If 741 * the PIR Table is present in ROM, use the location 742 * specified by the PIR Table, and use the compat ID, 743 * if present. Otherwise, we have to look for the router 744 * ourselves (the PCI-ISA bridge). 745 * 746 * A number of buggy BIOS implementations leave the router 747 * entry as 000:00:0, which is typically not the correct 748 * device/function. If the router device address is set to 749 * this value, and the compatible router entry is undefined 750 * (zero is the correct value to indicate undefined), then we 751 * work on the basis it is most likely an error, and search 752 * the entire device-space of bus 0 (but obviously starting 753 * with 000:00:0, in case that really is the right one). 754 */ 755 if (pirh->signature != 0 && (pirh->router_bus != 0 || 756 pirh->router_devfunc != 0 || pirh->compat_router != 0)) { 757 758 icutag = pci_make_tag(pc, pirh->router_bus, 759 PIR_DEVFUNC_DEVICE(pirh->router_devfunc), 760 PIR_DEVFUNC_FUNCTION(pirh->router_devfunc)); 761 if (pirh->compat_router == 0 || 762 (piit = pciintr_icu_lookup(pirh->compat_router)) == NULL) { 763 /* 764 * No compat ID, or don't know the compat ID? Read 765 * it from the configuration header. 766 */ 767 pirh->compat_router = pci_conf_read(pc, icutag, 768 PCI_ID_REG); 769 } 770 if (piit == NULL) 771 piit = pciintr_icu_lookup(pirh->compat_router); 772 } else { 773 int device, maxdevs = pci_bus_maxdevs(pc, 0); 774 775 /* 776 * Search configuration space for a known interrupt 777 * router. 778 */ 779 for (device = 0; device < maxdevs; device++) { 780 const struct pci_quirkdata *qd; 781 int function, nfuncs; 782 pcireg_t icuid; 783 pcireg_t bhlcr; 784 785 icutag = pci_make_tag(pc, 0, device, 0); 786 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 787 788 /* Invalid vendor ID value? */ 789 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 790 continue; 791 /* XXX Not invalid, but we've done this ~forever. */ 792 if (PCI_VENDOR(icuid) == 0) 793 continue; 794 795 qd = pci_lookup_quirkdata(PCI_VENDOR(icuid), 796 PCI_PRODUCT(icuid)); 797 798 bhlcr = pci_conf_read(pc, icutag, PCI_BHLC_REG); 799 if (PCI_HDRTYPE_MULTIFN(bhlcr) || (qd != NULL && 800 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 801 nfuncs = 8; 802 else 803 nfuncs = 1; 804 805 for (function = 0; function < nfuncs; function++) { 806 icutag = pci_make_tag(pc, 0, device, function); 807 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 808 809 /* Invalid vendor ID value? */ 810 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 811 continue; 812 /* Not invalid, but we've done this ~forever. */ 813 if (PCI_VENDOR(icuid) == 0) 814 continue; 815 816 if ((piit = pciintr_icu_lookup(icuid))) { 817 pirh->compat_router = icuid; 818 pirh->router_bus = 0; 819 pirh->router_devfunc = 820 PIR_DEVFUNC_COMPOSE(device, 0); 821 break; 822 } 823 } 824 825 if (piit != NULL) 826 break; 827 } 828 } 829 830 if (piit == NULL) { 831 printf("%s: no compatible PCI ICU found", sc->sc_dev.dv_xname); 832 if (pirh->signature != 0 && pirh->compat_router != 0) 833 printf(": ICU vendor 0x%04x product 0x%04x", 834 PCI_VENDOR(pirh->compat_router), 835 PCI_PRODUCT(pirh->compat_router)); 836 printf("\n"); 837 if (!(pcibios_flags & PCIBIOS_INTR_GUESS)) { 838 if (pciintr_link_init(pc)) 839 return (-1); /* non-fatal */ 840 if (pciintr_guess_irq()) 841 return (-1); /* non-fatal */ 842 } 843 return (0); 844 } else { 845 char devinfo[256]; 846 847 printf("%s: PCI Interrupt Router at %03d:%02d:%01d", 848 sc->sc_dev.dv_xname, pirh->router_bus, 849 PIR_DEVFUNC_DEVICE(pirh->router_devfunc), 850 PIR_DEVFUNC_FUNCTION(pirh->router_devfunc)); 851 if (pirh->compat_router != 0) { 852 pci_devinfo(pirh->compat_router, 0, 0, devinfo, 853 sizeof devinfo); 854 printf(" (%s)", devinfo); 855 } 856 printf("\n"); 857 } 858 859 /* 860 * Initialize the PCI ICU. 861 */ 862 if ((*piit->piit_init)(pc, iot, icutag, &pciintr_icu_tag, 863 &pciintr_icu_handle) != 0) 864 return (-1); /* non-fatal */ 865 866 /* 867 * Initialize the PCI interrupt link map. 868 */ 869 if (pciintr_link_init(pc)) 870 return (-1); /* non-fatal */ 871 872 /* 873 * Fix up the link->IRQ mappings. 874 */ 875 if (pciintr_link_fixup() != 0) 876 return (-1); /* non-fatal */ 877 878 return (0); 879 } 880