1 /* $OpenBSD: pci_machdep.c,v 1.77 2013/11/06 10:40:36 mpi Exp $ */ 2 /* $NetBSD: pci_machdep.c,v 1.28 1997/06/06 23:29:17 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1997 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * Copyright (c) 1994 Charles Hannum. All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Charles Hannum. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Machine-specific functions for PCI autoconfiguration. 66 * 67 * On PCs, there are two methods of generating PCI configuration cycles. 68 * We try to detect the appropriate mechanism for this machine and set 69 * up a few function pointers to access the correct method directly. 70 * 71 * The configuration method can be hard-coded in the config file by 72 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 73 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 74 */ 75 76 #include <sys/types.h> 77 #include <sys/param.h> 78 #include <sys/time.h> 79 #include <sys/systm.h> 80 #include <sys/errno.h> 81 #include <sys/device.h> 82 #include <sys/extent.h> 83 #include <sys/malloc.h> 84 85 #include <uvm/uvm_extern.h> 86 87 #include <machine/bus.h> 88 #include <machine/pio.h> 89 #include <machine/i8259.h> 90 #include <machine/biosvar.h> 91 92 #include "bios.h" 93 #if NBIOS > 0 94 extern bios_pciinfo_t *bios_pciinfo; 95 #endif 96 97 #include <dev/isa/isavar.h> 98 #include <dev/pci/pcivar.h> 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcidevs.h> 101 #include <dev/pci/ppbreg.h> 102 103 #include "ioapic.h" 104 105 #include <machine/i82093var.h> 106 #include <machine/i82489reg.h> 107 #include <machine/i82489var.h> 108 #if NIOAPIC > 0 109 #include <machine/mpbiosvar.h> 110 #endif 111 112 #include "pcibios.h" 113 #if NPCIBIOS > 0 114 #include <i386/pci/pcibiosvar.h> 115 #endif 116 117 int pci_mode = -1; 118 119 /* 120 * Memory Mapped Configuration space access. 121 * 122 * Since mapping the whole configuration space will cost us up to 123 * 256MB of kernel virtual memory, we use seperate mappings per bus. 124 * The mappings are created on-demand, such that we only use kernel 125 * virtual memory for busses that are actually present. 126 */ 127 bus_addr_t pci_mcfg_addr; 128 int pci_mcfg_min_bus, pci_mcfg_max_bus; 129 bus_space_tag_t pci_mcfgt = I386_BUS_SPACE_MEM; 130 bus_space_handle_t pci_mcfgh[256]; 131 void pci_mcfg_map_bus(int); 132 133 struct mutex pci_conf_lock = MUTEX_INITIALIZER(IPL_HIGH); 134 135 #define PCI_CONF_LOCK() \ 136 do { \ 137 mtx_enter(&pci_conf_lock); \ 138 } while (0) 139 140 #define PCI_CONF_UNLOCK() \ 141 do { \ 142 mtx_leave(&pci_conf_lock); \ 143 } while (0) 144 145 #define PCI_MODE1_ENABLE 0x80000000UL 146 #define PCI_MODE1_ADDRESS_REG 0x0cf8 147 #define PCI_MODE1_DATA_REG 0x0cfc 148 149 #define PCI_MODE2_ENABLE_REG 0x0cf8 150 #define PCI_MODE2_FORWARD_REG 0x0cfa 151 152 #define _m1tag(b, d, f) \ 153 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 154 #define _qe(bus, dev, fcn, vend, prod) \ 155 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 156 struct { 157 u_int32_t tag; 158 pcireg_t id; 159 } pcim1_quirk_tbl[] = { 160 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 161 /* XXX Triflex2 not tested */ 162 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 163 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 164 /* Triton needed for Connectix Virtual PC */ 165 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 166 /* Connectix Virtual PC 5 has a 440BX */ 167 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 168 {0, 0xffffffff} /* patchable */ 169 }; 170 #undef _m1tag 171 #undef _qe 172 173 /* 174 * PCI doesn't have any special needs; just use the generic versions 175 * of these functions. 176 */ 177 struct bus_dma_tag pci_bus_dma_tag = { 178 NULL, /* _cookie */ 179 _bus_dmamap_create, 180 _bus_dmamap_destroy, 181 _bus_dmamap_load, 182 _bus_dmamap_load_mbuf, 183 _bus_dmamap_load_uio, 184 _bus_dmamap_load_raw, 185 _bus_dmamap_unload, 186 _bus_dmamap_sync, 187 _bus_dmamem_alloc, 188 _bus_dmamem_free, 189 _bus_dmamem_map, 190 _bus_dmamem_unmap, 191 _bus_dmamem_mmap, 192 }; 193 194 void 195 pci_attach_hook(struct device *parent, struct device *self, 196 struct pcibus_attach_args *pba) 197 { 198 pci_chipset_tag_t pc = pba->pba_pc; 199 pcitag_t tag; 200 pcireg_t id, class; 201 202 #if NBIOS > 0 203 if (pba->pba_bus == 0) 204 printf(": configuration mode %d (%s)", 205 pci_mode, (bios_pciinfo?"bios":"no bios")); 206 #else 207 if (pba->pba_bus == 0) 208 printf(": configuration mode %d", pci_mode); 209 #endif 210 211 if (pba->pba_bus != 0) 212 return; 213 214 /* 215 * Machines that use the non-standard method of generating PCI 216 * configuration cycles are way too old to support MSI. 217 */ 218 if (pci_mode == 2) 219 return; 220 221 /* 222 * In order to decide whether the system supports MSI we look 223 * at the host bridge, which should be device 0 function 0 on 224 * bus 0. It is better to not enable MSI on systems that 225 * support it than the other way around, so be conservative 226 * here. So we don't enable MSI if we don't find a host 227 * bridge there. We also deliberately don't enable MSI on 228 * chipsets from low-end manifacturers like VIA and SiS. 229 */ 230 tag = pci_make_tag(pc, 0, 0, 0); 231 id = pci_conf_read(pc, tag, PCI_ID_REG); 232 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 233 234 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 235 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_HOST) 236 return; 237 238 switch (PCI_VENDOR(id)) { 239 case PCI_VENDOR_INTEL: 240 /* 241 * For Intel platforms, MSI support was introduced 242 * with the new Pentium 4 processor interrupt delivery 243 * mechanism, so we blacklist all PCI chipsets that 244 * support Pentium III and earlier CPUs. 245 */ 246 switch (PCI_PRODUCT(id)) { 247 case PCI_PRODUCT_INTEL_PCMC: /* 82434LX/NX */ 248 case PCI_PRODUCT_INTEL_82437FX: 249 case PCI_PRODUCT_INTEL_82437MX: 250 case PCI_PRODUCT_INTEL_82437VX: 251 case PCI_PRODUCT_INTEL_82439HX: 252 case PCI_PRODUCT_INTEL_82439TX: 253 case PCI_PRODUCT_INTEL_82440BX: 254 case PCI_PRODUCT_INTEL_82440BX_AGP: 255 case PCI_PRODUCT_INTEL_82440MX_HB: 256 case PCI_PRODUCT_INTEL_82441FX: 257 case PCI_PRODUCT_INTEL_82443BX: 258 case PCI_PRODUCT_INTEL_82443BX_AGP: 259 case PCI_PRODUCT_INTEL_82443BX_NOAGP: 260 case PCI_PRODUCT_INTEL_82443GX: 261 case PCI_PRODUCT_INTEL_82443LX: 262 case PCI_PRODUCT_INTEL_82443LX_AGP: 263 case PCI_PRODUCT_INTEL_82810_HB: 264 case PCI_PRODUCT_INTEL_82810E_HB: 265 case PCI_PRODUCT_INTEL_82815_HB: 266 case PCI_PRODUCT_INTEL_82820_HB: 267 case PCI_PRODUCT_INTEL_82830M_HB: 268 case PCI_PRODUCT_INTEL_82840_HB: 269 break; 270 default: 271 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED; 272 break; 273 } 274 break; 275 case PCI_VENDOR_NVIDIA: 276 /* 277 * Since NVIDIA chipsets are completely undocumented, 278 * we have to make a guess here. We assume that all 279 * chipsets that support PCIe include support for MSI, 280 * since support for MSI is mandated by the PCIe 281 * standard. 282 */ 283 switch (PCI_PRODUCT(id)) { 284 case PCI_PRODUCT_NVIDIA_NFORCE_PCHB: 285 case PCI_PRODUCT_NVIDIA_NFORCE2_PCHB: 286 break; 287 default: 288 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED; 289 break; 290 } 291 break; 292 case PCI_VENDOR_AMD: 293 /* 294 * The AMD-750 and AMD-760 chipsets don't support MSI. 295 */ 296 switch (PCI_PRODUCT(id)) { 297 case PCI_PRODUCT_AMD_SC751_SC: 298 case PCI_PRODUCT_AMD_761_PCHB: 299 case PCI_PRODUCT_AMD_762_PCHB: 300 break; 301 default: 302 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED; 303 break; 304 } 305 break; 306 } 307 308 /* 309 * Don't enable MSI on a HyperTransport bus. In order to 310 * determine that bus 0 is a HyperTransport bus, we look at 311 * device 24 function 0, which is the HyperTransport 312 * host/primary interface integrated on most 64-bit AMD CPUs. 313 * If that device has a HyperTransport capability, bus 0 must 314 * be a HyperTransport bus and we disable MSI. 315 */ 316 tag = pci_make_tag(pc, 0, 24, 0); 317 if (pci_get_capability(pc, tag, PCI_CAP_HT, NULL, NULL)) 318 pba->pba_flags &= ~PCI_FLAGS_MSI_ENABLED; 319 } 320 321 int 322 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 323 { 324 325 /* 326 * Bus number is irrelevant. If Configuration Mechanism 2 is in 327 * use, can only have devices 0-15 on any bus. If Configuration 328 * Mechanism 1 is in use, can have devices 0-31 (i.e. the `normal' 329 * range). 330 */ 331 if (pci_mode == 2) 332 return (16); 333 else 334 return (32); 335 } 336 337 pcitag_t 338 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 339 { 340 pcitag_t tag; 341 342 switch (pci_mode) { 343 case 1: 344 if (bus >= 256 || device >= 32 || function >= 8) 345 panic("pci_make_tag: bad request"); 346 347 tag.mode1 = PCI_MODE1_ENABLE | 348 (bus << 16) | (device << 11) | (function << 8); 349 break; 350 case 2: 351 if (bus >= 256 || device >= 16 || function >= 8) 352 panic("pci_make_tag: bad request"); 353 354 tag.mode2.port = 0xc000 | (device << 8); 355 tag.mode2.enable = 0xf0 | (function << 1); 356 tag.mode2.forward = bus; 357 break; 358 default: 359 panic("pci_make_tag: mode not configured"); 360 } 361 362 return tag; 363 } 364 365 void 366 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp) 367 { 368 switch (pci_mode) { 369 case 1: 370 if (bp != NULL) 371 *bp = (tag.mode1 >> 16) & 0xff; 372 if (dp != NULL) 373 *dp = (tag.mode1 >> 11) & 0x1f; 374 if (fp != NULL) 375 *fp = (tag.mode1 >> 8) & 0x7; 376 break; 377 case 2: 378 if (bp != NULL) 379 *bp = tag.mode2.forward & 0xff; 380 if (dp != NULL) 381 *dp = (tag.mode2.port >> 8) & 0xf; 382 if (fp != NULL) 383 *fp = (tag.mode2.enable >> 1) & 0x7; 384 break; 385 default: 386 panic("pci_decompose_tag: mode not configured"); 387 } 388 } 389 390 int 391 pci_conf_size(pci_chipset_tag_t pc, pcitag_t tag) 392 { 393 int bus; 394 395 if (pci_mcfg_addr) { 396 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 397 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) 398 return PCIE_CONFIG_SPACE_SIZE; 399 } 400 401 return PCI_CONFIG_SPACE_SIZE; 402 } 403 404 void 405 pci_mcfg_map_bus(int bus) 406 { 407 if (pci_mcfgh[bus]) 408 return; 409 410 if (bus_space_map(pci_mcfgt, pci_mcfg_addr + (bus << 20), 1 << 20, 411 0, &pci_mcfgh[bus])) 412 panic("pci_conf_read: cannot map mcfg space"); 413 } 414 415 pcireg_t 416 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 417 { 418 pcireg_t data; 419 int bus; 420 421 KASSERT((reg & 0x3) == 0); 422 423 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) { 424 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 425 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) { 426 pci_mcfg_map_bus(bus); 427 data = bus_space_read_4(pci_mcfgt, pci_mcfgh[bus], 428 (tag.mode1 & 0x000ff00) << 4 | reg); 429 return data; 430 } 431 } 432 433 PCI_CONF_LOCK(); 434 switch (pci_mode) { 435 case 1: 436 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 437 data = inl(PCI_MODE1_DATA_REG); 438 outl(PCI_MODE1_ADDRESS_REG, 0); 439 break; 440 case 2: 441 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 442 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 443 data = inl(tag.mode2.port | reg); 444 outb(PCI_MODE2_ENABLE_REG, 0); 445 break; 446 default: 447 panic("pci_conf_read: mode not configured"); 448 } 449 PCI_CONF_UNLOCK(); 450 451 return data; 452 } 453 454 void 455 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 456 { 457 int bus; 458 459 KASSERT((reg & 0x3) == 0); 460 461 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) { 462 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 463 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) { 464 pci_mcfg_map_bus(bus); 465 bus_space_write_4(pci_mcfgt, pci_mcfgh[bus], 466 (tag.mode1 & 0x000ff00) << 4 | reg, data); 467 return; 468 } 469 } 470 471 PCI_CONF_LOCK(); 472 switch (pci_mode) { 473 case 1: 474 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 475 outl(PCI_MODE1_DATA_REG, data); 476 outl(PCI_MODE1_ADDRESS_REG, 0); 477 break; 478 case 2: 479 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 480 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 481 outl(tag.mode2.port | reg, data); 482 outb(PCI_MODE2_ENABLE_REG, 0); 483 break; 484 default: 485 panic("pci_conf_write: mode not configured"); 486 } 487 PCI_CONF_UNLOCK(); 488 } 489 490 int 491 pci_mode_detect(void) 492 { 493 494 #ifdef PCI_CONF_MODE 495 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 496 return (pci_mode = PCI_CONF_MODE); 497 #else 498 #error Invalid PCI configuration mode. 499 #endif 500 #else 501 u_int32_t sav, val; 502 int i; 503 pcireg_t idreg; 504 505 if (pci_mode != -1) 506 return (pci_mode); 507 508 #if NBIOS > 0 509 /* 510 * If we have PCI info passed from the BIOS, use the mode given there 511 * for all of this code. If not, pass on through to the previous tests 512 * to try and divine the correct mode. 513 */ 514 if (bios_pciinfo != NULL) { 515 if (bios_pciinfo->pci_chars & 0x2) 516 return (pci_mode = 2); 517 518 if (bios_pciinfo->pci_chars & 0x1) 519 return (pci_mode = 1); 520 521 /* We should never get here, but if we do, fall through... */ 522 } 523 #endif 524 525 /* 526 * We try to divine which configuration mode the host bridge wants. 527 * 528 * This should really be done using the PCI BIOS. If we get here, the 529 * PCI BIOS does not exist, or the boot blocks did not provide the 530 * information. 531 */ 532 533 sav = inl(PCI_MODE1_ADDRESS_REG); 534 535 pci_mode = 1; /* assume this for now */ 536 /* 537 * catch some known buggy implementations of mode 1 538 */ 539 for (i = 0; i < sizeof(pcim1_quirk_tbl) / sizeof(pcim1_quirk_tbl[0]); 540 i++) { 541 pcitag_t t; 542 543 if (!pcim1_quirk_tbl[i].tag) 544 break; 545 t.mode1 = pcim1_quirk_tbl[i].tag; 546 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 547 if (idreg == pcim1_quirk_tbl[i].id) { 548 #ifdef DEBUG 549 printf("known mode 1 PCI chipset (%08x)\n", 550 idreg); 551 #endif 552 return (pci_mode); 553 } 554 } 555 556 /* 557 * Strong check for standard compliant mode 1: 558 * 1. bit 31 ("enable") can be set 559 * 2. byte/word access does not affect register 560 */ 561 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 562 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 563 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 564 val = inl(PCI_MODE1_ADDRESS_REG); 565 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 566 #ifdef DEBUG 567 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 568 val); 569 #endif 570 goto not1; 571 } 572 outl(PCI_MODE1_ADDRESS_REG, 0); 573 val = inl(PCI_MODE1_ADDRESS_REG); 574 if ((val & 0x80fffffc) != 0) 575 goto not1; 576 return (pci_mode); 577 not1: 578 outl(PCI_MODE1_ADDRESS_REG, sav); 579 580 /* 581 * This mode 2 check is quite weak (and known to give false 582 * positives on some Compaq machines). 583 * However, this doesn't matter, because this is the 584 * last test, and simply no PCI devices will be found if 585 * this happens. 586 */ 587 outb(PCI_MODE2_ENABLE_REG, 0); 588 outb(PCI_MODE2_FORWARD_REG, 0); 589 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 590 inb(PCI_MODE2_FORWARD_REG) != 0) 591 goto not2; 592 return (pci_mode = 2); 593 not2: 594 return (pci_mode = 0); 595 #endif 596 } 597 598 int 599 pci_intr_map_msi(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 600 { 601 pci_chipset_tag_t pc = pa->pa_pc; 602 pcitag_t tag = pa->pa_tag; 603 604 if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 || mp_busses == NULL || 605 pci_get_capability(pc, tag, PCI_CAP_MSI, NULL, NULL) == 0) 606 return 1; 607 608 ihp->tag = tag; 609 ihp->line = APIC_INT_VIA_MSG; 610 ihp->pin = 0; 611 return 0; 612 } 613 614 int 615 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 616 { 617 int pin = pa->pa_rawintrpin; 618 int line = pa->pa_intrline; 619 #if NIOAPIC > 0 620 struct mp_intr_map *mip; 621 int bus, dev, func; 622 #endif 623 624 if (pin == 0) { 625 /* No IRQ used. */ 626 goto bad; 627 } 628 629 if (pin > PCI_INTERRUPT_PIN_MAX) { 630 printf("pci_intr_map: bad interrupt pin %d\n", pin); 631 goto bad; 632 } 633 634 ihp->tag = pa->pa_tag; 635 ihp->line = line; 636 ihp->pin = pin; 637 638 #if NIOAPIC > 0 639 pci_decompose_tag (pa->pa_pc, pa->pa_tag, &bus, &dev, &func); 640 641 if (!(ihp->line & PCI_INT_VIA_ISA) && mp_busses != NULL) { 642 int mpspec_pin = (dev << 2) | (pin - 1); 643 644 if (bus < mp_nbusses) { 645 for (mip = mp_busses[bus].mb_intrs; 646 mip != NULL; mip = mip->next) { 647 if (&mp_busses[bus] == mp_isa_bus || 648 &mp_busses[bus] == mp_eisa_bus) 649 continue; 650 if (mip->bus_pin == mpspec_pin) { 651 ihp->line = mip->ioapic_ih | line; 652 return 0; 653 } 654 } 655 } 656 657 if (pa->pa_bridgetag) { 658 int swizpin = PPB_INTERRUPT_SWIZZLE(pin, dev); 659 if (pa->pa_bridgeih[swizpin - 1].line != -1) { 660 ihp->line = pa->pa_bridgeih[swizpin - 1].line; 661 ihp->line |= line; 662 return 0; 663 } 664 } 665 /* 666 * No explicit PCI mapping found. This is not fatal, 667 * we'll try the ISA (or possibly EISA) mappings next. 668 */ 669 } 670 #endif 671 672 #if NPCIBIOS > 0 673 pci_intr_header_fixup(pa->pa_pc, pa->pa_tag, ihp); 674 line = ihp->line & APIC_INT_LINE_MASK; 675 #endif 676 677 /* 678 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 679 * `unknown' or `no connection' on a PC. We assume that a device with 680 * `no connection' either doesn't have an interrupt (in which case the 681 * pin number should be 0, and would have been noticed above), or 682 * wasn't configured by the BIOS (in which case we punt, since there's 683 * no real way we can know how the interrupt lines are mapped in the 684 * hardware). 685 * 686 * XXX 687 * Since IRQ 0 is only used by the clock, and we can't actually be sure 688 * that the BIOS did its job, we also recognize that as meaning that 689 * the BIOS has not configured the device. 690 */ 691 if (line == 0 || line == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 692 goto bad; 693 694 if (line >= ICU_LEN) { 695 printf("pci_intr_map: bad interrupt line %d\n", line); 696 goto bad; 697 } 698 if (line == 2) { 699 printf("pci_intr_map: changed line 2 to line 9\n"); 700 line = 9; 701 } 702 703 #if NIOAPIC > 0 704 if (!(ihp->line & PCI_INT_VIA_ISA) && mp_busses != NULL) { 705 if (mip == NULL && mp_isa_bus) { 706 for (mip = mp_isa_bus->mb_intrs; mip != NULL; 707 mip = mip->next) { 708 if (mip->bus_pin == line) { 709 ihp->line = mip->ioapic_ih | line; 710 return 0; 711 } 712 } 713 } 714 if (mip == NULL && mp_eisa_bus) { 715 for (mip = mp_eisa_bus->mb_intrs; mip != NULL; 716 mip = mip->next) { 717 if (mip->bus_pin == line) { 718 ihp->line = mip->ioapic_ih | line; 719 return 0; 720 } 721 } 722 } 723 if (mip == NULL) { 724 printf("pci_intr_map: " 725 "bus %d dev %d func %d pin %d; line %d\n", 726 bus, dev, func, pin, line); 727 printf("pci_intr_map: no MP mapping found\n"); 728 } 729 } 730 #endif 731 732 return 0; 733 734 bad: 735 ihp->line = -1; 736 return 1; 737 } 738 739 const char * 740 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 741 { 742 static char irqstr[64]; 743 int line = ih.line & APIC_INT_LINE_MASK; 744 745 if (ih.line & APIC_INT_VIA_MSG) 746 return ("msi"); 747 748 #if NIOAPIC > 0 749 if (ih.line & APIC_INT_VIA_APIC) { 750 snprintf(irqstr, sizeof irqstr, "apic %d int %d", 751 APIC_IRQ_APIC(ih.line), APIC_IRQ_PIN(ih.line)); 752 return (irqstr); 753 } 754 #endif 755 756 if (line == 0 || line >= ICU_LEN || line == 2) 757 panic("pci_intr_string: bogus handle 0x%x", line); 758 759 snprintf(irqstr, sizeof irqstr, "irq %d", line); 760 return (irqstr); 761 } 762 763 #include "acpiprt.h" 764 #if NACPIPRT > 0 765 void acpiprt_route_interrupt(int bus, int dev, int pin); 766 #endif 767 768 extern struct intrhand *apic_intrhand[256]; 769 extern int apic_maxlevel[256]; 770 771 void * 772 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 773 int (*func)(void *), void *arg, const char *what) 774 { 775 void *ret; 776 int bus, dev; 777 int l = ih.line & APIC_INT_LINE_MASK; 778 pcitag_t tag = ih.tag; 779 int irq = ih.line; 780 781 if (ih.line & APIC_INT_VIA_MSG) { 782 struct intrhand *ih; 783 pcireg_t reg, addr; 784 int off, vec; 785 int flags; 786 787 flags = level & IPL_MPSAFE; 788 level &= ~IPL_MPSAFE; 789 790 KASSERT(level <= IPL_TTY || flags & IPL_MPSAFE); 791 792 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0) 793 panic("%s: no msi capability", __func__); 794 795 vec = idt_vec_alloc(level, level + 15); 796 if (vec == 0) 797 return (NULL); 798 799 ih = malloc(sizeof(*ih), M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 800 if (ih == NULL) 801 panic("%s: can't malloc handler info", __func__); 802 803 ih->ih_fun = func; 804 ih->ih_arg = arg; 805 ih->ih_next = NULL; 806 ih->ih_level = level; 807 ih->ih_flags = flags; 808 ih->ih_irq = irq; 809 ih->ih_pin = tag.mode1; 810 ih->ih_vec = vec; 811 evcount_attach(&ih->ih_count, what, &ih->ih_vec); 812 813 apic_maxlevel[vec] = level; 814 apic_intrhand[vec] = ih; 815 idt_vec_set(vec, apichandler[vec & 0xf]); 816 817 addr = 0xfee00000UL | (cpu_info_primary.ci_apicid << 12); 818 819 if (reg & PCI_MSI_MC_C64) { 820 pci_conf_write(pc, tag, off + PCI_MSI_MA, addr); 821 pci_conf_write(pc, tag, off + PCI_MSI_MAU32, 0); 822 pci_conf_write(pc, tag, off + PCI_MSI_MD64, vec); 823 } else { 824 pci_conf_write(pc, tag, off + PCI_MSI_MA, addr); 825 pci_conf_write(pc, tag, off + PCI_MSI_MD32, vec); 826 } 827 pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE); 828 return (ih); 829 } 830 831 pci_decompose_tag(pc, ih.tag, &bus, &dev, NULL); 832 #if NACPIPRT > 0 833 acpiprt_route_interrupt(bus, dev, ih.pin); 834 #endif 835 836 #if NIOAPIC > 0 837 if (l != -1 && ih.line & APIC_INT_VIA_APIC) 838 return (apic_intr_establish(ih.line, IST_LEVEL, level, func, 839 arg, what)); 840 #endif 841 if (l == 0 || l >= ICU_LEN || l == 2) 842 panic("pci_intr_establish: bogus handle 0x%x", l); 843 844 ret = isa_intr_establish(NULL, l, IST_LEVEL, level, func, arg, what); 845 #if NPCIBIOS > 0 846 if (ret) 847 pci_intr_route_link(pc, &ih); 848 #endif 849 return (ret); 850 } 851 852 void 853 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 854 { 855 struct intrhand *ih = cookie; 856 857 if (ih->ih_irq & APIC_INT_VIA_MSG) { 858 pcitag_t tag = { .mode1 = ih->ih_pin }; 859 pcireg_t reg; 860 int off; 861 862 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0) 863 panic("%s: no msi capability", __func__); 864 865 pci_conf_write(pc, tag, off, reg &= ~PCI_MSI_MC_MSIE); 866 867 apic_maxlevel[ih->ih_vec] = 0; 868 apic_intrhand[ih->ih_vec] = NULL; 869 idt_vec_free(ih->ih_vec); 870 871 evcount_detach(&ih->ih_count); 872 free(ih, M_DEVBUF); 873 return; 874 } 875 876 /* XXX oh, unroute the pci int link? */ 877 isa_intr_disestablish(NULL, cookie); 878 } 879 880 struct extent *pciio_ex; 881 struct extent *pcimem_ex; 882 struct extent *pcibus_ex; 883 884 void 885 pci_init_extents(void) 886 { 887 bios_memmap_t *bmp; 888 u_int64_t size; 889 890 if (pciio_ex == NULL) { 891 /* 892 * We only have 64K of addressable I/O space. 893 * However, since BARs may contain garbage, we cover 894 * the full 32-bit address space defined by PCI of 895 * which we only make the first 64K available. 896 */ 897 pciio_ex = extent_create("pciio", 0, 0xffffffff, M_DEVBUF, 898 NULL, 0, EX_NOWAIT | EX_FILLED); 899 if (pciio_ex == NULL) 900 return; 901 extent_free(pciio_ex, 0, 0x10000, M_NOWAIT); 902 } 903 904 if (pcimem_ex == NULL) { 905 pcimem_ex = extent_create("pcimem", 0, 0xffffffff, M_DEVBUF, 906 NULL, 0, EX_NOWAIT); 907 if (pcimem_ex == NULL) 908 return; 909 910 for (bmp = bios_memmap; bmp->type != BIOS_MAP_END; bmp++) { 911 /* 912 * Ignore address space beyond 4G. 913 */ 914 if (bmp->addr >= 0x100000000ULL) 915 continue; 916 size = bmp->size; 917 if (bmp->addr + size >= 0x100000000ULL) 918 size = 0x100000000ULL - bmp->addr; 919 920 /* Ignore zero-sized regions. */ 921 if (size == 0) 922 continue; 923 924 if (extent_alloc_region(pcimem_ex, bmp->addr, size, 925 EX_NOWAIT)) 926 printf("memory map conflict 0x%llx/0x%llx\n", 927 bmp->addr, bmp->size); 928 } 929 930 /* Take out the video buffer area and BIOS areas. */ 931 extent_alloc_region(pcimem_ex, IOM_BEGIN, IOM_SIZE, 932 EX_CONFLICTOK | EX_NOWAIT); 933 } 934 935 if (pcibus_ex == NULL) { 936 pcibus_ex = extent_create("pcibus", 0, 0xff, M_DEVBUF, 937 NULL, 0, EX_NOWAIT); 938 } 939 } 940 941 #include "acpi.h" 942 #if NACPI > 0 943 void acpi_pci_match(struct device *, struct pci_attach_args *); 944 pcireg_t acpi_pci_min_powerstate(pci_chipset_tag_t, pcitag_t); 945 void acpi_pci_set_powerstate(pci_chipset_tag_t, pcitag_t, int, int); 946 #endif 947 948 void 949 pci_dev_postattach(struct device *dev, struct pci_attach_args *pa) 950 { 951 #if NACPI > 0 952 acpi_pci_match(dev, pa); 953 #endif 954 } 955 956 pcireg_t 957 pci_min_powerstate(pci_chipset_tag_t pc, pcitag_t tag) 958 { 959 #if NACPI > 0 960 return acpi_pci_min_powerstate(pc, tag); 961 #else 962 return pci_get_powerstate(pc, tag); 963 #endif 964 } 965 966 void 967 pci_set_powerstate_md(pci_chipset_tag_t pc, pcitag_t tag, int state, int pre) 968 { 969 #if NACPI > 0 970 acpi_pci_set_powerstate(pc, tag, state, pre); 971 #endif 972 } 973