1 /* $OpenBSD: pciide_gcsc_reg.h,v 1.2 2013/11/26 20:33:13 deraadt Exp $ */ 2 /* $NetBSD: gcscide.c,v 1.6 2007/10/06 07:21:03 xtraeme Exp $ */ 3 4 /*- 5 * Copyright (c) 2007 Juan Romero Pardines. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 30 /* 31 * 6.4 - ATA-5 Controller Register Definitions. 32 */ 33 #define GCSC_MSR_ATAC_BASE 0x51300000 34 #define GCSC_ATAC_GLD_MSR_CAP (GCSC_MSR_ATAC_BASE + 0) 35 #define GCSC_ATAC_GLD_MSR_CONFIG (GCSC_MSR_ATAC_BASE + 0x01) 36 #define GCSC_ATAC_GLD_MSR_SMI (GCSC_MSR_ATAC_BASE + 0x02) 37 #define GCSC_ATAC_GLD_MSR_ERROR (GCSC_MSR_ATAC_BASE + 0x03) 38 #define GCSC_ATAC_GLD_MSR_PM (GCSC_MSR_ATAC_BASE + 0x04) 39 #define GCSC_ATAC_GLD_MSR_DIAG (GCSC_MSR_ATAC_BASE + 0x05) 40 #define GCSC_ATAC_IO_BAR (GCSC_MSR_ATAC_BASE + 0x08) 41 #define GCSC_ATAC_RESET (GCSC_MSR_ATAC_BASE + 0x10) 42 #define GCSC_ATAC_CH0D0_PIO (GCSC_MSR_ATAC_BASE + 0x20) 43 #define GCSC_ATAC_CH0D0_DMA (GCSC_MSR_ATAC_BASE + 0x21) 44 #define GCSC_ATAC_CH0D1_PIO (GCSC_MSR_ATAC_BASE + 0x22) 45 #define GCSC_ATAC_CH0D1_DMA (GCSC_MSR_ATAC_BASE + 0x23) 46 #define GCSC_ATAC_PCI_ABRTERR (GCSC_MSR_ATAC_BASE + 0x24) 47 #define GCSC_ATAC_BM0_CMD_PRIM 0x00 48 #define GCSC_ATAC_BM0_STS_PRIM 0x02 49 #define GCSC_ATAC_BM0_PRD 0x04 50 51 /* 52 * ATAC_CH0D0_DMA registers: 53 * 54 * PIO Format (bit 31): Format 1 allows independent control of command 55 * and data per drive, while Format 0 selects the slowest speed 56 * of the two drives. 57 */ 58 #define GCSC_ATAC_PIO_FORMAT (1U << 31) /* PIO Mode Format 1 */ 59 /* 60 * DMA_SEL (bit 20): sets Ultra DMA mode (if enabled) or Multi-word 61 * DMA mode (if disabled). 62 */ 63 #define GCSC_ATAC_DMA_SEL (1 << 20) 64 65 /* PIO Format 1 settings */ 66 static const uint32_t gcsc_pio_timings[] = { 67 0xf7f4f7f4, /* PIO Mode 0 */ 68 0x53f3f173, /* PIO Mode 1 */ 69 0x13f18141, /* PIO Mode 2 */ 70 0x51315131, /* PIO Mode 3 */ 71 0x11311131 /* PIO Mode 4 */ 72 }; 73 74 static const uint32_t gcsc_mdma_timings[] = { 75 0x7f0ffff3, /* MDMA Mode 0 */ 76 0x7f035352, /* MDMA Mode 1 */ 77 0x7f024241 /* MDMA Mode 2 */ 78 }; 79 80 static const uint32_t gcsc_udma_timings[] = { 81 0x7f7436a1, /* Ultra DMA Mode 0 */ 82 0x7f733481, /* Ultra DMA Mode 1 */ 83 0x7f723261, /* Ultra DMA Mode 2 */ 84 0x7f713161, /* Ultra DMA Mode 3 */ 85 0x7f703061 /* Ultra DMA Mode 4 */ 86 }; 87 88