1 /* $OpenBSD: rccosb4.c,v 1.6 2015/09/01 06:01:24 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 2004,2005 Michael Shalayeff 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Support for RCC South Bridge interrupt controller 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/malloc.h> 37 38 #include <machine/intr.h> 39 #include <machine/bus.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 44 #include <i386/pci/pcibiosvar.h> 45 #include <i386/pci/piixvar.h> 46 #include <i386/pci/rccosb4reg.h> 47 48 struct osb4_handle { 49 struct piix_handle piix; 50 51 #define osb4_iot piix.ph_iot 52 bus_space_handle_t osb4_ioh; 53 }; 54 55 int osb4_getclink(pciintr_icu_handle_t, int, int *); 56 int osb4_get_intr(pciintr_icu_handle_t, int, int *); 57 int osb4_set_intr(pciintr_icu_handle_t, int, int); 58 59 const struct pciintr_icu osb4_pci_icu = { 60 osb4_getclink, 61 osb4_get_intr, 62 osb4_set_intr, 63 piix_get_trigger, 64 piix_set_trigger, 65 }; 66 67 int 68 osb4_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag, 69 pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp) 70 { 71 struct osb4_handle *ph; 72 73 ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT); 74 if (ph == NULL) 75 return (1); 76 77 ph->piix.ph_iot = iot; 78 ph->piix.ph_pc = pc; 79 ph->piix.ph_tag = tag; 80 81 if (bus_space_map(iot, OSB4_PIAIR, 2, 0, &ph->osb4_ioh)) { 82 free(ph, M_DEVBUF, sizeof *ph); 83 return (1); 84 } 85 86 if (bus_space_map(iot, OSB4_REG_ELCR, 2, 0, &ph->piix.ph_elcr_ioh)) { 87 free(ph, M_DEVBUF, sizeof *ph); 88 return (1); 89 } 90 91 *ptagp = &osb4_pci_icu; 92 *phandp = ph; 93 return (0); 94 } 95 96 int 97 osb4_getclink(pciintr_icu_handle_t v, int link, int *clinkp) 98 { 99 if (OSB4_LEGAL_LINK(link - 1)) { 100 *clinkp = link; 101 if (link <= OSB4_PISP) 102 *clinkp |= PCI_INT_VIA_ISA; 103 return (0); 104 } 105 106 return (1); 107 } 108 109 int 110 osb4_get_intr(pciintr_icu_handle_t v, int clink, int *irqp) 111 { 112 struct osb4_handle *ph = v; 113 int link = clink & 0xff; 114 115 if (!OSB4_LEGAL_LINK(link)) 116 return (1); 117 118 bus_space_write_1(ph->osb4_iot, ph->osb4_ioh, 0, link); 119 *irqp = bus_space_read_1(ph->osb4_iot, ph->osb4_ioh, 1) & 0xf; 120 if (*irqp == 0) 121 *irqp = I386_PCI_INTERRUPT_LINE_NO_CONNECTION; 122 123 return (0); 124 } 125 126 int 127 osb4_set_intr(pciintr_icu_handle_t v, int clink, int irq) 128 { 129 struct osb4_handle *ph = v; 130 int link = clink & 0xff; 131 132 if (!OSB4_LEGAL_LINK(link) || !OSB4_LEGAL_IRQ(irq & 0xf)) 133 return (1); 134 135 bus_space_write_1(ph->osb4_iot, ph->osb4_ioh, 0, link); 136 bus_space_write_1(ph->osb4_iot, ph->osb4_ioh, 1, irq & 0xf); 137 138 return (0); 139 } 140