xref: /openbsd/sys/arch/i386/pci/sis85c503.c (revision 73471bf0)
1 /*	$OpenBSD: sis85c503.c,v 1.8 2008/06/26 05:42:11 ray Exp $	*/
2 /*	$NetBSD: sis85c503.c,v 1.2 2000/07/18 11:24:09 soda Exp $	*/
3 
4 /*-
5  * Copyright (c) 1999 The NetBSD Foundation, Inc.
6  * All rights reserved.
7  *
8  * This code is derived from software contributed to The NetBSD Foundation
9  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10  * NASA Ames Research Center.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 /*
35  * Copyright (c) 1999, by UCHIYAMA Yasushi
36  * All rights reserved.
37  *
38  * Redistribution and use in source and binary forms, with or without
39  * modification, are permitted provided that the following conditions
40  * are met:
41  * 1. Redistributions of source code must retain the above copyright
42  *    notice, this list of conditions and the following disclaimer.
43  * 2. The name of the developer may NOT be used to endorse or promote products
44  *    derived from this software without specific prior written permission.
45  *
46  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
47  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
48  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
49  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
50  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
51  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
52  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
53  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
54  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
55  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
56  * SUCH DAMAGE.
57  */
58 
59 /*
60  * Support for the SiS 85c503 PCI-ISA bridge interrupt controller.
61  */
62 
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/device.h>
66 
67 #include <machine/intr.h>
68 #include <machine/bus.h>
69 
70 #include <dev/pci/pcivar.h>
71 #include <dev/pci/pcireg.h>
72 #include <dev/pci/pcidevs.h>
73 
74 #include <i386/pci/pcibiosvar.h>
75 #include <i386/pci/sis85c503reg.h>
76 #include <i386/pci/piixvar.h>
77 
78 int	sis85c503_getclink(pciintr_icu_handle_t, int, int *);
79 int	sis85c503_get_intr(pciintr_icu_handle_t, int, int *);
80 int	sis85c503_set_intr(pciintr_icu_handle_t, int, int);
81 
82 const struct pciintr_icu sis85c503_pci_icu = {
83 	sis85c503_getclink,
84 	sis85c503_get_intr,
85 	sis85c503_set_intr,
86 	piix_get_trigger,
87 	piix_set_trigger,
88 };
89 
90 int
91 sis85c503_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag,
92     pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp)
93 {
94 
95 	if (piix_init(pc, iot, tag, ptagp, phandp) == 0) {
96 		*ptagp = &sis85c503_pci_icu;
97 		return (0);
98 	}
99 
100 	return (1);
101 }
102 
103 int
104 sis85c503_getclink(pciintr_icu_handle_t v, int link, int *clinkp)
105 {
106 
107 	/* Pattern 1: simple. */
108 	if (link >= 1 && link <= 4) {
109 		*clinkp = SIS85C503_CFG_PIRQ_REGSTART + link - 1;
110 		return (0);
111 	}
112 
113 	/* Pattern 2: configuration register offset */
114 	if (link >= SIS85C503_CFG_PIRQ_REGSTART &&
115 	    link <= SIS85C503_CFG_PIRQ_REGEND) {
116 		*clinkp = link;
117 		return (0);
118 	}
119 
120 	return (1);
121 }
122 
123 int
124 sis85c503_get_intr(pciintr_icu_handle_t v, int clink, int *irqp)
125 {
126 	struct piix_handle *ph = v;
127 	pcireg_t reg;
128 
129 	if (SIS85C503_LEGAL_LINK(clink) == 0)
130 		return (1);
131 
132 	reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
133 	    SIS85C503_CFG_PIRQ_REGOFS(clink));
134 	reg = SIS85C503_CFG_PIRQ_REG(reg, clink);
135 
136 	if (reg & SIS85C503_CFG_PIRQ_ROUTE_DISABLE)
137 		*irqp = 0xff;
138 	else
139 		*irqp = reg & SIS85C503_CFG_PIRQ_INTR_MASK;
140 
141 	return (0);
142 }
143 
144 int
145 sis85c503_set_intr(pciintr_icu_handle_t v, int clink, int irq)
146 {
147 	struct piix_handle *ph = v;
148 	int shift;
149 	pcireg_t reg;
150 
151 	if (SIS85C503_LEGAL_LINK(clink) == 0 || SIS85C503_LEGAL_IRQ(irq) == 0)
152 		return (1);
153 
154 	reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
155 	    SIS85C503_CFG_PIRQ_REGOFS(clink));
156 	shift = SIS85C503_CFG_PIRQ_SHIFT(clink);
157 	reg &= ~((SIS85C503_CFG_PIRQ_ROUTE_DISABLE |
158 	    SIS85C503_CFG_PIRQ_INTR_MASK) << shift);
159 	reg |= (irq << shift);
160 	pci_conf_write(ph->ph_pc, ph->ph_tag, SIS85C503_CFG_PIRQ_REGOFS(clink),
161 	    reg);
162 
163 	return (0);
164 }
165