1 /* $OpenBSD: bonito.c,v 1.34 2018/02/24 11:42:30 visa Exp $ */ 2 /* $NetBSD: bonito_mainbus.c,v 1.11 2008/04/28 20:23:10 martin Exp $ */ 3 /* $NetBSD: bonito_pci.c,v 1.5 2008/04/28 20:23:28 martin Exp $ */ 4 5 /* 6 * Copyright (c) 2009, 2010 Miodrag Vallat. 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 /*- 21 * Copyright (c) 2001 The NetBSD Foundation, Inc. 22 * All rights reserved. 23 * 24 * This code is derived from software contributed to The NetBSD Foundation 25 * by Jason R. Thorpe. 26 * 27 * Redistribution and use in source and binary forms, with or without 28 * modification, are permitted provided that the following conditions 29 * are met: 30 * 1. Redistributions of source code must retain the above copyright 31 * notice, this list of conditions and the following disclaimer. 32 * 2. Redistributions in binary form must reproduce the above copyright 33 * notice, this list of conditions and the following disclaimer in the 34 * documentation and/or other materials provided with the distribution. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 37 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 38 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 39 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 40 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 41 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 42 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 43 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 44 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 45 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 46 * POSSIBILITY OF SUCH DAMAGE. 47 */ 48 49 /* 50 * PCI configuration space support for the Loongson PCI and memory controller 51 * chip, which is derived from the Algorithmics BONITO chip. 52 */ 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/device.h> 57 #include <sys/extent.h> 58 #include <sys/malloc.h> 59 60 #include <machine/autoconf.h> 61 #include <machine/bus.h> 62 #include <machine/cpu.h> 63 #include <mips64/mips_cpu.h> 64 #include <machine/intr.h> 65 66 #include <dev/pci/pcidevs.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/ppbreg.h> 70 71 #include <loongson/dev/bonitoreg.h> 72 #include <loongson/dev/bonitovar.h> 73 #include <loongson/dev/bonito_irq.h> 74 75 #include <uvm/uvm_extern.h> 76 77 #if 0 78 #define BONITO_DEBUG 79 #endif 80 81 int bonito_match(struct device *, void *, void *); 82 void bonito_attach(struct device *, struct device *, void *); 83 84 const struct cfattach bonito_ca = { 85 sizeof(struct bonito_softc), bonito_match, bonito_attach 86 }; 87 88 struct cfdriver bonito_cd = { 89 NULL, "bonito", DV_DULL 90 }; 91 92 #define wbflush() mips_sync() 93 94 bus_addr_t bonito_pa_to_device(paddr_t); 95 paddr_t bonito_device_to_pa(bus_addr_t); 96 97 void bonito_intr_makemasks(void); 98 uint32_t bonito_intr_2e(uint32_t, struct trapframe *); 99 uint32_t bonito_intr_2f(uint32_t, struct trapframe *); 100 void bonito_intr_dispatch(uint64_t, int, struct trapframe *); 101 102 void bonito_attach_hook(struct device *, struct device *, 103 struct pcibus_attach_args *); 104 int bonito_bus_maxdevs(void *, int); 105 pcitag_t bonito_make_tag(void *, int, int, int); 106 void bonito_decompose_tag(void *, pcitag_t, int *, int *, int *); 107 int bonito_conf_size(void *, pcitag_t); 108 pcireg_t bonito_conf_read(void *, pcitag_t, int); 109 pcireg_t bonito_conf_read_internal(const struct bonito_config *, pcitag_t, int); 110 void bonito_conf_write(void *, pcitag_t, int, pcireg_t); 111 int bonito_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 112 const char * 113 bonito_pci_intr_string(void *, pci_intr_handle_t); 114 void *bonito_pci_intr_establish(void *, pci_intr_handle_t, int, 115 int (*)(void *), void *, char *); 116 void bonito_pci_intr_disestablish(void *, void *); 117 118 int bonito_conf_addr(const struct bonito_config *, pcitag_t, int, 119 u_int32_t *, u_int32_t *); 120 121 void bonito_splx(int); 122 123 /* 124 * Bonito interrupt handling declarations. 125 * See <loongson/dev/bonito_irq.h> for details. 126 */ 127 struct intrhand *bonito_intrhand[BONITO_NINTS]; 128 uint64_t bonito_intem; 129 uint64_t bonito_imask[NIPLS]; 130 131 struct machine_bus_dma_tag bonito_bus_dma_tag = { 132 ._dmamap_create = _dmamap_create, 133 ._dmamap_destroy = _dmamap_destroy, 134 ._dmamap_load = _dmamap_load, 135 ._dmamap_load_mbuf = _dmamap_load_mbuf, 136 ._dmamap_load_uio = _dmamap_load_uio, 137 ._dmamap_load_raw = _dmamap_load_raw, 138 ._dmamap_load_buffer = _dmamap_load_buffer, 139 ._dmamap_unload = _dmamap_unload, 140 ._dmamap_sync = _dmamap_sync, 141 142 ._dmamem_alloc = _dmamem_alloc, 143 ._dmamem_free = _dmamem_free, 144 ._dmamem_map = _dmamem_map, 145 ._dmamem_unmap = _dmamem_unmap, 146 ._dmamem_mmap = _dmamem_mmap, 147 148 ._pa_to_device = bonito_pa_to_device, 149 ._device_to_pa = bonito_device_to_pa 150 }; 151 152 int bonito_io_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 153 bus_space_handle_t *); 154 int bonito_mem_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 155 bus_space_handle_t *); 156 157 struct mips_bus_space bonito_pci_io_space_tag = { 158 .bus_base = PHYS_TO_XKPHYS(BONITO_PCIIO_BASE, CCA_NC), 159 ._space_read_1 = generic_space_read_1, 160 ._space_write_1 = generic_space_write_1, 161 ._space_read_2 = generic_space_read_2, 162 ._space_write_2 = generic_space_write_2, 163 ._space_read_4 = generic_space_read_4, 164 ._space_write_4 = generic_space_write_4, 165 ._space_read_8 = generic_space_read_8, 166 ._space_write_8 = generic_space_write_8, 167 ._space_read_raw_2 = generic_space_read_raw_2, 168 ._space_write_raw_2 = generic_space_write_raw_2, 169 ._space_read_raw_4 = generic_space_read_raw_4, 170 ._space_write_raw_4 = generic_space_write_raw_4, 171 ._space_read_raw_8 = generic_space_read_raw_8, 172 ._space_write_raw_8 = generic_space_write_raw_8, 173 ._space_map = bonito_io_map, 174 ._space_unmap = generic_space_unmap, 175 ._space_subregion = generic_space_region, 176 ._space_vaddr = generic_space_vaddr, 177 ._space_mmap = generic_space_mmap 178 }; 179 180 struct mips_bus_space bonito_pci_mem_space_tag = { 181 .bus_base = PHYS_TO_XKPHYS(0, CCA_NC), 182 ._space_read_1 = generic_space_read_1, 183 ._space_write_1 = generic_space_write_1, 184 ._space_read_2 = generic_space_read_2, 185 ._space_write_2 = generic_space_write_2, 186 ._space_read_4 = generic_space_read_4, 187 ._space_write_4 = generic_space_write_4, 188 ._space_read_8 = generic_space_read_8, 189 ._space_write_8 = generic_space_write_8, 190 ._space_read_raw_2 = generic_space_read_raw_2, 191 ._space_write_raw_2 = generic_space_write_raw_2, 192 ._space_read_raw_4 = generic_space_read_raw_4, 193 ._space_write_raw_4 = generic_space_write_raw_4, 194 ._space_read_raw_8 = generic_space_read_raw_8, 195 ._space_write_raw_8 = generic_space_write_raw_8, 196 ._space_map = bonito_mem_map, 197 ._space_unmap = generic_space_unmap, 198 ._space_subregion = generic_space_region, 199 ._space_vaddr = generic_space_vaddr, 200 ._space_mmap = generic_space_mmap 201 }; 202 203 int 204 bonito_match(struct device *parent, void *vcf, void *aux) 205 { 206 struct mainbus_attach_args *maa = aux; 207 208 if (loongson_ver >= 0x3a) 209 return (0); 210 211 if (strcmp(maa->maa_name, bonito_cd.cd_name) == 0) 212 return (1); 213 214 return (0); 215 } 216 217 void 218 bonito_attach(struct device *parent, struct device *self, void *aux) 219 { 220 struct bonito_softc *sc = (struct bonito_softc *)self; 221 struct pcibus_attach_args pba; 222 pci_chipset_tag_t pc = &sc->sc_pc; 223 const struct bonito_config *bc; 224 uint32_t reg; 225 226 /* 227 * Loongson 2F processors do not use a real Bonito64 chip but 228 * their own derivative, which is no longer 100% compatible. 229 * We need to make sure we never try to access an unimplemented 230 * register... 231 */ 232 if (loongson_ver >= 0x2f) 233 sc->sc_compatible = 0; 234 else 235 sc->sc_compatible = 1; 236 237 reg = PCI_REVISION(REGVAL(BONITO_PCI_REG(PCI_CLASS_REG))); 238 if (sc->sc_compatible) { 239 printf(": BONITO Memory and PCI controller, %s rev %d.%d\n", 240 BONITO_REV_FPGA(reg) ? "FPGA" : "ASIC", 241 BONITO_REV_MAJOR(reg), BONITO_REV_MINOR(reg)); 242 } else { 243 printf(": memory and PCI-X controller, rev %d\n", 244 PCI_REVISION(REGVAL(BONITO_PCI_REG(PCI_CLASS_REG)))); 245 } 246 247 bc = sys_platform->bonito_config; 248 sc->sc_bonito = bc; 249 SLIST_INIT(&sc->sc_hook); 250 251 #ifdef BONITO_DEBUG 252 if (!sc->sc_compatible) 253 printf("ISR4C: %08x\n", REGVAL(BONITO_PCI_REG(0x4c))); 254 printf("PCIMAP: %08x\n", REGVAL(BONITO_PCIMAP)); 255 printf("MEMWIN: %08x.%08x - %08x.%08x\n", 256 REGVAL(BONITO_MEM_WIN_BASE_H), REGVAL(BONITO_MEM_WIN_BASE_L), 257 REGVAL(BONITO_MEM_WIN_MASK_H), REGVAL(BONITO_MEM_WIN_MASK_L)); 258 if (!sc->sc_compatible) { 259 printf("HITSEL0: %08x.%08x\n", 260 REGVAL(LOONGSON_PCI_HIT0_SEL_H), 261 REGVAL(LOONGSON_PCI_HIT0_SEL_L)); 262 printf("HITSEL1: %08x.%08x\n", 263 REGVAL(LOONGSON_PCI_HIT1_SEL_H), 264 REGVAL(LOONGSON_PCI_HIT1_SEL_L)); 265 printf("HITSEL2: %08x.%08x\n", 266 REGVAL(LOONGSON_PCI_HIT2_SEL_H), 267 REGVAL(LOONGSON_PCI_HIT2_SEL_L)); 268 } 269 printf("PCI BAR 0:%08x 1:%08x 2:%08x 3:%08x 4:%08x 5:%08x\n", 270 REGVAL(BONITO_PCI_REG(PCI_MAPREG_START + 0 * 4)), 271 REGVAL(BONITO_PCI_REG(PCI_MAPREG_START + 1 * 4)), 272 REGVAL(BONITO_PCI_REG(PCI_MAPREG_START + 2 * 4)), 273 REGVAL(BONITO_PCI_REG(PCI_MAPREG_START + 3 * 4)), 274 REGVAL(BONITO_PCI_REG(PCI_MAPREG_START + 4 * 4)), 275 REGVAL(BONITO_PCI_REG(PCI_MAPREG_START + 5 * 4))); 276 #endif 277 278 /* 279 * Setup proper abitration. 280 */ 281 282 if (!sc->sc_compatible) { 283 /* 284 * According to Linux, changing the value of this register 285 * ``avoids deadlock of PCI reading/writing lock operation''. 286 * 287 * Unfortunately, documentation for the Implementation 288 * Specific Registers (ISR40 to ISR5C) is only found in the 289 * chinese version of the Loongson 2F documentation. 290 * 291 * The particular bit we set here is ``mas_read_defer''. 292 */ 293 /* c2000001 -> d2000001 */ 294 REGVAL(BONITO_PCI_REG(0x4c)) |= 0x10000000; 295 296 /* all pci devices may need to hold the bus */ 297 reg = REGVAL(LOONGSON_PXARB_CFG); 298 reg &= ~LOONGSON_PXARB_RUDE_DEV_MSK; 299 reg |= 0xfe << LOONGSON_PXARB_RUDE_DEV_SHFT; 300 REGVAL(LOONGSON_PXARB_CFG) = reg; 301 (void)REGVAL(LOONGSON_PXARB_CFG); 302 } 303 304 /* 305 * Setup interrupt handling. 306 */ 307 308 REGVAL(BONITO_GPIOIE) = bc->bc_gpioIE; 309 REGVAL(BONITO_INTEDGE) = bc->bc_intEdge; 310 if (sc->sc_compatible) 311 REGVAL(BONITO_INTSTEER) = bc->bc_intSteer; 312 REGVAL(BONITO_INTPOL) = bc->bc_intPol; 313 314 REGVAL(BONITO_INTENCLR) = 0xffffffff; 315 (void)REGVAL(BONITO_INTENCLR); 316 317 if (sc->sc_compatible) { 318 bonito_intem |= BONITO_INTRMASK_MASTERERR; 319 } 320 321 if (loongson_ver >= 0x2f) 322 set_intr(INTPRI_BONITO, CR_INT_4, bonito_intr_2f); 323 else 324 set_intr(INTPRI_BONITO, CR_INT_0, bonito_intr_2e); 325 register_splx_handler(bonito_splx); 326 327 /* 328 * Attach PCI bus. 329 */ 330 331 pc->pc_conf_v = sc; 332 pc->pc_attach_hook = bonito_attach_hook; 333 pc->pc_bus_maxdevs = bonito_bus_maxdevs; 334 pc->pc_make_tag = bonito_make_tag; 335 pc->pc_decompose_tag = bonito_decompose_tag; 336 pc->pc_conf_size = bonito_conf_size; 337 pc->pc_conf_read = bonito_conf_read; 338 pc->pc_conf_write = bonito_conf_write; 339 340 pc->pc_intr_v = sc; 341 pc->pc_intr_map = bonito_pci_intr_map; 342 pc->pc_intr_string = bonito_pci_intr_string; 343 pc->pc_intr_establish = bonito_pci_intr_establish; 344 pc->pc_intr_disestablish = bonito_pci_intr_disestablish; 345 346 bzero(&pba, sizeof pba); 347 pba.pba_busname = "pci"; 348 pba.pba_iot = &bonito_pci_io_space_tag; 349 pba.pba_memt = &bonito_pci_mem_space_tag; 350 pba.pba_dmat = &bonito_bus_dma_tag; 351 pba.pba_pc = pc; 352 pba.pba_domain = pci_ndomains++; 353 pba.pba_bus = 0; 354 #ifdef notyet 355 pba.pba_ioex = bonito_get_resource_extent(pc, 1); 356 pba.pba_memex = bonito_get_resource_extent(pc, 0); 357 #endif 358 359 config_found(&sc->sc_dev, &pba, bonito_print); 360 } 361 362 bus_addr_t 363 bonito_pa_to_device(paddr_t pa) 364 { 365 return pa ^ loongson_dma_base; 366 } 367 368 paddr_t 369 bonito_device_to_pa(bus_addr_t addr) 370 { 371 return addr ^ loongson_dma_base; 372 } 373 374 int 375 bonito_print(void *aux, const char *pnp) 376 { 377 struct pcibus_attach_args *pba = aux; 378 379 if (pnp) 380 printf("%s at %s", pba->pba_busname, pnp); 381 printf(" bus %d", pba->pba_bus); 382 383 return UNCONF; 384 } 385 386 /* 387 * Bonito interrupt handling 388 */ 389 390 void * 391 bonito_intr_establish(int irq, int type, int level, int (*handler)(void *), 392 void *arg, const char *name) 393 { 394 struct intrhand **p, *q, *ih; 395 int s; 396 397 #ifdef DIAGNOSTIC 398 if (irq >= BONITO_NINTS || irq == BONITO_ISA_IRQ(2) || irq < 0) 399 panic("bonito_intr_establish: illegal irq %d", irq); 400 #endif 401 402 level &= ~IPL_MPSAFE; 403 404 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 405 if (ih == NULL) 406 return NULL; 407 408 ih->ih_next = NULL; 409 ih->ih_fun = handler; 410 ih->ih_arg = arg; 411 ih->ih_level = level; 412 ih->ih_irq = irq; 413 evcount_attach(&ih->ih_count, name, &ih->ih_irq); 414 415 s = splhigh(); 416 417 /* 418 * Figure out where to put the handler. 419 * This is O(N^2), but we want to preserve the order, and N is 420 * generally small. 421 */ 422 for (p = &bonito_intrhand[irq]; (q = *p) != NULL; p = &q->ih_next) 423 ; 424 *p = ih; 425 426 bonito_intem |= 1UL << irq; 427 bonito_intr_makemasks(); 428 429 splx(s); /* causes hw mask update */ 430 431 return (ih); 432 } 433 434 void 435 bonito_intr_disestablish(void *vih) 436 { 437 struct intrhand *ih = (struct intrhand *)vih; 438 struct intrhand **p, *q; 439 int irq = ih->ih_irq; 440 int s; 441 442 #ifdef DIAGNOSTIC 443 if (irq >= BONITO_NINTS || irq == BONITO_ISA_IRQ(2) || irq < 0) 444 panic("bonito_intr_disestablish: illegal irq %d", irq); 445 #endif 446 447 s = splhigh(); 448 449 evcount_detach(&ih->ih_count); 450 451 for (p = &bonito_intrhand[irq]; (q = *p) != NULL; p = &q->ih_next) 452 if (q == ih) 453 break; 454 #ifdef DIAGNOSTIC 455 if (q == NULL) 456 panic("bonito_intr_disestablish: never registered"); 457 #endif 458 *p = ih->ih_next; 459 460 if (ih->ih_next == NULL && p == &bonito_intrhand[irq]) { 461 bonito_intem &= ~(1UL << irq); 462 bonito_intr_makemasks(); 463 /* 464 * No need to clear a bit in INTEN through INTCLR, 465 * splhigh() took care of disabling everything and 466 * splx() will not reenable this source after the 467 * mask update. 468 */ 469 } 470 471 splx(s); 472 473 free(ih, M_DEVBUF, sizeof *ih); 474 } 475 476 /* 477 * Update interrupt masks. This is for designs without legacy PIC. 478 */ 479 480 void 481 bonito_splx(int newipl) 482 { 483 struct cpu_info *ci = curcpu(); 484 485 /* Update masks to new ipl. Order highly important! */ 486 ci->ci_ipl = newipl; 487 bonito_setintrmask(newipl); 488 /* If we still have softints pending trigger processing. */ 489 if (ci->ci_softpending != 0 && newipl < IPL_SOFTINT) 490 setsoftintr0(); 491 } 492 493 void 494 bonito_setintrmask(int level) 495 { 496 uint64_t active; 497 uint32_t clear, set; 498 register_t sr; 499 500 active = bonito_intem & ~bonito_imask[level]; 501 /* be sure to mask high bits, there may be other interrupt sources */ 502 clear = BONITO_DIRECT_MASK(bonito_imask[level]); 503 set = BONITO_DIRECT_MASK(active); 504 505 sr = disableintr(); 506 507 if (clear != 0) { 508 REGVAL(BONITO_INTENCLR) = clear; 509 (void)REGVAL(BONITO_INTENCLR); 510 } 511 if (set != 0) { 512 REGVAL(BONITO_INTENSET) = set; 513 (void)REGVAL(BONITO_INTENSET); 514 } 515 516 setsr(sr); 517 } 518 519 /* 520 * Recompute interrupt masks. 521 */ 522 void 523 bonito_intr_makemasks() 524 { 525 int irq, level; 526 struct intrhand *q; 527 uint intrlevel[BONITO_NINTS]; 528 529 /* First, figure out which levels each IRQ uses. */ 530 for (irq = 0; irq < BONITO_NINTS; irq++) { 531 uint levels = 0; 532 for (q = bonito_intrhand[irq]; q != NULL; q = q->ih_next) 533 levels |= 1 << q->ih_level; 534 intrlevel[irq] = levels; 535 } 536 537 /* 538 * Then figure out which IRQs use each level. 539 * Note that we make sure never to overwrite imask[IPL_HIGH], in 540 * case an interrupt occurs during intr_disestablish() and causes 541 * an unfortunate splx() while we are here recomputing the masks. 542 */ 543 for (level = IPL_NONE; level < IPL_HIGH; level++) { 544 uint64_t irqs = 0; 545 for (irq = 0; irq < BONITO_NINTS; irq++) 546 if (intrlevel[irq] & (1 << level)) 547 irqs |= 1UL << irq; 548 bonito_imask[level] = irqs; 549 } 550 551 /* 552 * There are tty, network and disk drivers that use free() at interrupt 553 * time, so vm > (tty | net | bio). 554 * 555 * Enforce a hierarchy that gives slow devices a better chance at not 556 * dropping data. 557 */ 558 bonito_imask[IPL_NET] |= bonito_imask[IPL_BIO]; 559 bonito_imask[IPL_TTY] |= bonito_imask[IPL_NET]; 560 bonito_imask[IPL_VM] |= bonito_imask[IPL_TTY]; 561 bonito_imask[IPL_CLOCK] |= bonito_imask[IPL_VM]; 562 563 /* 564 * These are pseudo-levels. 565 */ 566 bonito_imask[IPL_NONE] = 0; 567 bonito_imask[IPL_HIGH] = -1UL; 568 } 569 570 /* 571 * Process native interrupts 572 */ 573 574 uint32_t 575 bonito_intr_2e(uint32_t hwpend, struct trapframe *frame) 576 { 577 uint64_t imr, isr, mask; 578 579 isr = REGVAL(BONITO_INTISR); 580 581 /* 582 * According to Linux code, Bonito64 - at least on Loongson 583 * systems - triggers an interrupt during DMA, which is to be 584 * ignored. Smells like a chip errata to me. 585 */ 586 while (ISSET(isr, BONITO_INTRMASK_MASTERERR)) { 587 delay(1); 588 isr = REGVAL(BONITO_INTISR); 589 } 590 591 isr &= BONITO_INTRMASK_GPIN; 592 imr = REGVAL(BONITO_INTEN); 593 isr &= imr; 594 #ifdef DEBUG 595 printf("pci interrupt: imr %04x isr %04x\n", imr, isr); 596 #endif 597 if (isr == 0) 598 return 0; /* not for us */ 599 600 /* 601 * Mask all pending interrupts. 602 */ 603 REGVAL(BONITO_INTENCLR) = isr; 604 (void)REGVAL(BONITO_INTENCLR); 605 606 /* 607 * If interrupts are spl-masked, mask them and wait for splx() 608 * to reenable them when necessary. 609 */ 610 if ((mask = isr & bonito_imask[frame->ipl]) != 0) { 611 isr &= ~mask; 612 imr &= ~mask; 613 } 614 615 /* 616 * Now process allowed interrupts. 617 */ 618 if (isr != 0) { 619 bonito_intr_dispatch(isr, 30, frame); 620 621 /* 622 * Reenable interrupts which have been serviced. 623 */ 624 REGVAL(BONITO_INTENSET) = imr; 625 (void)REGVAL(BONITO_INTENSET); 626 } 627 628 return hwpend; 629 } 630 631 uint32_t 632 bonito_intr_2f(uint32_t hwpend, struct trapframe *frame) 633 { 634 uint64_t imr, isr, mask; 635 636 isr = REGVAL(BONITO_INTISR) & LOONGSON_INTRMASK_LVL4; 637 imr = REGVAL(BONITO_INTEN); 638 isr &= imr; 639 #ifdef DEBUG 640 printf("pci interrupt: imr %04x isr %04x\n", imr, isr); 641 #endif 642 if (isr == 0) 643 return 0; /* not for us */ 644 645 /* 646 * Mask all pending interrupts. 647 */ 648 REGVAL(BONITO_INTENCLR) = isr; 649 (void)REGVAL(BONITO_INTENCLR); 650 651 /* 652 * If interrupts are spl-masked, mask them and wait for splx() 653 * to reenable them when necessary. 654 */ 655 if ((mask = isr & bonito_imask[frame->ipl]) != 0) { 656 isr &= ~mask; 657 imr &= ~mask; 658 } 659 660 /* 661 * Now process allowed interrupts. 662 */ 663 if (isr != 0) { 664 bonito_intr_dispatch(isr, 665 LOONGSON_INTR_DRAM_PARERR /* skip non-pci interrupts */, 666 frame); 667 668 /* 669 * Reenable interrupts which have been serviced. 670 */ 671 REGVAL(BONITO_INTENSET) = imr; 672 (void)REGVAL(BONITO_INTENSET); 673 } 674 675 return hwpend; 676 } 677 678 void 679 bonito_intr_dispatch(uint64_t isr, int startbit, struct trapframe *frame) 680 { 681 int lvl, bitno; 682 uint64_t tmpisr, mask; 683 struct intrhand *ih; 684 int rc; 685 686 /* Service higher level interrupts first */ 687 for (lvl = IPL_HIGH - 1; lvl != IPL_NONE; lvl--) { 688 tmpisr = isr & (bonito_imask[lvl] ^ bonito_imask[lvl - 1]); 689 if (tmpisr == 0) 690 continue; 691 for (bitno = startbit, mask = 1UL << bitno; mask != 0; 692 bitno--, mask >>= 1) { 693 if ((tmpisr & mask) == 0) 694 continue; 695 696 rc = 0; 697 for (ih = bonito_intrhand[bitno]; ih != NULL; 698 ih = ih->ih_next) { 699 splraise(ih->ih_level); 700 if ((*ih->ih_fun)(ih->ih_arg) != 0) { 701 rc = 1; 702 ih->ih_count.ec_count++; 703 } 704 curcpu()->ci_ipl = frame->ipl; 705 } 706 if (rc == 0) { 707 printf("spurious interrupt %d\n", bitno); 708 #ifdef DEBUG 709 printf("ISR %08x IMR %08x ipl %d mask %08x\n", 710 REGVAL(BONITO_INTISR), REGVAL(BONITO_INTEN), 711 frame->ipl, bonito_imask[frame->ipl]); 712 #ifdef DDB 713 db_enter(); 714 #endif 715 #endif 716 } 717 718 if ((isr ^= mask) == 0) 719 return; 720 if ((tmpisr ^= mask) == 0) 721 break; 722 } 723 } 724 } 725 726 /* 727 * various PCI helpers 728 */ 729 730 void 731 bonito_attach_hook(struct device *parent, struct device *self, 732 struct pcibus_attach_args *pba) 733 { 734 pci_chipset_tag_t pc = pba->pba_pc; 735 struct bonito_softc *sc = pc->pc_conf_v; 736 const struct bonito_config *bc = sc->sc_bonito; 737 738 if (pba->pba_bus != 0) 739 return; 740 741 (*bc->bc_attach_hook)(pc); 742 } 743 744 /* 745 * PCI configuration space access routines 746 */ 747 748 int 749 bonito_bus_maxdevs(void *v, int busno) 750 { 751 struct bonito_softc *sc = v; 752 const struct bonito_config *bc = sc->sc_bonito; 753 754 return busno == 0 ? 32 - bc->bc_adbase : 32; 755 } 756 757 pcitag_t 758 bonito_make_tag(void *unused, int b, int d, int f) 759 { 760 return (b << 16) | (d << 11) | (f << 8); 761 } 762 763 void 764 bonito_decompose_tag(void *unused, pcitag_t tag, int *bp, int *dp, int *fp) 765 { 766 if (bp != NULL) 767 *bp = (tag >> 16) & 0xff; 768 if (dp != NULL) 769 *dp = (tag >> 11) & 0x1f; 770 if (fp != NULL) 771 *fp = (tag >> 8) & 0x7; 772 } 773 774 int 775 bonito_conf_addr(const struct bonito_config *bc, pcitag_t tag, int offset, 776 u_int32_t *cfgoff, u_int32_t *pcimap_cfg) 777 { 778 int b, d, f; 779 780 bonito_decompose_tag(NULL, tag, &b, &d, &f); 781 782 if (b == 0) { 783 d += bc->bc_adbase; 784 if (d > 31) 785 return 1; 786 *cfgoff = (1 << d) | (f << 8) | offset; 787 *pcimap_cfg = 0; 788 } else { 789 *cfgoff = tag | offset; 790 *pcimap_cfg = BONITO_PCIMAPCFG_TYPE1; 791 } 792 793 return 0; 794 } 795 796 /* PCI Configuration Space access hook structure */ 797 struct bonito_cfg_hook { 798 SLIST_ENTRY(bonito_cfg_hook) next; 799 int (*read)(void *, pci_chipset_tag_t, pcitag_t, int, pcireg_t *); 800 int (*write)(void *, pci_chipset_tag_t, pcitag_t, int, pcireg_t); 801 void *cookie; 802 }; 803 804 int 805 bonito_pci_hook(pci_chipset_tag_t pc, void *cookie, 806 int (*r)(void *, pci_chipset_tag_t, pcitag_t, int, pcireg_t *), 807 int (*w)(void *, pci_chipset_tag_t, pcitag_t, int, pcireg_t)) 808 { 809 struct bonito_softc *sc = pc->pc_conf_v; 810 struct bonito_cfg_hook *bch; 811 812 bch = malloc(sizeof *bch, M_DEVBUF, M_NOWAIT); 813 if (bch == NULL) 814 return ENOMEM; 815 816 bch->read = r; 817 bch->write = w; 818 bch->cookie = cookie; 819 SLIST_INSERT_HEAD(&sc->sc_hook, bch, next); 820 return 0; 821 } 822 823 int 824 bonito_conf_size(void *v, pcitag_t tag) 825 { 826 return PCI_CONFIG_SPACE_SIZE; 827 } 828 829 pcireg_t 830 bonito_conf_read(void *v, pcitag_t tag, int offset) 831 { 832 struct bonito_softc *sc = v; 833 struct bonito_cfg_hook *hook; 834 pcireg_t data; 835 836 SLIST_FOREACH(hook, &sc->sc_hook, next) { 837 if (hook->read != NULL && 838 (*hook->read)(hook->cookie, &sc->sc_pc, tag, offset, 839 &data) != 0) 840 return data; 841 } 842 843 return bonito_conf_read_internal(sc->sc_bonito, tag, offset); 844 } 845 846 pcireg_t 847 bonito_conf_read_internal(const struct bonito_config *bc, pcitag_t tag, 848 int offset) 849 { 850 pcireg_t data; 851 u_int32_t cfgoff, pcimap_cfg; 852 register_t sr; 853 uint64_t imr; 854 855 if (bonito_conf_addr(bc, tag, offset, &cfgoff, &pcimap_cfg)) 856 return (pcireg_t)-1; 857 858 sr = disableintr(); 859 imr = REGVAL(BONITO_INTEN); 860 REGVAL(BONITO_INTENCLR) = 0xffffffff; 861 (void)REGVAL(BONITO_INTENCLR); 862 863 /* clear aborts */ 864 REGVAL(BONITO_PCI_REG(PCI_COMMAND_STATUS_REG)) |= 865 PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT; 866 867 /* high 16 bits of address go into PciMapCfg register */ 868 REGVAL(BONITO_PCIMAP_CFG) = (cfgoff >> 16) | pcimap_cfg; 869 (void)REGVAL(BONITO_PCIMAP_CFG); 870 wbflush(); 871 872 /* low 16 bits of address are offset into config space */ 873 data = REGVAL(BONITO_PCICFG_BASE + (cfgoff & 0xfffc)); 874 875 /* check for error */ 876 if (REGVAL(BONITO_PCI_REG(PCI_COMMAND_STATUS_REG)) & 877 (PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT)) { 878 REGVAL(BONITO_PCI_REG(PCI_COMMAND_STATUS_REG)) |= 879 PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT; 880 data = (pcireg_t) -1; 881 } 882 883 REGVAL(BONITO_INTENSET) = imr; 884 (void)REGVAL(BONITO_INTENSET); 885 setsr(sr); 886 887 return data; 888 } 889 890 void 891 bonito_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data) 892 { 893 struct bonito_softc *sc = v; 894 u_int32_t cfgoff, pcimap_cfg; 895 struct bonito_cfg_hook *hook; 896 register_t sr; 897 uint64_t imr; 898 899 SLIST_FOREACH(hook, &sc->sc_hook, next) { 900 if (hook->write != NULL && 901 (*hook->write)(hook->cookie, &sc->sc_pc, tag, offset, 902 data) != 0) 903 return; 904 } 905 906 if (bonito_conf_addr(sc->sc_bonito, tag, offset, &cfgoff, &pcimap_cfg)) 907 panic("bonito_conf_write"); 908 909 sr = disableintr(); 910 imr = REGVAL(BONITO_INTEN); 911 REGVAL(BONITO_INTENCLR) = 0xffffffff; 912 (void)REGVAL(BONITO_INTENCLR); 913 914 /* clear aborts */ 915 REGVAL(BONITO_PCI_REG(PCI_COMMAND_STATUS_REG)) |= 916 PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT; 917 918 /* high 16 bits of address go into PciMapCfg register */ 919 REGVAL(BONITO_PCIMAP_CFG) = (cfgoff >> 16) | pcimap_cfg; 920 (void)REGVAL(BONITO_PCIMAP_CFG); 921 wbflush(); 922 923 /* low 16 bits of address are offset into config space */ 924 REGVAL(BONITO_PCICFG_BASE + (cfgoff & 0xfffc)) = data; 925 926 REGVAL(BONITO_INTENSET) = imr; 927 (void)REGVAL(BONITO_INTENSET); 928 setsr(sr); 929 } 930 931 /* 932 * PCI Interrupt handling 933 */ 934 935 int 936 bonito_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 937 { 938 struct bonito_softc *sc = pa->pa_pc->pc_intr_v; 939 const struct bonito_config *bc = sc->sc_bonito; 940 int bus, dev, fn, pin; 941 942 *ihp = (pci_intr_handle_t)-1; 943 944 if (pa->pa_intrpin == 0) /* no interrupt needed */ 945 return 1; 946 947 #ifdef DIAGNOSTIC 948 if (pa->pa_intrpin > 4) { 949 printf("%s: bad interrupt pin %d\n", __func__, pa->pa_intrpin); 950 return 1; 951 } 952 #endif 953 954 pci_decompose_tag(pa->pa_pc, pa->pa_tag, &bus, &dev, &fn); 955 if (pa->pa_bridgetag) { 956 pin = PPB_INTERRUPT_SWIZZLE(pa->pa_rawintrpin, dev); 957 *ihp = pa->pa_bridgeih[pin - 1]; 958 } else { 959 if (bus == 0) 960 *ihp = (*bc->bc_intr_map)(dev, fn, pa->pa_intrpin); 961 962 if (*ihp == (pci_intr_handle_t)-1) 963 return 1; 964 } 965 966 return 0; 967 } 968 969 const char * 970 bonito_pci_intr_string(void *cookie, pci_intr_handle_t ih) 971 { 972 static char irqstr[1 + 12]; 973 974 if (BONITO_IRQ_IS_ISA(ih)) 975 snprintf(irqstr, sizeof irqstr, "isa irq %lu", 976 BONITO_IRQ_TO_ISA(ih)); 977 else 978 snprintf(irqstr, sizeof irqstr, "irq %lu", ih); 979 return irqstr; 980 } 981 982 void * 983 bonito_pci_intr_establish(void *cookie, pci_intr_handle_t ih, int level, 984 int (*cb)(void *), void *cbarg, char *name) 985 { 986 return bonito_intr_establish(ih, IST_LEVEL, level, cb, cbarg, name); 987 } 988 989 void 990 bonito_pci_intr_disestablish(void *cookie, void *ihp) 991 { 992 bonito_intr_disestablish(ihp); 993 } 994 995 /* 996 * bus_space mapping routines. 997 */ 998 999 /* 1000 * Legacy I/O access protection. 1001 * Since MI ISA code does not expect bus access to cause any failure when 1002 * accessing missing hardware, but only receive bogus data in return, we 1003 * force bus_space_map() to fail if there is no hardware there. 1004 */ 1005 1006 int 1007 bonito_io_map(bus_space_tag_t t, bus_addr_t offs, bus_size_t size, int flags, 1008 bus_space_handle_t *bshp) 1009 { 1010 const struct legacy_io_range *r; 1011 bus_addr_t rend; 1012 1013 if (offs < BONITO_PCIIO_LEGACY) { 1014 if ((r = sys_platform->legacy_io_ranges) == NULL) 1015 return ENXIO; 1016 1017 rend = offs + size - 1; 1018 for (; r->start != 0; r++) 1019 if (offs >= r->start && rend <= r->end) 1020 break; 1021 1022 if (r->end == 0) 1023 return ENXIO; 1024 } 1025 1026 *bshp = t->bus_base + offs; 1027 return 0; 1028 } 1029 1030 /* 1031 * PCI memory access. 1032 * Things are a bit complicated here, as we can either use one of the 64MB 1033 * windows in PCILO space (making sure ranges spanning multiple windows will 1034 * turn contiguous), or a direct access within the PCIHI space. 1035 * Note that, on 2F systems, only the PCIHI range for which CPU->PCI accesses 1036 * are enabled in the crossbar is usable. 1037 */ 1038 1039 int 1040 bonito_mem_map(bus_space_tag_t t, bus_addr_t offs, bus_size_t size, int flags, 1041 bus_space_handle_t *bshp) 1042 { 1043 uint32_t pcimap; 1044 bus_addr_t pcilo_w[3]; 1045 bus_addr_t ws, we, w; 1046 bus_addr_t end = offs + size - 1; 1047 int pcilo_window; 1048 1049 pcimap = REGVAL(BONITO_PCIMAP); 1050 1051 /* 1052 * Try a PCIHI mapping first. 1053 */ 1054 1055 if (loongson_ver >= 0x2f) { 1056 if (offs >= LS2F_PCIHI_BASE && end <= LS2F_PCIHI_TOP) { 1057 *bshp = t->bus_base + offs; 1058 return 0; 1059 } 1060 } else { 1061 /* 1062 * Only try HI space if we do not have memory setup there. 1063 */ 1064 if (physmem <= atop(BONITO_PCILO_BASE)) { 1065 /* PCI1.5 */ 1066 if (offs >= BONITO_PCIHI_BASE && 1067 end <= BONITO_PCIHI_TOP) { 1068 *bshp = t->bus_base + offs; 1069 return 0; 1070 } 1071 1072 /* PCI2 */ 1073 w = pcimap & BONITO_PCIMAP_PCIMAP_2 ? 0x80000000UL : 0; 1074 if (offs >= w && end < (w + 0x80000000UL)) { 1075 *bshp = t->bus_base + 0x80000000UL + (offs - w); 1076 return 0; 1077 } 1078 } 1079 } 1080 1081 /* 1082 * No luck, try a PCILO mapping. 1083 */ 1084 1085 /* 1086 * Decode PCIMAP, and figure out what PCILO mappings are 1087 * possible. 1088 */ 1089 1090 pcilo_w[0] = (pcimap & BONITO_PCIMAP_PCIMAP_LO0) >> 1091 BONITO_PCIMAP_PCIMAP_LO0_SHIFT; 1092 pcilo_w[1] = (pcimap & BONITO_PCIMAP_PCIMAP_LO1) >> 1093 BONITO_PCIMAP_PCIMAP_LO1_SHIFT; 1094 pcilo_w[2] = (pcimap & BONITO_PCIMAP_PCIMAP_LO2) >> 1095 BONITO_PCIMAP_PCIMAP_LO2_SHIFT; 1096 1097 /* 1098 * Check if the 64MB areas we want to span are all available as 1099 * contiguous PCILO mappings. 1100 */ 1101 1102 ws = offs >> 26; 1103 we = end >> 26; 1104 1105 pcilo_window = -1; 1106 if (ws == pcilo_w[0]) 1107 pcilo_window = 0; 1108 else if (ws == pcilo_w[1]) 1109 pcilo_window = 1; 1110 else if (ws == pcilo_w[2]) 1111 pcilo_window = 2; 1112 1113 if (pcilo_window >= 0) { 1114 /* contiguous area test */ 1115 for (w = ws + 1; w <= we; w++) { 1116 if (pcilo_window + (w - ws) > 2 || 1117 w != pcilo_w[pcilo_window + (w - ws)]) { 1118 pcilo_window = -1; 1119 break; 1120 } 1121 } 1122 } 1123 1124 if (pcilo_window >= 0) { 1125 *bshp = t->bus_base + BONITO_PCILO_BASE + 1126 BONITO_PCIMAP_WINBASE(pcilo_window) + 1127 BONITO_PCIMAP_WINOFFSET(offs); 1128 return 0; 1129 } 1130 1131 return EINVAL; 1132 } 1133 1134 /* 1135 * PCI resource handling 1136 */ 1137 1138 struct extent * 1139 bonito_get_resource_extent(pci_chipset_tag_t pc, int io) 1140 { 1141 struct bonito_softc *sc = pc->pc_conf_v; 1142 struct extent *ex; 1143 char *exname; 1144 size_t exnamesz; 1145 uint32_t reg; 1146 int errors; 1147 1148 exnamesz = 1 + 16 + 4; 1149 exname = (char *)malloc(exnamesz, M_DEVBUF, M_NOWAIT); 1150 if (exname == NULL) 1151 return NULL; 1152 snprintf(exname, exnamesz, "%s%s", sc->sc_dev.dv_xname, 1153 io ? "_io" : "_mem"); 1154 1155 ex = extent_create(exname, 0, 0xffffffff, M_DEVBUF, NULL, 0, 1156 EX_NOWAIT | EX_FILLED); 1157 if (ex == NULL) 1158 goto out; 1159 1160 errors = 0; 1161 if (io) { 1162 /* 1163 * Reserve the low 16KB of I/O space to the legacy hardware, 1164 * if any. 1165 */ 1166 if (extent_free(ex, BONITO_PCIIO_LEGACY, BONITO_PCIIO_SIZE, 1167 EX_NOWAIT) != 0) 1168 errors++; 1169 } else { 1170 reg = REGVAL(BONITO_PCIMAP); 1171 if (extent_free(ex, 1172 BONITO_PCIMAP_WINBASE((reg & BONITO_PCIMAP_PCIMAP_LO0) >> 1173 BONITO_PCIMAP_PCIMAP_LO0_SHIFT), 1174 BONITO_PCIMAP_WINSIZE, EX_NOWAIT) != 0) 1175 errors++; 1176 if (extent_free(ex, 1177 BONITO_PCIMAP_WINBASE((reg & BONITO_PCIMAP_PCIMAP_LO1) >> 1178 BONITO_PCIMAP_PCIMAP_LO1_SHIFT), 1179 BONITO_PCIMAP_WINSIZE, EX_NOWAIT) != 0) 1180 errors++; 1181 if (extent_free(ex, 1182 BONITO_PCIMAP_WINBASE((reg & BONITO_PCIMAP_PCIMAP_LO2) >> 1183 BONITO_PCIMAP_PCIMAP_LO2_SHIFT), 1184 BONITO_PCIMAP_WINSIZE, EX_NOWAIT) != 0) 1185 errors++; 1186 1187 if (sc->sc_compatible) { 1188 /* XXX make PCIMAP_HI available if PCIMAP_2 set */ 1189 } 1190 } 1191 1192 if (errors != 0) { 1193 extent_destroy(ex); 1194 ex = NULL; 1195 } 1196 1197 #ifdef BONITO_DEBUG 1198 extent_print(ex); 1199 #endif 1200 1201 out: 1202 free(exname, M_DEVBUF, exnamesz); 1203 1204 return ex; 1205 } 1206 1207 /* 1208 * Functions used during early system configuration (before bonito attaches). 1209 */ 1210 1211 pcitag_t bonito_make_tag_early(int, int, int); 1212 pcireg_t bonito_conf_read_early(pcitag_t, int); 1213 1214 pcitag_t 1215 bonito_make_tag_early(int b, int d, int f) 1216 { 1217 return bonito_make_tag(NULL, b, d, f); 1218 } 1219 1220 pcireg_t 1221 bonito_conf_read_early(pcitag_t tag, int reg) 1222 { 1223 return bonito_conf_read_internal(sys_platform->bonito_config, tag, reg); 1224 } 1225 1226 void 1227 bonito_early_setup() 1228 { 1229 pci_make_tag_early = bonito_make_tag_early; 1230 pci_conf_read_early = bonito_conf_read_early; 1231 1232 early_mem_t = &bonito_pci_mem_space_tag; 1233 early_io_t = &bonito_pci_io_space_tag; 1234 } 1235