1 /* $OpenBSD: intr.h,v 1.18 2019/09/05 05:31:38 visa Exp $ */ 2 3 /* 4 * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 16 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef _MACHINE_INTR_H_ 30 #define _MACHINE_INTR_H_ 31 32 /* 33 * The interrupt level ipl is a logical level; per-platform interrupt 34 * code will turn it into the appropriate hardware interrupt masks 35 * values. 36 * 37 * Interrupt sources on the CPU are kept enabled regardless of the 38 * current ipl value; individual hardware sources interrupting while 39 * logically masked are masked on the fly, remembered as pending, and 40 * unmasked at the first splx() opportunity. 41 * 42 * An exception to this rule is the clock interrupt. Clock interrupts 43 * are always allowed to happen, but will (of course!) not be serviced 44 * if logically masked. The reason for this is that clocks usually sit on 45 * INT5 and cannot be easily masked if external hardware masking is used. 46 */ 47 48 /* Interrupt priority `levels'; not mutually exclusive. */ 49 #define IPL_NONE 0 /* nothing */ 50 #define IPL_SOFTINT 1 /* soft interrupts */ 51 #define IPL_SOFTCLOCK 1 /* soft clock interrupts */ 52 #define IPL_SOFTNET 2 /* soft network interrupts */ 53 #define IPL_SOFTTTY 3 /* soft terminal interrupts */ 54 #define IPL_SOFTHIGH IPL_SOFTTTY /* highest level of soft interrupts */ 55 #define IPL_BIO 4 /* block I/O */ 56 #define IPL_AUDIO IPL_BIO 57 #define IPL_NET 5 /* network */ 58 #define IPL_TTY 6 /* terminal */ 59 #define IPL_VM 7 /* memory allocation */ 60 #define IPL_CLOCK 8 /* clock */ 61 #define IPL_STATCLOCK IPL_CLOCK 62 #define IPL_SCHED 9 /* everything */ 63 #define IPL_HIGH 9 /* everything */ 64 #define IPL_IPI 10 /* interprocessor interrupt */ 65 #define NIPLS 11 /* number of levels */ 66 67 #define IPL_MPFLOOR IPL_TTY 68 69 /* Interrupt priority 'flags'. */ 70 #define IPL_MPSAFE 0x100 71 72 /* Interrupt sharing types. */ 73 #define IST_NONE 0 /* none */ 74 #define IST_PULSE 1 /* pulsed */ 75 #define IST_EDGE 2 /* edge-triggered */ 76 #define IST_LEVEL 3 /* level-triggered */ 77 78 #define SINTBIT(q) (q) 79 #define SINTMASK(q) (1 << SINTBIT(q)) 80 81 /* Soft interrupt masks. */ 82 83 #define SI_SOFTCLOCK 0 /* for IPL_SOFTCLOCK */ 84 #define SI_SOFTNET 1 /* for IPL_SOFTNET */ 85 #define SI_SOFTTTY 2 /* for IPL_SOFTTTY */ 86 87 #define SI_NQUEUES 3 88 89 #ifndef _LOCORE 90 91 #include <sys/mutex.h> 92 #include <sys/queue.h> 93 94 struct soft_intrhand { 95 TAILQ_ENTRY(soft_intrhand) sih_list; 96 void (*sih_func)(void *); 97 void *sih_arg; 98 struct soft_intrq *sih_siq; 99 int sih_pending; 100 }; 101 102 struct soft_intrq { 103 TAILQ_HEAD(, soft_intrhand) siq_list; 104 int siq_si; 105 struct mutex siq_mtx; 106 }; 107 108 void softintr_disestablish(void *); 109 void softintr_dispatch(int); 110 void *softintr_establish(int, void (*)(void *), void *); 111 void softintr_init(void); 112 void softintr_schedule(void *); 113 114 #define splbio() splraise(IPL_BIO) 115 #define splnet() splraise(IPL_NET) 116 #define spltty() splraise(IPL_TTY) 117 #define splaudio() splraise(IPL_AUDIO) 118 #define splclock() splraise(IPL_CLOCK) 119 #define splvm() splraise(IPL_VM) 120 #define splhigh() splraise(IPL_HIGH) 121 122 #define splsoftclock() splraise(IPL_SOFTCLOCK) 123 #define splsoftnet() splraise(IPL_SOFTNET) 124 #define splstatclock() splhigh() 125 126 #define splsched() splhigh() 127 #define spl0() spllower(0) 128 129 void splinit(void); 130 131 #ifdef DIAGNOSTIC 132 /* 133 * Although this function is implemented in MI code, it must be in this MD 134 * header because we don't want this header to include MI includes. 135 */ 136 void splassert_fail(int, int, const char *); 137 extern int splassert_ctl; 138 void splassert_check(int, const char *); 139 #define splassert(__wantipl) do { \ 140 if (splassert_ctl > 0) { \ 141 splassert_check(__wantipl, __func__); \ 142 } \ 143 } while (0) 144 #define splsoftassert(wantipl) splassert(wantipl) 145 #else 146 #define splassert(X) 147 #define splsoftassert(X) 148 #endif 149 150 void register_splx_handler(void (*)(int)); 151 int splraise(int); 152 void splx(int); 153 int spllower(int); 154 155 /* 156 * Interrupt control struct used by interrupt dispatchers 157 * to hold interrupt handler info. 158 */ 159 160 #include <sys/evcount.h> 161 162 struct intrhand { 163 struct intrhand *ih_next; 164 int (*ih_fun)(void *); 165 void *ih_arg; 166 int ih_level; 167 int ih_irq; 168 int ih_flags; 169 #define IH_MPSAFE 0x01 170 struct evcount ih_count; 171 }; 172 173 void intr_barrier(void *); 174 175 /* 176 * Low level interrupt dispatcher registration data. 177 */ 178 179 /* Schedule priorities for base interrupts (CPU) */ 180 #define INTPRI_IPI 0 181 #define INTPRI_CLOCK 1 182 /* other values are system-specific */ 183 184 #define NLOWINT 4 /* Number of low level registrations possible */ 185 186 extern uint32_t idle_mask; 187 188 struct trapframe; 189 void set_intr(int, uint32_t, uint32_t(*)(uint32_t, struct trapframe *)); 190 191 uint32_t updateimask(uint32_t); 192 void dosoftint(void); 193 194 #ifdef MULTIPROCESSOR 195 extern uint32_t ipi_mask; 196 #define ENABLEIPI() updateimask(~ipi_mask) 197 #endif 198 199 struct pic { 200 void (*pic_eoi)(int); 201 void (*pic_mask)(int); 202 void (*pic_unmask)(int); 203 }; 204 205 #ifdef CPU_LOONGSON3 206 207 void loongson3_intr_init(void); 208 void *loongson3_intr_establish(int, int, int (*)(void *), void*, 209 const char *); 210 void loongson3_intr_disestablish(void *); 211 void *loongson3_ht_intr_establish(int, int, int (*)(void *), void*, 212 const char *); 213 void loongson3_ht_intr_disestablish(void *); 214 215 void loongson3_register_ht_pic(const struct pic *); 216 217 #endif /* CPU_LOONGSON3 */ 218 219 #endif /* _LOCORE */ 220 221 #endif /* _MACHINE_INTR_H_ */ 222