1 /* $OpenBSD: mb89352.c,v 1.34 2022/08/29 02:58:13 jsg Exp $ */ 2 /* $NetBSD: mb89352.c,v 1.5 2000/03/23 07:01:31 thorpej Exp $ */ 3 /* NecBSD: mb89352.c,v 1.4 1998/03/14 07:31:20 kmatsuda Exp */ 4 5 #ifdef DDB 6 #define integrate 7 #else 8 #define integrate static __inline 9 #endif 10 11 /*- 12 * Copyright (c) 1996,97,98,99 The NetBSD Foundation, Inc. 13 * All rights reserved. 14 * 15 * This code is derived from software contributed to The NetBSD Foundation 16 * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. All advertising materials mentioning features or use of this software 27 * must display the following acknowledgement: 28 * This product includes software developed by Charles M. Hannum. 29 * 4. The name of the author may not be used to endorse or promote products 30 * derived from this software without specific prior written permission. 31 * 32 * Copyright (c) 1994 Jarle Greipsland 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. The name of the author may not be used to endorse or promote products 44 * derived from this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 48 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 49 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 50 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 51 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 52 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 54 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 55 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 56 * POSSIBILITY OF SUCH DAMAGE. 57 */ 58 /* 59 * [NetBSD for NEC PC-98 series] 60 * Copyright (c) 1996, 1997, 1998 61 * NetBSD/pc98 porting staff. All rights reserved. 62 * Copyright (c) 1996, 1997, 1998 63 * Kouichi Matsuda. All rights reserved. 64 */ 65 66 /* 67 * Acknowledgements: Many of the algorithms used in this driver are 68 * inspired by the work of Julian Elischer (julian@tfs.com) and 69 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 70 */ 71 72 /* TODO list: 73 * 1) Get the DMA stuff working. 74 * 2) Get the iov/uio stuff working. Is this a good thing ??? 75 * 3) Get the synch stuff working. 76 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.? 77 */ 78 79 /* 80 * A few customizable items: 81 */ 82 83 /* Synchronous data transfers? */ 84 #define SPC_USE_SYNCHRONOUS 0 85 #define SPC_SYNC_REQ_ACK_OFS 8 86 87 /* Wide data transfers? */ 88 #define SPC_USE_WIDE 0 89 #define SPC_MAX_WIDTH 0 90 91 /* Max attempts made to transmit a message */ 92 #define SPC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */ 93 94 /* 95 * Some spin loop parameters (essentially how long to wait some places) 96 * The problem(?) is that sometimes we expect either to be able to transmit a 97 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid 98 * returning from the interrupt just to get yanked back for the next byte we 99 * may spin in the interrupt routine waiting for this byte to come. How long? 100 * This is really (SCSI) device and processor dependent. Tuneable, I guess. 101 */ 102 #define SPC_MSGIN_SPIN 1 /* Will spinwait upto ?ms for a new msg byte */ 103 #define SPC_MSGOUT_SPIN 1 104 105 /* 106 * Include debug functions? At the end of this file there are a bunch of 107 * functions that will print out various information regarding queued SCSI 108 * commands, driver state and chip contents. You can call them from the 109 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 110 * kernel uses less memory) but you lose the debugging facilities. 111 */ 112 /* #define SPC_DEBUG */ 113 114 #define SPC_ABORT_TIMEOUT 2000 /* time to wait for abort */ 115 116 /* End of customizable parameters */ 117 118 /* 119 * MB89352 SCSI Protocol Controller (SPC) routines. 120 */ 121 122 #include <sys/param.h> 123 #include <sys/systm.h> 124 #include <sys/kernel.h> 125 #include <sys/errno.h> 126 #include <sys/ioctl.h> 127 #include <sys/device.h> 128 #include <sys/buf.h> 129 #include <sys/proc.h> 130 #include <sys/queue.h> 131 132 #include <machine/intr.h> 133 #include <machine/bus.h> 134 135 #include <scsi/scsi_all.h> 136 #include <scsi/scsi_message.h> 137 #include <scsi/scsiconf.h> 138 139 #include <luna88k/dev/mb89352reg.h> 140 #include <luna88k/dev/mb89352var.h> 141 142 #ifndef DDB 143 #define db_enter() panic("should call debugger here (mb89352.c)") 144 #endif /* ! DDB */ 145 146 #ifdef SPC_DEBUG 147 int spc_debug = 0x00; /* SPC_SHOWSTART|SPC_SHOWMISC|SPC_SHOWTRACE; */ 148 #endif 149 150 void spc_done (struct spc_softc *, struct spc_acb *); 151 void spc_dequeue (struct spc_softc *, struct spc_acb *); 152 void spc_scsi_cmd (struct scsi_xfer *); 153 int spc_poll (struct spc_softc *, struct scsi_xfer *, int); 154 integrate void spc_sched_msgout(struct spc_softc *, u_char); 155 integrate void spc_setsync(struct spc_softc *, struct spc_tinfo *); 156 void spc_select (struct spc_softc *, struct spc_acb *); 157 void spc_timeout (void *); 158 void spc_scsi_reset (struct spc_softc *); 159 void spc_reset (struct spc_softc *); 160 void spc_acb_free (void *, void *); 161 void *spc_acb_alloc (void *); 162 int spc_reselect (struct spc_softc *, int); 163 void spc_sense (struct spc_softc *, struct spc_acb *); 164 void spc_msgin (struct spc_softc *); 165 void spc_abort (struct spc_softc *, struct spc_acb *); 166 void spc_msgout (struct spc_softc *); 167 int spc_dataout_pio (struct spc_softc *, u_char *, int); 168 int spc_datain_pio (struct spc_softc *, u_char *, int); 169 #ifdef SPC_DEBUG 170 void spc_print_acb (struct spc_acb *); 171 void spc_dump_driver (struct spc_softc *); 172 void spc_dump89352 (struct spc_softc *); 173 void spc_show_scsi_cmd(struct spc_acb *); 174 void spc_print_active_acb(void); 175 #endif 176 177 extern struct cfdriver spc_cd; 178 179 #define breathe() \ 180 do { \ 181 asm volatile ("or %r0, %r0, %r0"); \ 182 asm volatile ("or %r0, %r0, %r0"); \ 183 asm volatile ("or %r0, %r0, %r0"); \ 184 asm volatile ("or %r0, %r0, %r0"); \ 185 } while (0) 186 187 /* 188 * INITIALIZATION ROUTINES (probe, attach ++) 189 */ 190 191 void 192 /* spc_attach(sc) */ 193 spc_attach(struct spc_softc *sc, const struct scsi_adapter *adapter) 194 { 195 struct scsibus_attach_args saa; 196 SPC_TRACE(("spc_attach ")); 197 sc->sc_state = SPC_INIT; 198 199 sc->sc_freq = 20; /* XXXX Assume 20 MHz. */ 200 201 #if SPC_USE_SYNCHRONOUS 202 /* 203 * These are the bounds of the sync period, based on the frequency of 204 * the chip's clock input and the size and offset of the sync period 205 * register. 206 * 207 * For a 20MHz clock, this gives us 25, or 100nS, or 10MB/s, as a 208 * maximum transfer rate, and 112.5, or 450nS, or 2.22MB/s, as a 209 * minimum transfer rate. 210 */ 211 sc->sc_minsync = (2 * 250) / sc->sc_freq; 212 sc->sc_maxsync = (9 * 250) / sc->sc_freq; 213 #endif 214 215 spc_init(sc); /* Init chip and driver */ 216 217 saa.saa_adapter_softc = sc; 218 saa.saa_adapter_target = sc->sc_initiator; 219 saa.saa_adapter = adapter; 220 saa.saa_luns = saa.saa_adapter_buswidth = 8; 221 saa.saa_openings = 2; 222 saa.saa_pool = &sc->sc_iopool; 223 saa.saa_flags = saa.saa_quirks = 0; 224 saa.saa_wwpn = saa.saa_wwnn = 0; 225 226 config_found(&sc->sc_dev, &saa, scsiprint); 227 } 228 229 /* 230 * Initialize MB89352 chip itself 231 * The following conditions should hold: 232 * spc_isa_probe should have succeeded, i.e. the iobase address in spc_softc 233 * must be valid. 234 */ 235 void 236 spc_reset(struct spc_softc *sc) 237 { 238 bus_space_tag_t iot = sc->sc_iot; 239 bus_space_handle_t ioh = sc->sc_ioh; 240 241 SPC_TRACE(("spc_reset ")); 242 /* 243 * Disable interrupts then reset the FUJITSU chip. 244 */ 245 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_CTRLRST); 246 bus_space_write_1(iot, ioh, SCMD, 0); 247 bus_space_write_1(iot, ioh, TMOD, 0); 248 bus_space_write_1(iot, ioh, PCTL, 0); 249 bus_space_write_1(iot, ioh, TEMP, 0); 250 bus_space_write_1(iot, ioh, TCH, 0); 251 bus_space_write_1(iot, ioh, TCM, 0); 252 bus_space_write_1(iot, ioh, TCL, 0); 253 bus_space_write_1(iot, ioh, INTS, 0); 254 bus_space_write_1(iot, ioh, SCTL, 255 SCTL_DISABLE | SCTL_ABRT_ENAB | SCTL_PARITY_ENAB | SCTL_RESEL_ENAB); 256 bus_space_write_1(iot, ioh, BDID, sc->sc_initiator); 257 delay(400); 258 bus_space_write_1(iot, ioh, SCTL, 259 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_DISABLE); 260 } 261 262 263 /* 264 * Pull the SCSI RST line for 500us. 265 */ 266 void 267 spc_scsi_reset(struct spc_softc *sc) 268 { 269 bus_space_tag_t iot = sc->sc_iot; 270 bus_space_handle_t ioh = sc->sc_ioh; 271 272 SPC_TRACE(("spc_scsi_reset ")); 273 bus_space_write_1(iot, ioh, SCMD, bus_space_read_1(iot, ioh, SCMD) | SCMD_RST); 274 delay(500); 275 bus_space_write_1(iot, ioh, SCMD, bus_space_read_1(iot, ioh, SCMD) & ~SCMD_RST); 276 delay(50); 277 } 278 279 /* 280 * Initialize spc SCSI driver. 281 */ 282 void 283 spc_init(struct spc_softc *sc) 284 { 285 struct spc_acb *acb; 286 int r; 287 288 SPC_TRACE(("spc_init ")); 289 spc_reset(sc); 290 spc_scsi_reset(sc); 291 spc_reset(sc); 292 293 if (sc->sc_state == SPC_INIT) { 294 /* First time through; initialize. */ 295 TAILQ_INIT(&sc->ready_list); 296 TAILQ_INIT(&sc->nexus_list); 297 TAILQ_INIT(&sc->free_list); 298 mtx_init(&sc->sc_acb_mtx, IPL_BIO); 299 scsi_iopool_init(&sc->sc_iopool, sc, spc_acb_alloc, spc_acb_free); 300 sc->sc_nexus = NULL; 301 acb = sc->sc_acb; 302 bzero(acb, sizeof(sc->sc_acb)); 303 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 304 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 305 acb++; 306 } 307 bzero(&sc->sc_tinfo, sizeof(sc->sc_tinfo)); 308 } else { 309 /* Cancel any active commands. */ 310 sc->sc_state = SPC_CLEANING; 311 if ((acb = sc->sc_nexus) != NULL) { 312 acb->xs->error = XS_DRIVER_STUFFUP; 313 timeout_del(&acb->xs->stimeout); 314 spc_done(sc, acb); 315 } 316 while ((acb = TAILQ_FIRST(&sc->nexus_list)) != NULL) { 317 acb->xs->error = XS_DRIVER_STUFFUP; 318 timeout_del(&acb->xs->stimeout); 319 spc_done(sc, acb); 320 } 321 } 322 323 sc->sc_prevphase = PH_INVALID; 324 for (r = 0; r < 8; r++) { 325 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 326 327 ti->flags = 0; 328 #if SPC_USE_SYNCHRONOUS 329 ti->flags |= DO_SYNC; 330 ti->period = sc->sc_minsync; 331 ti->offset = SPC_SYNC_REQ_ACK_OFS; 332 #else 333 ti->period = ti->offset = 0; 334 #endif 335 #if SPC_USE_WIDE 336 ti->flags |= DO_WIDE; 337 ti->width = SPC_MAX_WIDTH; 338 #else 339 ti->width = 0; 340 #endif 341 } 342 343 sc->sc_state = SPC_IDLE; 344 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SCTL, 345 bus_space_read_1(sc->sc_iot, sc->sc_ioh, SCTL) | SCTL_INTR_ENAB); 346 } 347 348 void 349 spc_acb_free(void *xsc, void *xacb) 350 { 351 struct spc_softc *sc = xsc; 352 struct spc_acb *acb = xacb; 353 354 SPC_TRACE(("spc_acb_free ")); 355 356 acb->flags = 0; 357 mtx_enter(&sc->sc_acb_mtx); 358 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 359 mtx_leave(&sc->sc_acb_mtx); 360 } 361 362 void * 363 spc_acb_alloc(void *xsc) 364 { 365 struct spc_softc *sc = xsc; 366 struct spc_acb *acb; 367 368 SPC_TRACE(("spc_acb_alloc ")); 369 370 mtx_enter(&sc->sc_acb_mtx); 371 acb = TAILQ_FIRST(&sc->free_list); 372 if (acb) 373 TAILQ_REMOVE(&sc->free_list, acb, chain); 374 mtx_leave(&sc->sc_acb_mtx); 375 376 return acb; 377 } 378 379 /* 380 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 381 */ 382 383 /* 384 * Expected sequence: 385 * 1) Command inserted into ready list 386 * 2) Command selected for execution 387 * 3) Command won arbitration and has selected target device 388 * 4) Send message out (identify message, eventually also sync.negotiations) 389 * 5) Send command 390 * 5a) Receive disconnect message, disconnect. 391 * 5b) Reselected by target 392 * 5c) Receive identify message from target. 393 * 6) Send or receive data 394 * 7) Receive status 395 * 8) Receive message (command complete etc.) 396 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 397 * Repeat 2-8 (no disconnects please...) 398 */ 399 400 /* 401 * Start a SCSI-command 402 * This function is called by the higher level SCSI-driver to queue/run 403 * SCSI-commands. 404 */ 405 void 406 spc_scsi_cmd(struct scsi_xfer *xs) 407 { 408 struct scsi_link *sc_link = xs->sc_link; 409 struct spc_softc *sc = sc_link->bus->sb_adapter_softc; 410 struct spc_acb *acb; 411 int s, flags; 412 413 SPC_TRACE(("spc_scsi_cmd ")); 414 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd.opcode, xs->cmdlen, 415 sc_link->target)); 416 417 flags = xs->flags; 418 acb = xs->io; 419 420 /* Initialize acb */ 421 acb->xs = xs; 422 acb->timeout = xs->timeout; 423 timeout_set(&xs->stimeout, spc_timeout, acb); 424 425 if (xs->flags & SCSI_RESET) { 426 acb->flags |= ACB_RESET; 427 acb->scsi_cmd_length = 0; 428 acb->data_length = 0; 429 } else { 430 bcopy(&xs->cmd, &acb->scsi_cmd, xs->cmdlen); 431 acb->scsi_cmd_length = xs->cmdlen; 432 acb->data_addr = xs->data; 433 acb->data_length = xs->datalen; 434 } 435 acb->target_stat = 0; 436 437 s = splbio(); 438 439 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 440 /* 441 * Start scheduling unless a queue process is in progress. 442 */ 443 if (sc->sc_state == SPC_IDLE) 444 spc_sched(sc); 445 /* 446 * After successful sending, check if we should return just now. 447 */ 448 449 splx(s); 450 451 if ((flags & SCSI_POLL) == 0) 452 return; 453 454 /* Not allowed to use interrupts, use polling instead */ 455 s = splbio(); 456 if (spc_poll(sc, xs, acb->timeout)) { 457 spc_timeout(acb); 458 if (spc_poll(sc, xs, acb->timeout)) 459 spc_timeout(acb); 460 } 461 splx(s); 462 } 463 464 /* 465 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 466 */ 467 int 468 spc_poll(struct spc_softc *sc, struct scsi_xfer *xs, int count) 469 { 470 bus_space_tag_t iot = sc->sc_iot; 471 bus_space_handle_t ioh = sc->sc_ioh; 472 473 SPC_TRACE(("spc_poll ")); 474 while (count) { 475 /* 476 * If we had interrupts enabled, would we 477 * have got an interrupt? 478 */ 479 if (bus_space_read_1(iot, ioh, INTS) != 0) 480 spc_intr(sc); 481 if ((xs->flags & ITSDONE) != 0) 482 return 0; 483 delay(1000); 484 count--; 485 } 486 return 1; 487 } 488 489 /* 490 * LOW LEVEL SCSI UTILITIES 491 */ 492 493 integrate void 494 spc_sched_msgout(struct spc_softc *sc, u_char m) 495 { 496 bus_space_tag_t iot = sc->sc_iot; 497 bus_space_handle_t ioh = sc->sc_ioh; 498 499 SPC_TRACE(("spc_sched_msgout ")); 500 if (sc->sc_msgpriq == 0) 501 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN); 502 sc->sc_msgpriq |= m; 503 } 504 505 /* 506 * Set synchronous transfer offset and period. 507 */ 508 integrate void 509 spc_setsync(struct spc_softc *sc, struct spc_tinfo *ti) 510 { 511 #if SPC_USE_SYNCHRONOUS 512 bus_space_tag_t iot = sc->sc_iot; 513 bus_space_handle_t ioh = sc->sc_ioh; 514 515 SPC_TRACE(("spc_setsync ")); 516 if (ti->offset != 0) 517 bus_space_write_1(iot, ioh, TMOD, 518 ((ti->period * sc->sc_freq) / 250 - 2) << 4 | ti->offset); 519 else 520 bus_space_write_1(iot, ioh, TMOD, 0); 521 #endif 522 } 523 524 /* 525 * Start a selection. This is used by spc_sched() to select an idle target, 526 * and by spc_done() to immediately reselect a target to get sense information. 527 */ 528 void 529 spc_select(struct spc_softc *sc, struct spc_acb *acb) 530 { 531 struct scsi_link *sc_link = acb->xs->sc_link; 532 int target = sc_link->target; 533 struct spc_tinfo *ti = &sc->sc_tinfo[target]; 534 bus_space_tag_t iot = sc->sc_iot; 535 bus_space_handle_t ioh = sc->sc_ioh; 536 537 SPC_TRACE(("spc_select ")); 538 spc_setsync(sc, ti); 539 540 #if 0 541 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN); 542 #endif 543 544 bus_space_write_1(iot, ioh, PCTL, 0); 545 bus_space_write_1(iot, ioh, TEMP, 546 (1 << sc->sc_initiator) | (1 << target)); 547 /* 548 * Setup BSY timeout (selection timeout). 549 * 250ms according to the SCSI specification. 550 * T = (X * 256 + 15) * Tclf * 2 (Tclf = 200ns on x68k) 551 * To setup 256ms timeout, 552 * 128000ns/200ns = X * 256 + 15 553 * 640 - 15 = X * 256 554 * X = 625 / 256 555 * X = 2 + 113 / 256 556 * ==> tch = 2, tcm = 113 (correct?) 557 */ 558 /* Time to the information transfer phase start. */ 559 /* XXX These values should be calculated from sc_freq */ 560 bus_space_write_1(iot, ioh, TCH, 2); 561 bus_space_write_1(iot, ioh, TCM, 113); 562 bus_space_write_1(iot, ioh, TCL, 3); 563 bus_space_write_1(iot, ioh, SCMD, SCMD_SELECT); 564 565 sc->sc_state = SPC_SELECTING; 566 } 567 568 int 569 spc_reselect(struct spc_softc *sc, int message) 570 { 571 u_char selid, target, lun; 572 struct spc_acb *acb; 573 struct scsi_link *sc_link; 574 struct spc_tinfo *ti; 575 576 SPC_TRACE(("spc_reselect ")); 577 /* 578 * The SCSI chip made a snapshot of the data bus while the reselection 579 * was being negotiated. This enables us to determine which target did 580 * the reselect. 581 */ 582 selid = sc->sc_selid & ~(1 << sc->sc_initiator); 583 if (selid & (selid - 1)) { 584 printf("%s: reselect with invalid selid %02x; " 585 "sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 586 SPC_BREAK(); 587 goto reset; 588 } 589 590 /* 591 * Search wait queue for disconnected cmd 592 * The list should be short, so I haven't bothered with 593 * any more sophisticated structures than a simple 594 * singly linked list. 595 */ 596 target = ffs(selid) - 1; 597 lun = message & 0x07; 598 TAILQ_FOREACH(acb, &sc->nexus_list, chain) { 599 sc_link = acb->xs->sc_link; 600 if (sc_link->target == target && 601 sc_link->lun == lun) 602 break; 603 } 604 if (acb == NULL) { 605 printf("%s: reselect from target %d lun %d with no nexus; " 606 "sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 607 SPC_BREAK(); 608 goto abort; 609 } 610 611 /* Make this nexus active again. */ 612 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 613 sc->sc_state = SPC_CONNECTED; 614 sc->sc_nexus = acb; 615 ti = &sc->sc_tinfo[target]; 616 ti->lubusy |= (1 << lun); 617 spc_setsync(sc, ti); 618 619 if (acb->flags & ACB_RESET) 620 spc_sched_msgout(sc, SEND_DEV_RESET); 621 else if (acb->flags & ACB_ABORT) 622 spc_sched_msgout(sc, SEND_ABORT); 623 624 /* Do an implicit RESTORE POINTERS. */ 625 sc->sc_dp = acb->data_addr; 626 sc->sc_dleft = acb->data_length; 627 sc->sc_cp = (u_char *)&acb->scsi_cmd; 628 sc->sc_cleft = acb->scsi_cmd_length; 629 630 return (0); 631 632 reset: 633 spc_sched_msgout(sc, SEND_DEV_RESET); 634 return (1); 635 636 abort: 637 spc_sched_msgout(sc, SEND_ABORT); 638 return (1); 639 } 640 641 /* 642 * Schedule a SCSI operation. This has now been pulled out of the interrupt 643 * handler so that we may call it from spc_scsi_cmd and spc_done. This may 644 * save us an unnecessary interrupt just to get things going. Should only be 645 * called when state == SPC_IDLE and at bio pl. 646 */ 647 void 648 spc_sched(struct spc_softc *sc) 649 { 650 struct spc_acb *acb; 651 struct scsi_link *sc_link; 652 struct spc_tinfo *ti; 653 654 /* missing the hw, just return and wait for our hw */ 655 if (sc->sc_flags & SPC_INACTIVE) 656 return; 657 SPC_TRACE(("spc_sched ")); 658 /* 659 * Find first acb in ready queue that is for a target/lunit pair that 660 * is not busy. 661 */ 662 TAILQ_FOREACH(acb, &sc->ready_list, chain) { 663 sc_link = acb->xs->sc_link; 664 ti = &sc->sc_tinfo[sc_link->target]; 665 if ((ti->lubusy & (1 << sc_link->lun)) == 0) { 666 SPC_MISC(("selecting %d:%d ", 667 sc_link->target, sc_link->lun)); 668 TAILQ_REMOVE(&sc->ready_list, acb, chain); 669 sc->sc_nexus = acb; 670 spc_select(sc, acb); 671 return; 672 } else 673 SPC_MISC(("%d:%d busy\n", 674 sc_link->target, sc_link->lun)); 675 } 676 SPC_MISC(("idle ")); 677 /* Nothing to start; just enable reselections and wait. */ 678 } 679 680 void 681 spc_sense(struct spc_softc *sc, struct spc_acb *acb) 682 { 683 struct scsi_xfer *xs = acb->xs; 684 struct scsi_link *sc_link = xs->sc_link; 685 struct spc_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 686 struct scsi_sense *ss = (void *)&acb->scsi_cmd; 687 688 SPC_MISC(("requesting sense ")); 689 /* Next, setup a request sense command block */ 690 bzero(ss, sizeof(*ss)); 691 ss->opcode = REQUEST_SENSE; 692 ss->byte2 = sc_link->lun << 5; 693 ss->length = sizeof(struct scsi_sense_data); 694 acb->scsi_cmd_length = sizeof(*ss); 695 acb->data_addr = (char *)&xs->sense; 696 acb->data_length = sizeof(struct scsi_sense_data); 697 acb->flags |= ACB_SENSE; 698 ti->senses++; 699 if (acb->flags & ACB_NEXUS) 700 ti->lubusy &= ~(1 << sc_link->lun); 701 if (acb == sc->sc_nexus) { 702 spc_select(sc, acb); 703 } else { 704 spc_dequeue(sc, acb); 705 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 706 if (sc->sc_state == SPC_IDLE) 707 spc_sched(sc); 708 } 709 } 710 711 /* 712 * POST PROCESSING OF SCSI_CMD (usually current) 713 */ 714 void 715 spc_done(struct spc_softc *sc, struct spc_acb *acb) 716 { 717 struct scsi_xfer *xs = acb->xs; 718 struct scsi_link *sc_link = xs->sc_link; 719 struct spc_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 720 721 SPC_TRACE(("spc_done ")); 722 723 /* 724 * Now, if we've come here with no error code, i.e. we've kept the 725 * initial XS_NOERROR, and the status code signals that we should 726 * check sense, we'll need to set up a request sense cmd block and 727 * push the command back into the ready queue *before* any other 728 * commands for this target/lunit, else we lose the sense info. 729 * We don't support chk sense conditions for the request sense cmd. 730 */ 731 if (xs->error == XS_NOERROR) { 732 if (acb->flags & ACB_ABORT) { 733 xs->error = XS_DRIVER_STUFFUP; 734 } else if (acb->flags & ACB_SENSE) { 735 xs->error = XS_SENSE; 736 } else { 737 switch (acb->target_stat) { 738 case SCSI_CHECK: 739 /* First, save the return values */ 740 xs->resid = acb->data_length; 741 xs->status = acb->target_stat; 742 spc_sense(sc, acb); 743 return; 744 case SCSI_BUSY: 745 xs->error = XS_BUSY; 746 break; 747 case SCSI_OK: 748 xs->resid = acb->data_length; 749 break; 750 default: 751 xs->error = XS_DRIVER_STUFFUP; 752 #ifdef SPC_DEBUG 753 printf("%s: spc_done: bad stat 0x%x\n", 754 sc->sc_dev.dv_xname, acb->target_stat); 755 #endif 756 break; 757 } 758 } 759 } 760 761 #ifdef SPC_DEBUG 762 if ((spc_debug & SPC_SHOWMISC) != 0) { 763 if (xs->resid != 0) 764 printf("resid=%d ", xs->resid); 765 if (xs->error == XS_SENSE) 766 printf("sense=0x%02x\n", xs->sense.error_code); 767 else 768 printf("error=%d\n", xs->error); 769 } 770 #endif 771 772 /* 773 * Remove the ACB from whatever queue it happens to be on. 774 */ 775 if (acb->flags & ACB_NEXUS) 776 ti->lubusy &= ~(1 << sc_link->lun); 777 if (acb == sc->sc_nexus) { 778 sc->sc_nexus = NULL; 779 sc->sc_state = SPC_IDLE; 780 spc_sched(sc); 781 } else 782 spc_dequeue(sc, acb); 783 784 ti->cmds++; 785 scsi_done(xs); 786 } 787 788 void 789 spc_dequeue(struct spc_softc *sc, struct spc_acb *acb) 790 { 791 792 SPC_TRACE(("spc_dequeue ")); 793 if (acb->flags & ACB_NEXUS) 794 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 795 else 796 TAILQ_REMOVE(&sc->ready_list, acb, chain); 797 } 798 799 /* 800 * INTERRUPT/PROTOCOL ENGINE 801 */ 802 803 /* 804 * Precondition: 805 * The SCSI bus is already in the MSGI phase and there is a message byte 806 * on the bus, along with an asserted REQ signal. 807 */ 808 void 809 spc_msgin(struct spc_softc *sc) 810 { 811 bus_space_tag_t iot = sc->sc_iot; 812 bus_space_handle_t ioh = sc->sc_ioh; 813 int n; 814 815 SPC_TRACE(("spc_msgin ")); 816 817 if (sc->sc_prevphase == PH_MSGIN) { 818 /* This is a continuation of the previous message. */ 819 n = sc->sc_imp - sc->sc_imess; 820 goto nextbyte; 821 } 822 823 /* This is a new MESSAGE IN phase. Clean up our state. */ 824 sc->sc_flags &= ~SPC_DROP_MSGIN; 825 826 nextmsg: 827 n = 0; 828 sc->sc_imp = &sc->sc_imess[n]; 829 830 nextbyte: 831 /* 832 * Read a whole message, but don't ack the last byte. If we reject the 833 * message, we have to assert ATN during the message transfer phase 834 * itself. 835 */ 836 for (;;) { 837 u_int8_t intstat; 838 #if 0 839 for (;;) { 840 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0) 841 break; 842 /* Wait for REQINIT. XXX Need timeout. */ 843 } 844 #endif 845 if (bus_space_read_1(iot, ioh, INTS) != 0) { 846 /* 847 * Target left MESSAGE IN, probably because it 848 * a) noticed our ATN signal, or 849 * b) ran out of messages. 850 */ 851 goto out; 852 } 853 854 /* If parity error, just dump everything on the floor. */ 855 if ((bus_space_read_1(iot, ioh, SERR) & 856 (SERR_SCSI_PAR|SERR_SPC_PAR)) != 0) { 857 sc->sc_flags |= SPC_DROP_MSGIN; 858 spc_sched_msgout(sc, SEND_PARITY_ERROR); 859 } 860 861 /* send TRANSFER command. */ 862 bus_space_write_1(iot, ioh, TCH, 0); 863 bus_space_write_1(iot, ioh, TCM, 0); 864 bus_space_write_1(iot, ioh, TCL, 1); 865 bus_space_write_1(iot, ioh, PCTL, 866 sc->sc_phase | PCTL_BFINT_ENAB); 867 #ifdef x68k 868 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* | SCMD_PROG_XFR */ 869 #else 870 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR | SCMD_PROG_XFR); /* XXX */ 871 #endif 872 intstat = 0; 873 for (;;) { 874 /*if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0 875 && (bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_EMPTY) != 0)*/ 876 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_EMPTY) == 0) 877 break; 878 /* 879 * We have to read INTS before checking SSTS to avoid 880 * race between SSTS_DREG_EMPTY and INTS_CMD_DONE. 881 */ 882 if (intstat != 0) 883 goto out; 884 intstat = bus_space_read_1(iot, ioh, INTS); 885 } 886 887 /* Gather incoming message bytes if needed. */ 888 if ((sc->sc_flags & SPC_DROP_MSGIN) == 0) { 889 if (n >= SPC_MAX_MSG_LEN) { 890 (void) bus_space_read_1(iot, ioh, DREG); 891 sc->sc_flags |= SPC_DROP_MSGIN; 892 spc_sched_msgout(sc, SEND_REJECT); 893 } else { 894 *sc->sc_imp++ = bus_space_read_1(iot, ioh, DREG); 895 n++; 896 /* 897 * This testing is suboptimal, but most 898 * messages will be of the one byte variety, so 899 * it should not affect performance 900 * significantly. 901 */ 902 if (n == 1 && IS1BYTEMSG(sc->sc_imess[0])) 903 break; 904 if (n == 2 && IS2BYTEMSG(sc->sc_imess[0])) 905 break; 906 if (n >= 3 && ISEXTMSG(sc->sc_imess[0]) && 907 n == sc->sc_imess[1] + 2) 908 break; 909 } 910 } else 911 (void) bus_space_read_1(iot, ioh, DREG); 912 913 /* 914 * If we reach this spot we're either: 915 * a) in the middle of a multi-byte message, or 916 * b) dropping bytes. 917 */ 918 #if 0 919 /* Ack the last byte read. */ 920 /*(void) bus_space_read_1(iot, ioh, DREG);*/ 921 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0) 922 ; 923 #endif 924 } 925 926 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 927 928 /* We now have a complete message. Parse it. */ 929 switch (sc->sc_state) { 930 struct spc_acb *acb; 931 struct scsi_link *sc_link; 932 struct spc_tinfo *ti; 933 934 case SPC_CONNECTED: 935 SPC_ASSERT(sc->sc_nexus != NULL); 936 acb = sc->sc_nexus; 937 ti = &sc->sc_tinfo[acb->xs->sc_link->target]; 938 939 switch (sc->sc_imess[0]) { 940 case MSG_CMDCOMPLETE: 941 if (sc->sc_dleft < 0) { 942 sc_link = acb->xs->sc_link; 943 printf("%s: %ld extra bytes from %d:%d\n", 944 sc->sc_dev.dv_xname, -sc->sc_dleft, 945 sc_link->target, sc_link->lun); 946 acb->data_length = 0; 947 } 948 acb->xs->resid = acb->data_length = sc->sc_dleft; 949 sc->sc_state = SPC_CMDCOMPLETE; 950 break; 951 952 case MSG_PARITY_ERROR: 953 /* Resend the last message. */ 954 spc_sched_msgout(sc, sc->sc_lastmsg); 955 break; 956 957 case MSG_MESSAGE_REJECT: 958 SPC_MISC(("message rejected %02x ", sc->sc_lastmsg)); 959 switch (sc->sc_lastmsg) { 960 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE 961 case SEND_IDENTIFY: 962 ti->flags &= ~(DO_SYNC | DO_WIDE); 963 ti->period = ti->offset = 0; 964 spc_setsync(sc, ti); 965 ti->width = 0; 966 break; 967 #endif 968 #if SPC_USE_SYNCHRONOUS 969 case SEND_SDTR: 970 ti->flags &= ~DO_SYNC; 971 ti->period = ti->offset = 0; 972 spc_setsync(sc, ti); 973 break; 974 #endif 975 #if SPC_USE_WIDE 976 case SEND_WDTR: 977 ti->flags &= ~DO_WIDE; 978 ti->width = 0; 979 break; 980 #endif 981 case SEND_INIT_DET_ERR: 982 spc_sched_msgout(sc, SEND_ABORT); 983 break; 984 } 985 break; 986 987 case MSG_NOOP: 988 break; 989 990 case MSG_DISCONNECT: 991 ti->dconns++; 992 sc->sc_state = SPC_DISCONNECT; 993 break; 994 995 case MSG_SAVEDATAPOINTER: 996 acb->data_addr = sc->sc_dp; 997 acb->data_length = sc->sc_dleft; 998 break; 999 1000 case MSG_RESTOREPOINTERS: 1001 sc->sc_dp = acb->data_addr; 1002 sc->sc_dleft = acb->data_length; 1003 sc->sc_cp = (u_char *)&acb->scsi_cmd; 1004 sc->sc_cleft = acb->scsi_cmd_length; 1005 break; 1006 1007 case MSG_EXTENDED: 1008 switch (sc->sc_imess[2]) { 1009 #if SPC_USE_SYNCHRONOUS 1010 case MSG_EXT_SDTR: 1011 if (sc->sc_imess[1] != 3) 1012 goto reject; 1013 ti->period = sc->sc_imess[3]; 1014 ti->offset = sc->sc_imess[4]; 1015 ti->flags &= ~DO_SYNC; 1016 if (ti->offset == 0) { 1017 } else if (ti->period < sc->sc_minsync || 1018 ti->period > sc->sc_maxsync || 1019 ti->offset > 8) { 1020 ti->period = ti->offset = 0; 1021 spc_sched_msgout(sc, SEND_SDTR); 1022 } else { 1023 sc_print_addr(acb->xs->sc_link); 1024 printf("sync, offset %d, " 1025 "period %dnsec\n", 1026 ti->offset, ti->period * 4); 1027 } 1028 spc_setsync(sc, ti); 1029 break; 1030 #endif 1031 1032 #if SPC_USE_WIDE 1033 case MSG_EXT_WDTR: 1034 if (sc->sc_imess[1] != 2) 1035 goto reject; 1036 ti->width = sc->sc_imess[3]; 1037 ti->flags &= ~DO_WIDE; 1038 if (ti->width == 0) { 1039 } else if (ti->width > SPC_MAX_WIDTH) { 1040 ti->width = 0; 1041 spc_sched_msgout(sc, SEND_WDTR); 1042 } else { 1043 sc_print_addr(acb->xs->sc_link); 1044 printf("wide, width %d\n", 1045 1 << (3 + ti->width)); 1046 } 1047 break; 1048 #endif 1049 1050 default: 1051 printf("%s: unrecognized MESSAGE EXTENDED; " 1052 "sending REJECT\n", sc->sc_dev.dv_xname); 1053 SPC_BREAK(); 1054 goto reject; 1055 } 1056 break; 1057 1058 default: 1059 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1060 sc->sc_dev.dv_xname); 1061 SPC_BREAK(); 1062 reject: 1063 spc_sched_msgout(sc, SEND_REJECT); 1064 break; 1065 } 1066 break; 1067 1068 case SPC_RESELECTED: 1069 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1070 printf("%s: reselect without IDENTIFY; " 1071 "sending DEVICE RESET\n", sc->sc_dev.dv_xname); 1072 SPC_BREAK(); 1073 goto reset; 1074 } 1075 1076 (void) spc_reselect(sc, sc->sc_imess[0]); 1077 break; 1078 1079 default: 1080 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1081 sc->sc_dev.dv_xname); 1082 SPC_BREAK(); 1083 reset: 1084 spc_sched_msgout(sc, SEND_DEV_RESET); 1085 break; 1086 1087 #ifdef notdef 1088 abort: 1089 spc_sched_msgout(sc, SEND_ABORT); 1090 break; 1091 #endif 1092 } 1093 1094 /* Ack the last message byte. */ 1095 #if 0 /* XXX? */ 1096 (void) bus_space_read_1(iot, ioh, DREG); 1097 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0) 1098 ; 1099 #endif 1100 1101 /* Go get the next message, if any. */ 1102 goto nextmsg; 1103 1104 out: 1105 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK); 1106 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1107 } 1108 1109 /* 1110 * Send the highest priority, scheduled message. 1111 */ 1112 void 1113 spc_msgout(struct spc_softc *sc) 1114 { 1115 bus_space_tag_t iot = sc->sc_iot; 1116 bus_space_handle_t ioh = sc->sc_ioh; 1117 #if SPC_USE_SYNCHRONOUS 1118 struct spc_tinfo *ti; 1119 #endif 1120 int n; 1121 1122 SPC_TRACE(("spc_msgout ")); 1123 1124 if (sc->sc_prevphase == PH_MSGOUT) { 1125 if (sc->sc_omp == sc->sc_omess) { 1126 /* 1127 * This is a retransmission. 1128 * 1129 * We get here if the target stayed in MESSAGE OUT 1130 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1131 * that all of the previously transmitted messages must 1132 * be sent again, in the same order. Therefore, we 1133 * requeue all the previously transmitted messages, and 1134 * start again from the top. Our simple priority 1135 * scheme keeps the messages in the right order. 1136 */ 1137 SPC_MISC(("retransmitting ")); 1138 sc->sc_msgpriq |= sc->sc_msgoutq; 1139 /* 1140 * Set ATN. If we're just sending a trivial 1-byte 1141 * message, we'll clear ATN later on anyway. 1142 */ 1143 bus_space_write_1(iot, ioh, SCMD, 1144 SCMD_SET_ATN); /* XXX? */ 1145 } else { 1146 /* This is a continuation of the previous message. */ 1147 n = sc->sc_omp - sc->sc_omess; 1148 goto nextbyte; 1149 } 1150 } 1151 1152 /* No messages transmitted so far. */ 1153 sc->sc_msgoutq = 0; 1154 sc->sc_lastmsg = 0; 1155 1156 nextmsg: 1157 /* Pick up highest priority message. */ 1158 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1159 sc->sc_msgpriq &= ~sc->sc_currmsg; 1160 sc->sc_msgoutq |= sc->sc_currmsg; 1161 1162 /* Build the outgoing message data. */ 1163 switch (sc->sc_currmsg) { 1164 case SEND_IDENTIFY: 1165 SPC_ASSERT(sc->sc_nexus != NULL); 1166 sc->sc_omess[0] = 1167 MSG_IDENTIFY(sc->sc_nexus->xs->sc_link->lun, 1); 1168 n = 1; 1169 break; 1170 1171 #if SPC_USE_SYNCHRONOUS 1172 case SEND_SDTR: 1173 SPC_ASSERT(sc->sc_nexus != NULL); 1174 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->target]; 1175 sc->sc_omess[4] = MSG_EXTENDED; 1176 sc->sc_omess[3] = MSG_EXT_SDTR_LEN; 1177 sc->sc_omess[2] = MSG_EXT_SDTR; 1178 sc->sc_omess[1] = ti->period >> 2; 1179 sc->sc_omess[0] = ti->offset; 1180 n = 5; 1181 break; 1182 #endif 1183 1184 #if SPC_USE_WIDE 1185 case SEND_WDTR: 1186 SPC_ASSERT(sc->sc_nexus != NULL); 1187 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->target]; 1188 sc->sc_omess[3] = MSG_EXTENDED; 1189 sc->sc_omess[2] = MSG_EXT_WDTR_LEN; 1190 sc->sc_omess[1] = MSG_EXT_WDTR; 1191 sc->sc_omess[0] = ti->width; 1192 n = 4; 1193 break; 1194 #endif 1195 1196 case SEND_DEV_RESET: 1197 sc->sc_flags |= SPC_ABORTING; 1198 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1199 n = 1; 1200 break; 1201 1202 case SEND_REJECT: 1203 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1204 n = 1; 1205 break; 1206 1207 case SEND_PARITY_ERROR: 1208 sc->sc_omess[0] = MSG_PARITY_ERROR; 1209 n = 1; 1210 break; 1211 1212 case SEND_INIT_DET_ERR: 1213 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1214 n = 1; 1215 break; 1216 1217 case SEND_ABORT: 1218 sc->sc_flags |= SPC_ABORTING; 1219 sc->sc_omess[0] = MSG_ABORT; 1220 n = 1; 1221 break; 1222 1223 default: 1224 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1225 sc->sc_dev.dv_xname); 1226 SPC_BREAK(); 1227 sc->sc_omess[0] = MSG_NOOP; 1228 n = 1; 1229 break; 1230 } 1231 sc->sc_omp = &sc->sc_omess[n]; 1232 1233 nextbyte: 1234 /* Send message bytes. */ 1235 /* send TRANSFER command. */ 1236 bus_space_write_1(iot, ioh, TCH, n >> 16); 1237 bus_space_write_1(iot, ioh, TCM, n >> 8); 1238 bus_space_write_1(iot, ioh, TCL, n); 1239 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB); 1240 #ifdef x68k 1241 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */ 1242 #else 1243 bus_space_write_1(iot, ioh, SCMD, 1244 SCMD_XFR | SCMD_PROG_XFR | SCMD_ICPT_XFR); 1245 #endif 1246 for (;;) { 1247 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) 1248 break; 1249 if (bus_space_read_1(iot, ioh, INTS) != 0) 1250 goto out; 1251 } 1252 for (;;) { 1253 #if 0 1254 for (;;) { 1255 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0) 1256 break; 1257 /* Wait for REQINIT. XXX Need timeout. */ 1258 } 1259 #endif 1260 if (bus_space_read_1(iot, ioh, INTS) != 0) { 1261 /* 1262 * Target left MESSAGE OUT, possibly to reject 1263 * our message. 1264 * 1265 * If this is the last message being sent, then we 1266 * deassert ATN, since either the target is going to 1267 * ignore this message, or it's going to ask for a 1268 * retransmission via MESSAGE PARITY ERROR (in which 1269 * case we reassert ATN anyway). 1270 */ 1271 #if 0 1272 if (sc->sc_msgpriq == 0) 1273 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 1274 #endif 1275 goto out; 1276 } 1277 1278 #if 0 1279 /* Clear ATN before last byte if this is the last message. */ 1280 if (n == 1 && sc->sc_msgpriq == 0) 1281 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 1282 #endif 1283 1284 while ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_FULL) != 0) 1285 ; 1286 /* Send message byte. */ 1287 bus_space_write_1(iot, ioh, DREG, *--sc->sc_omp); 1288 --n; 1289 /* Keep track of the last message we've sent any bytes of. */ 1290 sc->sc_lastmsg = sc->sc_currmsg; 1291 #if 0 1292 /* Wait for ACK to be negated. XXX Need timeout. */ 1293 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0) 1294 ; 1295 #endif 1296 1297 if (n == 0) 1298 break; 1299 } 1300 1301 /* We get here only if the entire message has been transmitted. */ 1302 if (sc->sc_msgpriq != 0) { 1303 /* There are more outgoing messages. */ 1304 goto nextmsg; 1305 } 1306 1307 /* 1308 * The last message has been transmitted. We need to remember the last 1309 * message transmitted (in case the target switches to MESSAGE IN phase 1310 * and sends a MESSAGE REJECT), and the list of messages transmitted 1311 * this time around (in case the target stays in MESSAGE OUT phase to 1312 * request a retransmit). 1313 */ 1314 1315 out: 1316 /* Disable REQ/ACK protocol. */ 1317 return; 1318 } 1319 1320 /* 1321 * spc_dataout_pio: perform a data transfer using the FIFO datapath in the spc 1322 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted 1323 * and ACK deasserted (i.e. waiting for a data byte). 1324 * 1325 * This new revision has been optimized (I tried) to make the common case fast, 1326 * and the rarer cases (as a result) somewhat more complex. 1327 */ 1328 int 1329 spc_dataout_pio(struct spc_softc *sc, u_char *p, int n) 1330 { 1331 bus_space_tag_t iot = sc->sc_iot; 1332 bus_space_handle_t ioh = sc->sc_ioh; 1333 u_char intstat = 0; 1334 int out = 0; 1335 #define DOUTAMOUNT 8 /* Full FIFO */ 1336 1337 SPC_TRACE(("spc_dataout_pio ")); 1338 /* send TRANSFER command. */ 1339 bus_space_write_1(iot, ioh, TCH, n >> 16); 1340 bus_space_write_1(iot, ioh, TCM, n >> 8); 1341 bus_space_write_1(iot, ioh, TCL, n); 1342 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB); 1343 #ifdef x68k 1344 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */ 1345 #else 1346 bus_space_write_1(iot, ioh, SCMD, 1347 SCMD_XFR | SCMD_PROG_XFR | SCMD_ICPT_XFR); /* XXX */ 1348 #endif 1349 for (;;) { 1350 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) 1351 break; 1352 if (bus_space_read_1(iot, ioh, INTS) != 0) 1353 break; 1354 } 1355 1356 /* 1357 * I have tried to make the main loop as tight as possible. This 1358 * means that some of the code following the loop is a bit more 1359 * complex than otherwise. 1360 */ 1361 while (n > 0) { 1362 int xfer; 1363 1364 for (;;) { 1365 intstat = bus_space_read_1(iot, ioh, INTS); 1366 /* Wait till buffer is empty. */ 1367 if ((bus_space_read_1(iot, ioh, SSTS) & 1368 SSTS_DREG_EMPTY) != 0) 1369 break; 1370 /* Break on interrupt. */ 1371 if (intstat != 0) 1372 goto phasechange; 1373 } 1374 1375 xfer = min(DOUTAMOUNT, n); 1376 1377 SPC_MISC(("%d> ", xfer)); 1378 1379 n -= xfer; 1380 out += xfer; 1381 #if 0 1382 bus_space_write_multi_1(iot, ioh, DREG, p, xfer); 1383 p += xfer; 1384 #else 1385 switch (xfer) { 1386 case 8: 1387 bus_space_write_1(iot, ioh, DREG, *p++); 1388 case 7: 1389 bus_space_write_1(iot, ioh, DREG, *p++); 1390 case 6: 1391 bus_space_write_1(iot, ioh, DREG, *p++); 1392 case 5: 1393 bus_space_write_1(iot, ioh, DREG, *p++); 1394 case 4: 1395 bus_space_write_1(iot, ioh, DREG, *p++); 1396 case 3: 1397 bus_space_write_1(iot, ioh, DREG, *p++); 1398 case 2: 1399 bus_space_write_1(iot, ioh, DREG, *p++); 1400 case 1: 1401 bus_space_write_1(iot, ioh, DREG, *p++); 1402 } 1403 #endif 1404 } 1405 1406 if (out == 0) { 1407 for (;;) { 1408 if (bus_space_read_1(iot, ioh, INTS) != 0) 1409 break; 1410 } 1411 SPC_MISC(("extra data ")); 1412 } else { 1413 /* See the bytes off chip */ 1414 for (;;) { 1415 /* Wait till buffer is empty. */ 1416 if ((bus_space_read_1(iot, ioh, SSTS) & 1417 SSTS_DREG_EMPTY) != 0) 1418 break; 1419 intstat = bus_space_read_1(iot, ioh, INTS); 1420 /* Break on interrupt. */ 1421 if (intstat != 0) 1422 goto phasechange; 1423 } 1424 } 1425 1426 phasechange: 1427 /* Stop the FIFO data path. */ 1428 1429 if (intstat != 0) { 1430 /* Some sort of phase change. */ 1431 int amount; 1432 1433 amount = ((bus_space_read_1(iot, ioh, TCH) << 16) | 1434 (bus_space_read_1(iot, ioh, TCM) << 8) | 1435 bus_space_read_1(iot, ioh, TCL)); 1436 if (amount > 0) { 1437 out -= amount; 1438 SPC_MISC(("+%d ", amount)); 1439 } 1440 } 1441 1442 return out; 1443 } 1444 1445 /* 1446 * spc_datain_pio: perform data transfers using the FIFO datapath in the spc 1447 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted 1448 * and ACK deasserted (i.e. at least one byte is ready). 1449 * 1450 * For now, uses a pretty dumb algorithm, hangs around until all data has been 1451 * transferred. This, is OK for fast targets, but not so smart for slow 1452 * targets which don't disconnect or for huge transfers. 1453 */ 1454 int 1455 spc_datain_pio(struct spc_softc *sc, u_char *p, int n) 1456 { 1457 bus_space_tag_t iot = sc->sc_iot; 1458 bus_space_handle_t ioh = sc->sc_ioh; 1459 u_int8_t intstat, sstat; 1460 int in = 0; 1461 #define DINAMOUNT 8 /* Full FIFO */ 1462 1463 SPC_TRACE(("spc_datain_pio ")); 1464 /* send TRANSFER command. */ 1465 bus_space_write_1(iot, ioh, TCH, n >> 16); 1466 bus_space_write_1(iot, ioh, TCM, n >> 8); 1467 bus_space_write_1(iot, ioh, TCL, n); 1468 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB); 1469 #ifdef x68k 1470 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */ 1471 #else 1472 bus_space_write_1(iot, ioh, SCMD, 1473 SCMD_XFR | SCMD_PROG_XFR); /* XXX */ 1474 #endif 1475 for (;;) { 1476 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) 1477 break; 1478 if (bus_space_read_1(iot, ioh, INTS) != 0) 1479 goto phasechange; 1480 } 1481 1482 /* 1483 * We leave this loop if one or more of the following is true: 1484 * a) phase != PH_DATAIN && FIFOs are empty 1485 * b) reset has occurred or busfree is detected. 1486 */ 1487 while (n > 0) { 1488 int xfer; 1489 1490 /* Wait for fifo half full or phase mismatch */ 1491 for (;;) { 1492 intstat = bus_space_read_1(iot, ioh, INTS); 1493 sstat = bus_space_read_1(iot, ioh, SSTS); 1494 if (intstat != 0 || 1495 (sstat & SSTS_DREG_FULL) != 0 || 1496 (sstat & SSTS_DREG_EMPTY) == 0) 1497 break; 1498 } 1499 1500 #if 1 1501 if (intstat != 0) 1502 goto phasechange; 1503 #else 1504 if (intstat != 0 && 1505 (sstat & SSTS_DREG_EMPTY) != 0) 1506 goto phasechange; 1507 #endif 1508 if ((sstat & SSTS_DREG_FULL) != 0) 1509 xfer = min(DINAMOUNT, n); 1510 else 1511 xfer = 1; 1512 1513 SPC_MISC((">%d ", xfer)); 1514 1515 n -= xfer; 1516 in += xfer; 1517 #if 0 1518 bus_space_read_multi_1(iot, ioh, DREG, p, xfer); 1519 p += xfer; 1520 #else 1521 switch (xfer) { 1522 case 8: 1523 *p++ = bus_space_read_1(iot, ioh, DREG); 1524 case 7: 1525 *p++ = bus_space_read_1(iot, ioh, DREG); 1526 case 6: 1527 *p++ = bus_space_read_1(iot, ioh, DREG); 1528 case 5: 1529 *p++ = bus_space_read_1(iot, ioh, DREG); 1530 case 4: 1531 *p++ = bus_space_read_1(iot, ioh, DREG); 1532 case 3: 1533 *p++ = bus_space_read_1(iot, ioh, DREG); 1534 case 2: 1535 *p++ = bus_space_read_1(iot, ioh, DREG); 1536 case 1: 1537 *p++ = bus_space_read_1(iot, ioh, DREG); 1538 } 1539 #endif 1540 1541 if (intstat != 0) 1542 goto phasechange; 1543 } 1544 1545 /* 1546 * Some SCSI-devices are rude enough to transfer more data than what 1547 * was requested, e.g. 2048 bytes from a CD-ROM instead of the 1548 * requested 512. Test for progress, i.e. real transfers. If no real 1549 * transfers have been performed (n is probably already zero) and the 1550 * FIFO is not empty, waste some bytes.... 1551 */ 1552 if (in == 0) { 1553 for (;;) { 1554 /* XXX needs timeout */ 1555 if (bus_space_read_1(iot, ioh, INTS) != 0) 1556 break; 1557 } 1558 SPC_MISC(("extra data ")); 1559 } 1560 1561 phasechange: 1562 /* Stop the FIFO data path. */ 1563 1564 return in; 1565 } 1566 1567 /* 1568 * Catch an interrupt from the adaptor 1569 */ 1570 /* 1571 * This is the workhorse routine of the driver. 1572 * Deficiencies (for now): 1573 * 1) always uses programmed I/O 1574 */ 1575 int 1576 spc_intr(void *arg) 1577 { 1578 struct spc_softc *sc = arg; 1579 bus_space_tag_t iot = sc->sc_iot; 1580 bus_space_handle_t ioh = sc->sc_ioh; 1581 u_char ints; 1582 struct spc_acb *acb; 1583 struct scsi_link *sc_link; 1584 struct spc_tinfo *ti; 1585 int n; 1586 1587 /* 1588 * On LUNA-88K2, 2 spc(4)'s share the level 3 interrupt. 1589 * So, first, check if this device needs to process this interrupt. 1590 */ 1591 ints = bus_space_read_1(iot, ioh, INTS); 1592 if (ints == 0) /* No interrupt event on this device */ 1593 return 0; 1594 1595 /* 1596 * Disable interrupt. 1597 */ 1598 bus_space_write_1(iot, ioh, SCTL, 1599 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_INTR_ENAB); 1600 1601 SPC_TRACE(("spc_intr ")); 1602 1603 loop: 1604 /* 1605 * Loop until transfer completion. 1606 */ 1607 /* 1608 * First check for abnormal conditions, such as reset. 1609 */ 1610 #ifdef x68k /* XXX? */ 1611 while ((ints = bus_space_read_1(iot, ioh, INTS)) == 0) 1612 delay(1); 1613 SPC_MISC(("ints = 0x%x ", ints)); 1614 #else 1615 ints = bus_space_read_1(iot, ioh, INTS); 1616 SPC_MISC(("ints = 0x%x ", ints)); 1617 #endif 1618 1619 if ((ints & INTS_RST) != 0) { 1620 printf("%s: SCSI bus reset\n", sc->sc_dev.dv_xname); 1621 goto reset; 1622 } 1623 1624 /* 1625 * Check for less serious errors. 1626 */ 1627 if ((bus_space_read_1(iot, ioh, SERR) & (SERR_SCSI_PAR|SERR_SPC_PAR)) 1628 != 0) { 1629 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1630 if (sc->sc_prevphase == PH_MSGIN) { 1631 sc->sc_flags |= SPC_DROP_MSGIN; 1632 spc_sched_msgout(sc, SEND_PARITY_ERROR); 1633 } else 1634 spc_sched_msgout(sc, SEND_INIT_DET_ERR); 1635 } 1636 1637 /* 1638 * If we're not already busy doing something test for the following 1639 * conditions: 1640 * 1) We have been reselected by something 1641 * 2) We have selected something successfully 1642 * 3) Our selection process has timed out 1643 * 4) This is really a bus free interrupt just to get a new command 1644 * going? 1645 * 5) Spurious interrupt? 1646 */ 1647 switch (sc->sc_state) { 1648 case SPC_IDLE: 1649 case SPC_SELECTING: 1650 SPC_MISC(("ints:0x%02x ", ints)); 1651 1652 if ((ints & INTS_SEL) != 0) { 1653 /* 1654 * We don't currently support target mode. 1655 */ 1656 printf("%s: target mode selected; going to BUS FREE\n", 1657 sc->sc_dev.dv_xname); 1658 1659 goto sched; 1660 } else if ((ints & INTS_RESEL) != 0) { 1661 SPC_MISC(("reselected ")); 1662 1663 /* 1664 * If we're trying to select a target ourselves, 1665 * push our command back into the ready list. 1666 */ 1667 if (sc->sc_state == SPC_SELECTING) { 1668 SPC_MISC(("backoff selector ")); 1669 SPC_ASSERT(sc->sc_nexus != NULL); 1670 acb = sc->sc_nexus; 1671 sc->sc_nexus = NULL; 1672 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 1673 } 1674 1675 /* Save reselection ID. */ 1676 sc->sc_selid = bus_space_read_1(iot, ioh, TEMP); 1677 1678 sc->sc_state = SPC_RESELECTED; 1679 } else if ((ints & INTS_CMD_DONE) != 0) { 1680 SPC_MISC(("selected ")); 1681 1682 /* 1683 * We have selected a target. Things to do: 1684 * a) Determine what message(s) to send. 1685 * b) Verify that we're still selecting the target. 1686 * c) Mark device as busy. 1687 */ 1688 if (sc->sc_state != SPC_SELECTING) { 1689 printf("%s: selection out while idle; " 1690 "resetting\n", sc->sc_dev.dv_xname); 1691 SPC_BREAK(); 1692 goto reset; 1693 } 1694 SPC_ASSERT(sc->sc_nexus != NULL); 1695 acb = sc->sc_nexus; 1696 sc_link = acb->xs->sc_link; 1697 ti = &sc->sc_tinfo[sc_link->target]; 1698 1699 sc->sc_msgpriq = SEND_IDENTIFY; 1700 if (acb->flags & ACB_RESET) 1701 sc->sc_msgpriq |= SEND_DEV_RESET; 1702 else if (acb->flags & ACB_ABORT) 1703 sc->sc_msgpriq |= SEND_ABORT; 1704 else { 1705 #if SPC_USE_SYNCHRONOUS 1706 if ((ti->flags & DO_SYNC) != 0) 1707 sc->sc_msgpriq |= SEND_SDTR; 1708 #endif 1709 #if SPC_USE_WIDE 1710 if ((ti->flags & DO_WIDE) != 0) 1711 sc->sc_msgpriq |= SEND_WDTR; 1712 #endif 1713 } 1714 1715 acb->flags |= ACB_NEXUS; 1716 ti->lubusy |= (1 << sc_link->lun); 1717 1718 /* Do an implicit RESTORE POINTERS. */ 1719 sc->sc_dp = acb->data_addr; 1720 sc->sc_dleft = acb->data_length; 1721 sc->sc_cp = (u_char *)&acb->scsi_cmd; 1722 sc->sc_cleft = acb->scsi_cmd_length; 1723 1724 /* On our first connection, schedule a timeout. */ 1725 if ((acb->xs->flags & SCSI_POLL) == 0) 1726 timeout_add_msec(&acb->xs->stimeout, 1727 acb->timeout); 1728 sc->sc_state = SPC_CONNECTED; 1729 } else if ((ints & INTS_TIMEOUT) != 0) { 1730 SPC_MISC(("selection timeout ")); 1731 1732 if (sc->sc_state != SPC_SELECTING) { 1733 printf("%s: selection timeout while idle; " 1734 "resetting\n", sc->sc_dev.dv_xname); 1735 SPC_BREAK(); 1736 goto reset; 1737 } 1738 SPC_ASSERT(sc->sc_nexus != NULL); 1739 acb = sc->sc_nexus; 1740 1741 delay(250); 1742 1743 acb->xs->error = XS_SELTIMEOUT; 1744 goto finish; 1745 } else { 1746 if (sc->sc_state != SPC_IDLE) { 1747 printf("%s: BUS FREE while not idle; " 1748 "state=%d\n", 1749 sc->sc_dev.dv_xname, sc->sc_state); 1750 SPC_BREAK(); 1751 goto out; 1752 } 1753 1754 goto sched; 1755 } 1756 1757 /* 1758 * Turn off selection stuff, and prepare to catch bus free 1759 * interrupts, parity errors, and phase changes. 1760 */ 1761 1762 sc->sc_flags = 0; 1763 sc->sc_prevphase = PH_INVALID; 1764 goto dophase; 1765 } 1766 1767 if ((ints & INTS_DISCON) != 0) { 1768 /* disable disconnect interrupt */ 1769 bus_space_write_1(iot, ioh, PCTL, 1770 bus_space_read_1(iot, ioh, PCTL) & ~PCTL_BFINT_ENAB); 1771 /* XXX reset interrupt */ 1772 bus_space_write_1(iot, ioh, INTS, ints); 1773 1774 switch (sc->sc_state) { 1775 case SPC_RESELECTED: 1776 goto sched; 1777 1778 case SPC_CONNECTED: 1779 SPC_ASSERT(sc->sc_nexus != NULL); 1780 acb = sc->sc_nexus; 1781 1782 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE 1783 if (sc->sc_prevphase == PH_MSGOUT) { 1784 /* 1785 * If the target went to BUS FREE phase during 1786 * or immediately after sending a SDTR or WDTR 1787 * message, disable negotiation. 1788 */ 1789 sc_link = acb->xs->sc_link; 1790 ti = &sc->sc_tinfo[sc_link->target]; 1791 switch (sc->sc_lastmsg) { 1792 #if SPC_USE_SYNCHRONOUS 1793 case SEND_SDTR: 1794 ti->flags &= ~DO_SYNC; 1795 ti->period = ti->offset = 0; 1796 break; 1797 #endif 1798 #if SPC_USE_WIDE 1799 case SEND_WDTR: 1800 ti->flags &= ~DO_WIDE; 1801 ti->width = 0; 1802 break; 1803 #endif 1804 } 1805 } 1806 #endif 1807 1808 if ((sc->sc_flags & SPC_ABORTING) == 0) { 1809 /* 1810 * Section 5.1.1 of the SCSI 2 spec suggests 1811 * issuing a REQUEST SENSE following an 1812 * unexpected disconnect. Some devices go into 1813 * a contingent allegiance condition when 1814 * disconnecting, and this is necessary to 1815 * clean up their state. 1816 */ 1817 printf("%s: unexpected disconnect; " 1818 "sending REQUEST SENSE\n", 1819 sc->sc_dev.dv_xname); 1820 SPC_BREAK(); 1821 spc_sense(sc, acb); 1822 goto out; 1823 } 1824 1825 acb->xs->error = XS_DRIVER_STUFFUP; 1826 goto finish; 1827 1828 case SPC_DISCONNECT: 1829 SPC_ASSERT(sc->sc_nexus != NULL); 1830 acb = sc->sc_nexus; 1831 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1832 sc->sc_nexus = NULL; 1833 goto sched; 1834 1835 case SPC_CMDCOMPLETE: 1836 SPC_ASSERT(sc->sc_nexus != NULL); 1837 acb = sc->sc_nexus; 1838 goto finish; 1839 } 1840 } 1841 else if ((ints & INTS_CMD_DONE) != 0 && 1842 sc->sc_prevphase == PH_MSGIN && sc->sc_state != SPC_CONNECTED) 1843 goto out; 1844 1845 dophase: 1846 #if 0 1847 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) { 1848 /* Wait for REQINIT. */ 1849 goto out; 1850 } 1851 #else 1852 bus_space_write_1(iot, ioh, INTS, ints); 1853 ints = 0; 1854 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) 1855 breathe(); /* need timeout XXX */ 1856 #endif 1857 1858 /* 1859 * State transition. 1860 */ 1861 sc->sc_phase = bus_space_read_1(iot, ioh, PSNS) & PH_MASK; 1862 #if 0 1863 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase); 1864 #endif 1865 1866 SPC_MISC(("phase=%d\n", sc->sc_phase)); 1867 switch (sc->sc_phase) { 1868 case PH_MSGOUT: 1869 if (sc->sc_state != SPC_CONNECTED && 1870 sc->sc_state != SPC_RESELECTED) 1871 break; 1872 spc_msgout(sc); 1873 sc->sc_prevphase = PH_MSGOUT; 1874 goto loop; 1875 1876 case PH_MSGIN: 1877 if (sc->sc_state != SPC_CONNECTED && 1878 sc->sc_state != SPC_RESELECTED) 1879 break; 1880 spc_msgin(sc); 1881 sc->sc_prevphase = PH_MSGIN; 1882 goto loop; 1883 1884 case PH_CMD: 1885 if (sc->sc_state != SPC_CONNECTED) 1886 break; 1887 #ifdef SPC_DEBUG 1888 if ((spc_debug & SPC_SHOWMISC) != 0) { 1889 SPC_ASSERT(sc->sc_nexus != NULL); 1890 acb = sc->sc_nexus; 1891 printf("cmd=0x%02x+%d ", 1892 acb->scsi_cmd.opcode, acb->scsi_cmd_length - 1); 1893 } 1894 #endif 1895 n = spc_dataout_pio(sc, sc->sc_cp, sc->sc_cleft); 1896 sc->sc_cp += n; 1897 sc->sc_cleft -= n; 1898 sc->sc_prevphase = PH_CMD; 1899 goto loop; 1900 1901 case PH_DATAOUT: 1902 if (sc->sc_state != SPC_CONNECTED) 1903 break; 1904 SPC_MISC(("dataout dleft=%d ", sc->sc_dleft)); 1905 n = spc_dataout_pio(sc, sc->sc_dp, sc->sc_dleft); 1906 sc->sc_dp += n; 1907 sc->sc_dleft -= n; 1908 sc->sc_prevphase = PH_DATAOUT; 1909 goto loop; 1910 1911 case PH_DATAIN: 1912 if (sc->sc_state != SPC_CONNECTED) 1913 break; 1914 SPC_MISC(("datain ")); 1915 n = spc_datain_pio(sc, sc->sc_dp, sc->sc_dleft); 1916 sc->sc_dp += n; 1917 sc->sc_dleft -= n; 1918 sc->sc_prevphase = PH_DATAIN; 1919 goto loop; 1920 1921 case PH_STAT: 1922 if (sc->sc_state != SPC_CONNECTED) 1923 break; 1924 SPC_ASSERT(sc->sc_nexus != NULL); 1925 acb = sc->sc_nexus; 1926 /*acb->target_stat = bus_space_read_1(iot, ioh, DREG);*/ 1927 spc_datain_pio(sc, &acb->target_stat, 1); 1928 SPC_MISC(("target_stat=0x%02x ", acb->target_stat)); 1929 sc->sc_prevphase = PH_STAT; 1930 goto loop; 1931 } 1932 1933 printf("%s: unexpected bus phase; resetting\n", sc->sc_dev.dv_xname); 1934 SPC_BREAK(); 1935 reset: 1936 spc_init(sc); 1937 return 1; 1938 1939 finish: 1940 timeout_del(&acb->xs->stimeout); 1941 bus_space_write_1(iot, ioh, INTS, ints); 1942 ints = 0; 1943 spc_done(sc, acb); 1944 goto out; 1945 1946 sched: 1947 sc->sc_state = SPC_IDLE; 1948 spc_sched(sc); 1949 goto out; 1950 1951 out: 1952 if (ints) 1953 bus_space_write_1(iot, ioh, INTS, ints); 1954 bus_space_write_1(iot, ioh, SCTL, 1955 bus_space_read_1(iot, ioh, SCTL) | SCTL_INTR_ENAB); 1956 return 1; 1957 } 1958 1959 void 1960 spc_abort(struct spc_softc *sc, struct spc_acb *acb) 1961 { 1962 1963 /* 2 secs for the abort */ 1964 acb->timeout = SPC_ABORT_TIMEOUT; 1965 acb->flags |= ACB_ABORT; 1966 1967 if (acb == sc->sc_nexus) { 1968 /* 1969 * If we're still selecting, the message will be scheduled 1970 * after selection is complete. 1971 */ 1972 if (sc->sc_state == SPC_CONNECTED) 1973 spc_sched_msgout(sc, SEND_ABORT); 1974 } else { 1975 spc_dequeue(sc, acb); 1976 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 1977 if (sc->sc_state == SPC_IDLE) 1978 spc_sched(sc); 1979 } 1980 } 1981 1982 void 1983 spc_timeout(void *arg) 1984 { 1985 struct spc_acb *acb = arg; 1986 struct scsi_xfer *xs = acb->xs; 1987 struct scsi_link *sc_link = xs->sc_link; 1988 struct spc_softc *sc = sc_link->bus->sb_adapter_softc; 1989 int s; 1990 1991 sc_print_addr(sc_link); 1992 printf("timed out"); 1993 1994 s = splbio(); 1995 1996 if (acb->flags & ACB_ABORT) { 1997 /* abort timed out */ 1998 printf(" AGAIN\n"); 1999 /* XXX Must reset! */ 2000 } else { 2001 /* abort the operation that has timed out */ 2002 printf("\n"); 2003 acb->xs->error = XS_TIMEOUT; 2004 spc_abort(sc, acb); 2005 } 2006 2007 splx(s); 2008 } 2009 2010 #ifdef SPC_DEBUG 2011 /* 2012 * The following functions are mostly used for debugging purposes, either 2013 * directly called from the driver or from the kernel debugger. 2014 */ 2015 2016 void 2017 spc_show_scsi_cmd(spc_acb *acb) 2018 { 2019 u_char *b = (u_char *)&acb->scsi_cmd; 2020 struct scsi_link *sc_link = acb->xs->sc_link; 2021 int i; 2022 2023 sc_print_addr(sc_link); 2024 if ((acb->xs->flags & SCSI_RESET) == 0) { 2025 for (i = 0; i < acb->scsi_cmd_length; i++) { 2026 if (i) 2027 printf(","); 2028 printf("%x", b[i]); 2029 } 2030 printf("\n"); 2031 } else 2032 printf("RESET\n"); 2033 } 2034 2035 void 2036 spc_print_acb(spc_acb *acb) 2037 { 2038 2039 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2040 printf(" dp=%p dleft=%d target_stat=%x\n", 2041 acb->data_addr, acb->data_length, acb->target_stat); 2042 spc_show_scsi_cmd(acb); 2043 } 2044 2045 void 2046 spc_print_active_acb() 2047 { 2048 struct spc_acb *acb; 2049 struct spc_softc *sc = spc_cd.cd_devs[0]; /* XXX */ 2050 2051 printf("ready list:\n"); 2052 TAILQ_FOREACH(acb, &sc->ready_list, chain) 2053 spc_print_acb(acb); 2054 printf("nexus:\n"); 2055 if (sc->sc_nexus != NULL) 2056 spc_print_acb(sc->sc_nexus); 2057 printf("nexus list:\n"); 2058 TAILQ_FOREACH(acb, &sc->nexus_list, chain) 2059 spc_print_acb(acb); 2060 } 2061 2062 void 2063 spc_dump89352(struct spc_softc *sc) 2064 { 2065 bus_space_tag_t iot = sc->sc_iot; 2066 bus_space_handle_t ioh = sc->sc_ioh; 2067 2068 printf("mb89352: BDID=%x SCTL=%x SCMD=%x TMOD=%x\n", 2069 bus_space_read_1(iot, ioh, BDID), 2070 bus_space_read_1(iot, ioh, SCTL), 2071 bus_space_read_1(iot, ioh, SCMD), 2072 bus_space_read_1(iot, ioh, TMOD)); 2073 printf(" INTS=%x PSNS=%x SSTS=%x SERR=%x PCTL=%x\n", 2074 bus_space_read_1(iot, ioh, INTS), 2075 bus_space_read_1(iot, ioh, PSNS), 2076 bus_space_read_1(iot, ioh, SSTS), 2077 bus_space_read_1(iot, ioh, SERR), 2078 bus_space_read_1(iot, ioh, PCTL)); 2079 printf(" MBC=%x DREG=%x TEMP=%x TCH=%x TCM=%x\n", 2080 bus_space_read_1(iot, ioh, MBC), 2081 #if 0 2082 bus_space_read_1(iot, ioh, DREG), 2083 #else 2084 0, 2085 #endif 2086 bus_space_read_1(iot, ioh, TEMP), 2087 bus_space_read_1(iot, ioh, TCH), 2088 bus_space_read_1(iot, ioh, TCM)); 2089 printf(" TCL=%x EXBF=%x\n", 2090 bus_space_read_1(iot, ioh, TCL), 2091 bus_space_read_1(iot, ioh, EXBF)); 2092 } 2093 2094 void 2095 spc_dump_driver(struct spc_softc *sc) 2096 { 2097 struct spc_tinfo *ti; 2098 int i; 2099 2100 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2101 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x " 2102 "currmsg=%x\n", sc->sc_state, sc->sc_imess[0], 2103 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2104 for (i = 0; i < 7; i++) { 2105 ti = &sc->sc_tinfo[i]; 2106 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2107 i, ti->cmds, ti->dconns, ti->touts); 2108 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2109 } 2110 } 2111 #endif 2112