1 /* $OpenBSD: board.h,v 1.15 2017/11/03 06:55:08 aoyama Exp $ */ 2 /* 3 * Mach Operating System 4 * Copyright (c) 1993-1991 Carnegie Mellon University 5 * Copyright (c) 1991 OMRON Corporation 6 * All Rights Reserved. 7 * 8 * Permission to use, copy, modify and distribute this software and its 9 * documentation is hereby granted, provided that both the copyright 10 * notice and this permission notice appear in all copies of the 11 * software, derivative works or modified versions, and any portions 12 * thereof, and that both notices appear in supporting documentation. 13 * 14 * CARNEGIE MELLON AND OMRON ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS IS" 15 * CONDITION. CARNEGIE MELLON AND OMRON DISCLAIM ANY LIABILITY OF ANY KIND 16 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 17 * 18 * Carnegie Mellon requests users of this software to return to 19 * 20 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 21 * School of Computer Science 22 * Carnegie Mellon University 23 * Pittsburgh PA 15213-3890 24 * 25 * any improvements or extensions that they make and grant Carnegie the 26 * rights to redistribute these changes. 27 */ 28 29 #ifndef _MACHINE_BOARD_H_ 30 #define _MACHINE_BOARD_H_ 31 32 /* 33 * OMRON SX9100DT CPU board constants 34 */ 35 36 /* 37 * Something to put append a 'U' to a long constant if it's C so that 38 * it'll be unsigned in both ANSI and traditional. 39 */ 40 #if defined(_LOCORE) 41 #define U(num) num 42 #elif defined(__STDC__) 43 #define U(num) num ## U 44 #else 45 #define U(num) num/**/U 46 #endif 47 48 /* machtype values */ 49 #define LUNA_88K 0x1 50 #define LUNA_88K2 0x2 51 52 #define MAXPHYSMEM U(0x10000000) /* max physical memory */ 53 54 #define PROM_ADDR U(0x41000000) /* PROM */ 55 #define PROM_SPACE U(0x00040000) 56 #define NVRAM_ADDR U(0x45000000) /* Non Volatile */ 57 #define NVRAM_SPACE U(0x00001FDC) 58 #define FUSE_ROM_ADDR U(0x43000000) /* FUSE_ROM */ 59 #define FUSE_ROM_SPACE 1024 60 #define OBIO_CAL_CTL U(0x45001FE0) /* calendar control register */ 61 #define OBIO_CAL_SEC U(0x45001FE4) /* seconds */ 62 #define OBIO_CAL_MIN U(0x45001FE8) /* minutes */ 63 #define OBIO_CAL_HOUR U(0x45001FEC) /* hours */ 64 #define OBIO_CAL_DOW U(0x45001FF0) /* Day Of the Week */ 65 #define OBIO_CAL_DAY U(0x45001FF4) /* days */ 66 #define OBIO_CAL_MON U(0x45001FF8) /* months */ 67 #define OBIO_CAL_YEAR U(0x45001FFC) /* years */ 68 #define NVRAM_ADDR_88K2 U(0x47000000) /* Non Volatile RAM area for LUNA-88K2 */ 69 #define OBIO_PIO0_BASE U(0x49000000) /* PIO-0 */ 70 #define OBIO_PIO0_SPACE U(0x0000000C) 71 #define OBIO_PIO0A U(0x49000000) /* PIO-0 port A */ 72 #define OBIO_PIO0B U(0x49000004) /* PIO-0 port B */ 73 #define OBIO_PIO0C U(0x49000008) /* PIO-0 port C*/ 74 #define OBIO_PIO0 U(0x4900000C) /* PIO-0 control */ 75 #define OBIO_PIO1_BASE U(0x4D000000) /* PIO-1 */ 76 #define OBIO_PIO1_SPACE U(0x0000000C) 77 #define OBIO_PIO1A U(0x4D000000) /* PIO-1 port A */ 78 #define OBIO_PIO1B U(0x4D000004) /* PIO-1 port B */ 79 #define OBIO_PIO1C U(0x4D000008) /* PIO-1 port C*/ 80 #define OBIO_PIO1 U(0x4D00000C) /* PIO-1 control */ 81 #define OBIO_SIO U(0x51000000) /* SIO */ 82 #define OBIO_TAS U(0x61000000) /* TAS register */ 83 #define OBIO_CLOCK0 U(0x63000000) /* system clock CPU 0 */ 84 #define OBIO_CLOCK1 U(0x63000004) /* system clock CPU 1 */ 85 #define OBIO_CLOCK2 U(0x63000008) /* system clock CPU 2 */ 86 #define OBIO_CLOCK3 U(0x6300000C) /* system clock CPU 3 */ 87 #define OBIO_CLK_INTR 31 /* system clock interrupt flag */ 88 #define INT_ST_MASK0 U(0x65000000) /* interrupt status register CPU 0 */ 89 #define INT_ST_MASK1 U(0x65000004) /* interrupt status register CPU 1 */ 90 #define INT_ST_MASK2 U(0x65000008) /* interrupt status register CPU 2 */ 91 #define INT_ST_MASK3 U(0x6500000C) /* interrupt status register CPU 3 */ 92 #define INT_LEVEL 8 /* # of interrupt level + 1 */ 93 #define INT_SET_LV7 U(0x00000000) /* disable interrupts */ 94 #define INT_SET_LV6 U(0x00000000) /* enable level 7 */ 95 #define INT_SET_LV5 U(0x84000000) /* enable level 7-6 */ 96 #define INT_SET_LV4 U(0xC4000000) /* enable level 7-5 */ 97 #define INT_SET_LV3 U(0xE4000000) /* enable level 7-4 */ 98 #define INT_SET_LV2 U(0xF4000000) /* enable level 7-3 */ 99 #define INT_SET_LV1 U(0xFC000000) /* enable level 7-2 */ 100 #define INT_SET_LV0 U(0xFC000000) /* enable interrupts */ 101 #define INT_SLAVE_MASK U(0x84000000) /* slave can only enable 6 and 1 */ 102 103 #define SOFT_INT0 U(0x69000000) /* software interrupt CPU 0 */ 104 #define SOFT_INT1 U(0x69000004) /* software interrupt CPU 1 */ 105 #define SOFT_INT2 U(0x69000008) /* software interrupt CPU 2 */ 106 #define SOFT_INT3 U(0x6900000C) /* software interrupt CPU 3 */ 107 #define SOFT_INT_FLAG0 U(0x6B000000) /* software interrupt flag CPU 0 */ 108 #define SOFT_INT_FLAG1 U(0x6B000000) /* software interrupt flag CPU 1 */ 109 #define SOFT_INT_FLAG2 U(0x6B000000) /* software interrupt flag CPU 2 */ 110 #define SOFT_INT_FLAG3 U(0x6B000000) /* software interrupt flag CPU 3 */ 111 #define RESET_CPU0 U(0x6D000000) /* reset CPU 0 */ 112 #define RESET_CPU1 U(0x6D000004) /* reset CPU 1 */ 113 #define RESET_CPU2 U(0x6D000008) /* reset CPU 2 */ 114 #define RESET_CPU3 U(0x6D00000C) /* reset CPU 3 */ 115 #define RESET_CPU_ALL U(0x6D000010) /* reset ALL CPUs */ 116 #define TRI_PORT_RAM U(0x71000000) /* 3 port RAM */ 117 #define TRI_PORT_RAM_SPACE 0x20000 118 #define EXT_A_ADDR U(0x81000000) /* extension board A */ 119 #define EXT_A_SPACE U(0x02000000) 120 #define EXT_B_ADDR U(0x83000000) /* extension board B */ 121 #define EXT_B_SPACE U(0x01000000) 122 #define PC_BASE U(0x90000000) /* pc-98 extension board */ 123 #define PC_SPACE U(0x02000000) 124 125 #define MROM_ADDR U(0xA1000000) /* Mask ROM address */ 126 #define MROM_SPACE 0x400000 127 #define BMAP_START U(0xB1000000) /* Bitmap start address */ 128 #define BMAP_SPACE (BMAP_END - BMAP_START) 129 #define BMAP_RFCNT U(0xB1000000) /* RFCNT register */ 130 #define BMAP_BMSEL U(0xB1040000) /* BMSEL register */ 131 #define BMAP_BMP U(0xB1080000) /* common bitmap plane */ 132 #define BMAP_BMAP0 U(0xB10C0000) /* bitmap plane 0 */ 133 #define BMAP_BMAP1 U(0xB1100000) /* bitmap plane 1 */ 134 #define BMAP_BMAP2 U(0xB1140000) /* bitmap plane 2 */ 135 #define BMAP_BMAP3 U(0xB1180000) /* bitmap plane 3 */ 136 #define BMAP_BMAP4 U(0xB11C0000) /* bitmap plane 4 */ 137 #define BMAP_BMAP5 U(0xB1200000) /* bitmap plane 5 */ 138 #define BMAP_BMAP6 U(0xB1240000) /* bitmap plane 6 */ 139 #define BMAP_BMAP7 U(0xB1280000) /* bitmap plane 7 */ 140 #define BMAP_FN U(0xB12C0000) /* common bitmap function */ 141 #define BMAP_FN0 U(0xB1300000) /* bitmap function 0 */ 142 #define BMAP_FN1 U(0xB1340000) /* bitmap function 1 */ 143 #define BMAP_FN2 U(0xB1380000) /* bitmap function 2 */ 144 #define BMAP_FN3 U(0xB13C0000) /* bitmap function 3 */ 145 #define BMAP_FN4 U(0xB1400000) /* bitmap function 4 */ 146 #define BMAP_FN5 U(0xB1440000) /* bitmap function 5 */ 147 #define BMAP_FN6 U(0xB1480000) /* bitmap function 6 */ 148 #define BMAP_FN7 U(0xB14C0000) /* bitmap function 7 */ 149 #define BMAP_END U(0xB1500000) 150 #define BMAP_END24P U(0xB1800000) /* end of 24p framemem */ 151 #define BMAP_PALLET0 U(0xC0000000) /* color pallet */ 152 #define BMAP_PALLET1 U(0xC1000000) /* color pallet */ 153 #define BMAP_PALLET2 U(0xC1100000) /* color pallet */ 154 #define BOARD_CHECK_REG U(0xD0000000) /* board check register */ 155 #define BMAP_CRTC U(0xD1000000) /* CRTC-II */ 156 #define BMAP_IDENTROM U(0xD1800000) /* bitmap-board identify ROM */ 157 #define SCSI_ADDR U(0xE1000000) /* SCSI address */ 158 #define LANCE_ADDR U(0xF1000000) /* LANCE */ 159 160 #define CMMU_I0 U(0xFFF07000) /* CMMU instruction cpu 0 */ 161 #define CMMU_D0 U(0xFFF06000) /* CMMU data cpu 0 */ 162 #define CMMU_I1 U(0xFFF05000) /* CMMU instruction cpu 1 */ 163 #define CMMU_D1 U(0xFFF04000) /* CMMU data cpu 1 */ 164 #define CMMU_I2 U(0xFFF03000) /* CMMU instruction cpu 2 */ 165 #define CMMU_D2 U(0xFFF02000) /* CMMU data cpu 2 */ 166 #define CMMU_I3 U(0xFFF01000) /* CMMU instruction cpu 3 */ 167 #define CMMU_D3 U(0xFFF00000) /* CMMU data cpu 3 */ 168 169 #endif /* _MACHINE_BOARD_H_ */ 170