1 /* $OpenBSD: sioreg.h,v 1.1 2013/10/28 22:13:13 miod Exp $ */ 2 /* $NetBSD: sioreg.h,v 1.2 2013/01/12 07:04:57 tsutsui Exp $ */ 3 4 /* 5 * Copyright (c) 1992 OMRON Corporation. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * OMRON Corporation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)sioreg.h 8.1 (Berkeley) 6/10/93 39 */ 40 /* 41 * Copyright (c) 1992, 1993 42 * The Regents of the University of California. All rights reserved. 43 * 44 * This code is derived from software contributed to Berkeley by 45 * OMRON Corporation. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)sioreg.h 8.1 (Berkeley) 6/10/93 72 */ 73 74 /* sioreg.h NOV-26-1991 */ 75 76 struct siodevice { 77 volatile u_char sio_data; 78 u_char sio_pad1[3]; 79 volatile u_char sio_cmd; 80 u_char sio_pad2[3]; 81 }; 82 83 #define sio_stat sio_cmd 84 85 #define REG(u, r) ( (u << 4) | r ) 86 #define CHANNEL(r) ( r >> 4 ) 87 #define REGNO(r) ( r & 0x07 ) 88 #define isStatusReg(r) ( r & 0x08 ) 89 90 #define WR0 0x00 91 #define WR1 0x01 92 #define WR2 0x02 93 #define WR3 0x03 94 #define WR4 0x04 95 #define WR5 0x05 96 #define WR6 0x06 97 #define WR7 0x07 98 99 #define WR2A 0x02 100 #define WR2B 0x12 101 102 #define RR0 0x08 103 #define RR1 0x09 104 #define RR2 0x0A 105 #define RR3 0x0B 106 #define RR4 0x0C 107 108 #define RR2A 0x0A 109 #define RR2B 0x1A 110 111 #define WR0_NOP 0x00 /* No Operation */ 112 #define WR0_SNDABRT 0x08 /* Send Abort (HDLC) */ 113 #define WR0_RSTINT 0x10 /* Reset External/Status Interrupt */ 114 #define WR0_CHANRST 0x18 /* Channel Reset */ 115 #define WR0_INTNXT 0x20 /* Enable Interrupt on Next Receive Character */ 116 #define WR0_RSTPEND 0x28 /* Reset Transmitter Interrput/DMA Pending */ 117 #define WR0_ERRRST 0x30 /* Error Reset */ 118 #define WR0_ENDINTR 0x38 /* End of Interrupt */ 119 120 #define WR1_ESENBL 0x01 /* External/Status Interrupt Enable */ 121 #define WR1_TXENBL 0x02 /* Tx Interrupt/DMA Enable */ 122 #define WR1_STATVEC 0x04 /* Status Affects Vector (Only Chan-B) */ 123 #define WR1_RXDSEBL 0x00 /* Rx Interrupt/DMA Disable */ 124 #define WR1_RXFIRST 0x08 /* Interrupt only First Character Received */ 125 #define WR1_RXALLS 0x10 /* Interrupt Every Characters Received (with Special Char.) */ 126 #define WR1_RXALL 0x18 /* Interrupt Every Characters Received (without Special Char.) */ 127 128 #define WR2_INTR_0 0x00 /* Interrupt Priority: RxA TxA RxB TxB E/SA E/SA */ 129 #define WR2_INTR_1 0x04 /* Interrupt Priority: RxA RxB TxA TxB E/SA E/SA */ 130 #define WR2_VEC85_1 0x00 /* 8085 Vectored Mode - 1 */ 131 #define WR2_VEC85_2 0x08 /* 8085 Vectored Mode - 2 */ 132 #define WR2_VEC86 0x10 /* 8086 Vectored */ 133 #define WR2_VEC85_3 0x18 /* 8085 Vectored Mode - 3 */ 134 135 #define WR3_RXENBL 0x01 /* Rx Enable */ 136 #define WR3_RXCRC 0x08 /* Rx CRC Check */ 137 #define WR3_AUTOEBL 0x20 /* Auto Enable (flow control for MODEM) */ 138 #define WR3_RX5BIT 0x00 /* Rx Bits/Character: 5 Bits */ 139 #define WR3_RX7BIT 0x40 /* Rx Bits/Character: 7 Bits */ 140 #define WR3_RX6BIT 0x80 /* Rx Bits/Character: 6 Bits */ 141 #define WR3_RX8BIT 0xc0 /* Rx Bits/Character: 8 Bits */ 142 143 #define WR4_NPARITY 0x00 /* No Parity */ 144 #define WR4_OPARITY 0x01 /* Parity Odd */ 145 #define WR4_EPARITY 0x02 /* Parity Even */ 146 #define WR4_STOP1 0x04 /* Stop Bits (1bit) */ 147 #define WR4_STOP15 0x08 /* Stop Bits (1.5bit) */ 148 #define WR4_STOP2 0x0c /* Stop Bits (2bit) */ 149 #define WR4_BAUD96 0x40 /* Clock Rate (9600 BAUD) */ 150 #define WR4_BAUD48 0x80 /* Clock Rate (4800 BAUD) */ 151 #define WR4_BAUD24 0xc0 /* Clock Rate (2400 BAUD) */ 152 153 #define WR5_TXCRC 0x01 /* Tx CRC Check */ 154 #define WR5_RTS 0x02 /* Request To Send [RTS] */ 155 #define WR5_TXENBL 0x08 /* Transmit Enable */ 156 #define WR5_BREAK 0x10 /* Send Break */ 157 #define WR5_TX5BIT 0x00 /* Tx Bits/Character: 5 Bits */ 158 #define WR5_TX7BIT 0x20 /* Tx Bits/Character: 7 Bits */ 159 #define WR5_TX6BIT 0x40 /* Tx Bits/Character: 6 Bits */ 160 #define WR5_TX8BIT 0x60 /* Tx Bits/Character: 8 Bits */ 161 #define WR5_DTR 0x80 /* Data Terminal Ready [DTR] */ 162 163 #define RR0_RXAVAIL 0x01 /* Rx Character Available */ 164 #define RR0_INTRPEND 0x02 /* Interrupt Pending (Channel-A Only) */ 165 #define RR0_TXEMPTY 0x04 /* Tx Buffer Empty */ 166 #define RR0_BREAK 0x80 /* Break Detected */ 167 168 #define RR1_PARITY 0x10 /* Parity Error */ 169 #define RR1_OVERRUN 0x20 /* Data Over Run */ 170 #define RR1_FRAMING 0x40 /* Framing Error */ 171