1 /* $OpenBSD: asm.h,v 1.16 2022/12/06 18:50:59 guenther Exp $ */ 2 3 /* 4 * Mach Operating System 5 * Copyright (c) 1993-1992 Carnegie Mellon University 6 * Copyright (c) 1991 OMRON Corporation 7 * All Rights Reserved. 8 * 9 * Permission to use, copy, modify and distribute this software and its 10 * documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON AND OMRON ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON AND OMRON DISCLAIM ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #ifndef _M88K_ASM_H_ 31 #define _M88K_ASM_H_ 32 33 #define _C_LABEL(name) name 34 #define _ASM_LABEL(name) name 35 36 #define _ENTRY(name) \ 37 .text; .align 3; .globl name; .type name,@function; name: 38 39 #define ENTRY(name) _ENTRY(name) 40 #define ASENTRY(name) _ENTRY(name) 41 42 #define END(name) \ 43 .size name,.-name 44 45 #define GLOBAL(name) \ 46 .globl name; name: 47 48 #define ASGLOBAL(name) \ 49 .globl name; name: 50 51 #define LOCAL(name) \ 52 name: 53 54 #define ASLOCAL(name) \ 55 name: 56 57 #define BSS(name, size) \ 58 .comm name, size 59 60 #define ASBSS(name, size) \ 61 .comm name, size 62 63 #define STRONG_ALIAS(alias,sym) \ 64 .global alias; \ 65 alias = sym 66 #define WEAK_ALIAS(alias,sym) \ 67 .weak alias; \ 68 alias = sym 69 70 #ifdef _KERNEL 71 72 #ifdef _LOCORE 73 74 /* 75 * Control register symbolic names 76 */ 77 78 #define PID %cr0 79 #define PSR %cr1 80 #define EPSR %cr2 81 #define SSBR %cr3 82 #define SXIP %cr4 /* 88100 */ 83 #define EXIP %cr4 /* 88110 */ 84 #define SNIP %cr5 /* 88100 */ 85 #define ENIP %cr5 /* 88110 */ 86 #define SFIP %cr6 /* 88100 */ 87 #define VBR %cr7 88 #define DMT0 %cr8 /* 88100 */ 89 #define DMD0 %cr9 /* 88100 */ 90 #define DMA0 %cr10 /* 88100 */ 91 #define DMT1 %cr11 /* 88100 */ 92 #define DMD1 %cr12 /* 88100 */ 93 #define DMA1 %cr13 /* 88100 */ 94 #define DMT2 %cr14 /* 88100 */ 95 #define DMD2 %cr15 /* 88100 */ 96 #define DMA2 %cr16 /* 88100 */ 97 #define SRX %cr16 /* 88110 */ 98 #define SR0 %cr17 99 #define SR1 %cr18 100 #define SR2 %cr19 101 #define SR3 %cr20 102 #define ICMD %cr25 /* 88110 */ 103 #define ICTL %cr26 /* 88110 */ 104 #define ISAR %cr27 /* 88110 */ 105 #define ISAP %cr28 /* 88110 */ 106 #define IUAP %cr29 /* 88110 */ 107 #define IIR %cr30 /* 88110 */ 108 #define IBP %cr31 /* 88110 */ 109 #define IPPU %cr32 /* 88110 */ 110 #define IPPL %cr33 /* 88110 */ 111 #define ISR %cr34 /* 88110 */ 112 #define ILAR %cr35 /* 88110 */ 113 #define IPAR %cr36 /* 88110 */ 114 #define DCMD %cr40 /* 88110 */ 115 #define DCTL %cr41 /* 88110 */ 116 #define DSAR %cr42 /* 88110 */ 117 #define DSAP %cr43 /* 88110 */ 118 #define DUAP %cr44 /* 88110 */ 119 #define DIR %cr45 /* 88110 */ 120 #define DBP %cr46 /* 88110 */ 121 #define DPPU %cr47 /* 88110 */ 122 #define DPPL %cr48 /* 88110 */ 123 #define DSR %cr49 /* 88110 */ 124 #define DLAR %cr50 /* 88110 */ 125 #define DPAR %cr51 /* 88110 */ 126 127 #define FPECR %fcr0 128 #define FPHS1 %fcr1 /* 88100 */ 129 #define FPLS1 %fcr2 /* 88100 */ 130 #define FPHS2 %fcr3 /* 88100 */ 131 #define FPLS2 %fcr4 /* 88100 */ 132 #define FPPT %fcr5 /* 88100 */ 133 #define FPRH %fcr6 /* 88100 */ 134 #define FPRL %fcr7 /* 88100 */ 135 #define FPIT %fcr8 /* 88100 */ 136 #define FPSR %fcr62 137 #define FPCR %fcr63 138 139 #define CPU SR0 140 141 /* 142 * At various times, there is the need to clear the pipeline (i.e. 143 * synchronize). A "tb1 0, r0, foo" will do that (because a trap 144 * instruction always synchronizes, and this particular instruction 145 * will never actually take the trap). 146 */ 147 #define FLUSH_PIPELINE tb1 0, %r0, 0 148 149 #define NOP or %r0, %r0, %r0 150 #define RTE NOP; rte 151 152 /* 153 * PSR bits 154 */ 155 #define PSR_SHADOW_FREEZE_BIT 0 156 #define PSR_INTERRUPT_DISABLE_BIT 1 157 #define PSR_FPU_DISABLE_BIT 3 158 #define PSR_GRAPHICS_DISABLE_BIT 4 /* SFU2 - MC88110 */ 159 #define PSR_SERIALIZE_BIT 25 /* MC88110 */ 160 #define PSR_CARRY_BIT 28 161 #define PSR_SERIAL_MODE_BIT 29 162 #define PSR_BIG_ENDIAN_MODE 30 163 #define PSR_SUPERVISOR_MODE_BIT 31 164 165 /* 166 * DMT0/DMT1/DMT2 bits 167 */ 168 #define DMT_VALID_BIT 0 169 #define DMT_WRITE_BIT 1 170 #define DMT_LOCK_BIT 12 171 #define DMT_DOUBLE_BIT 13 172 #define DMT_DAS_BIT 14 173 #define DMT_DREG_OFFSET 7 174 #define DMT_DREG_WIDTH 5 175 176 /* 177 * Status bits for an SXIP/SNIP/SFIP address. 178 */ 179 #define RTE_VALID_BIT 1 180 #define RTE_ERROR_BIT 0 181 182 #define VECTOR(x) \ 183 .word x 184 185 #endif /* _LOCORE */ 186 187 #endif /* _KERNEL */ 188 189 #endif /* _M88K_ASM_H_ */ 190