1*11b22cfdSmiod /* $OpenBSD: openpicreg.h,v 1.2 2007/01/07 13:39:28 miod Exp $ */ 2d9a5f17fSdrahn /* $NetBSD: openpicreg.h,v 1.1 2000/02/14 12:45:53 tsubai Exp $ */ 3d9a5f17fSdrahn 4d9a5f17fSdrahn /*- 5d9a5f17fSdrahn * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 6d9a5f17fSdrahn * 7d9a5f17fSdrahn * Redistribution and use in source and binary forms, with or without 8d9a5f17fSdrahn * modification, are permitted provided that the following conditions 9d9a5f17fSdrahn * are met: 10d9a5f17fSdrahn * 1. Redistributions of source code must retain the above copyright 11d9a5f17fSdrahn * notice, this list of conditions and the following disclaimer. 12d9a5f17fSdrahn * 2. Redistributions in binary form must reproduce the above copyright 13d9a5f17fSdrahn * notice, this list of conditions and the following disclaimer in the 14d9a5f17fSdrahn * documentation and/or other materials provided with the distribution. 15d9a5f17fSdrahn * 3. The name of the author may not be used to endorse or promote products 16d9a5f17fSdrahn * derived from this software without specific prior written permission. 17d9a5f17fSdrahn * 18d9a5f17fSdrahn * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19d9a5f17fSdrahn * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20d9a5f17fSdrahn * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21d9a5f17fSdrahn * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22d9a5f17fSdrahn * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23d9a5f17fSdrahn * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24d9a5f17fSdrahn * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25d9a5f17fSdrahn * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26d9a5f17fSdrahn * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27d9a5f17fSdrahn * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28d9a5f17fSdrahn */ 29d9a5f17fSdrahn 30d9a5f17fSdrahn /* 31d9a5f17fSdrahn * GLOBAL/TIMER register (IDU base + 0x1000) 32d9a5f17fSdrahn */ 33d9a5f17fSdrahn 34d9a5f17fSdrahn /* feature reporting reg 0 */ 35d9a5f17fSdrahn #define OPENPIC_FEATURE 0x1000 36d9a5f17fSdrahn 37d9a5f17fSdrahn /* global config reg 0 */ 38d9a5f17fSdrahn #define OPENPIC_CONFIG 0x1020 39d9a5f17fSdrahn #define OPENPIC_CONFIG_RESET 0x80000000 40d9a5f17fSdrahn #define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000 41d9a5f17fSdrahn 42d9a5f17fSdrahn /* vendor ID */ 43d9a5f17fSdrahn #define OPENPIC_VENDOR_ID 0x1080 44d9a5f17fSdrahn 45d9a5f17fSdrahn /* processor initialization reg */ 46d9a5f17fSdrahn #define OPENPIC_PROC_INIT 0x1090 47d9a5f17fSdrahn 48d9a5f17fSdrahn /* IPI vector/priority reg */ 49d9a5f17fSdrahn #define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10) 50d9a5f17fSdrahn 51d9a5f17fSdrahn /* spurious intr. vector */ 52d9a5f17fSdrahn #define OPENPIC_SPURIOUS_VECTOR 0x10e0 53d9a5f17fSdrahn 54d9a5f17fSdrahn 55d9a5f17fSdrahn /* 56d9a5f17fSdrahn * INTERRUPT SOURCE register (IDU base + 0x10000) 57d9a5f17fSdrahn */ 58d9a5f17fSdrahn 59d9a5f17fSdrahn /* interrupt vector/priority reg */ 60d9a5f17fSdrahn #define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20) 61d9a5f17fSdrahn #define OPENPIC_SENSE_LEVEL 0x00400000 62d9a5f17fSdrahn #define OPENPIC_SENSE_EDGE 0x00000000 63d9a5f17fSdrahn #define OPENPIC_POLARITY_POSITIVE 0x00800000 64d9a5f17fSdrahn #define OPENPIC_POLARITY_NEGATIVE 0x00000000 65d9a5f17fSdrahn #define OPENPIC_IMASK 0x80000000 66d9a5f17fSdrahn #define OPENPIC_ACTIVITY 0x40000000 67d9a5f17fSdrahn #define OPENPIC_PRIORITY_MASK 0x000f0000 68d9a5f17fSdrahn #define OPENPIC_PRIORITY_SHIFT 16 69d9a5f17fSdrahn #define OPENPIC_VECTOR_MASK 0x000000ff 70d9a5f17fSdrahn 71d9a5f17fSdrahn /* interrupt destination cpu */ 72d9a5f17fSdrahn #define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20) 73d9a5f17fSdrahn 74d9a5f17fSdrahn 75d9a5f17fSdrahn /* 76d9a5f17fSdrahn * PROCESSOR register (IDU base + 0x20000) 77d9a5f17fSdrahn */ 78d9a5f17fSdrahn 79d9a5f17fSdrahn /* IPI command reg */ 80*11b22cfdSmiod #define OPENPIC_IPI(cpu, ipi) (0x20040 + (cpu) * 0x1000 + (ipi) * 0x10) 81d9a5f17fSdrahn 82d9a5f17fSdrahn /* current task priority reg */ 83d9a5f17fSdrahn #define OPENPIC_CPU_PRIORITY(cpu) (0x20080 + (cpu) * 0x1000) 84d9a5f17fSdrahn #define OPENPIC_CPU_PRIORITY_MASK 0x0000000f 85d9a5f17fSdrahn 86d9a5f17fSdrahn /* interrupt acknowledge reg */ 87d9a5f17fSdrahn #define OPENPIC_IACK(cpu) (0x200a0 + (cpu) * 0x1000) 88d9a5f17fSdrahn 89d9a5f17fSdrahn /* end of interrupt reg */ 90d9a5f17fSdrahn #define OPENPIC_EOI(cpu) (0x200b0 + (cpu) * 0x1000) 91