1*f4fee9beSvisa /* $OpenBSD: cn30xxcorereg.h,v 1.2 2017/11/01 14:43:01 visa Exp $ */ 2d8671520Syasuoka 3d8671520Syasuoka /* 4d8671520Syasuoka * Copyright (c) 2014 YASUOKA Masahiko <yasuoka@openbsd.org> 5d8671520Syasuoka * 6d8671520Syasuoka * Permission to use, copy, modify, and distribute this software for any 7d8671520Syasuoka * purpose with or without fee is hereby granted, provided that the above 8d8671520Syasuoka * copyright notice and this permission notice appear in all copies. 9d8671520Syasuoka * 10d8671520Syasuoka * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11d8671520Syasuoka * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12d8671520Syasuoka * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13d8671520Syasuoka * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14d8671520Syasuoka * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15d8671520Syasuoka * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16d8671520Syasuoka * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17d8671520Syasuoka */ 18d8671520Syasuoka 19d8671520Syasuoka #ifndef _CN30XXCOREREG_H_ 20d8671520Syasuoka #define _CN30XXCOREREG_H_ 21d8671520Syasuoka 22d8671520Syasuoka /* 23d8671520Syasuoka * Cavium Networks OCTEON CN30XX Hardware Reference Manual CN30XX-HM-1.0 24d8671520Syasuoka * 4. cnMIPS Cores 25d8671520Syasuoka */ 26d8671520Syasuoka 27d8671520Syasuoka /* 4.11 Core Coprocessor 0 Privileged Registers */ 28d8671520Syasuoka 29d8671520Syasuoka /* CvmCtl Registers */ 30d8671520Syasuoka #define COP_0_CVMCTL_FUSE_START_BIT 0x80000000 31d8671520Syasuoka #define COP_0_CVMCTL_NOFDA_CP2 0x10000000 32d8671520Syasuoka #define COP_0_CVMCTL_NOMUL 0x08000000 33d8671520Syasuoka #define COP_0_CVMCTL_NOCRYPTO 0x04000000 34d8671520Syasuoka #define COP_0_CVMCTL_RST_SHT 0x02000000 35d8671520Syasuoka #define COP_0_CVMCTL_BIST_DIS 0x01000000 36d8671520Syasuoka #define COP_0_CVMCTL_DISSETPRED 0x00800000 37d8671520Syasuoka #define COP_0_CVMCTL_DISJRPRED 0x00400000 38d8671520Syasuoka #define COP_0_CVMCTL_DISICACHE 0x00200000 39d8671520Syasuoka #define COP_0_CVMCTL_DISWAIT 0x00100000 40d8671520Syasuoka #define COP_0_CVMCTL_DEFET 0x00080000 41d8671520Syasuoka #define COP_0_CVMCTL_DISCO 0x00040000 42d8671520Syasuoka #define COP_0_CVMCTL_DISCE 0x00020000 43d8671520Syasuoka #define COP_0_CVMCTL_DDCLK 0x00010000 44d8671520Syasuoka #define COP_0_CVMCTL_DCICLK 0x00008000 45d8671520Syasuoka #define COP_0_CVMCTL_REPUN 0x00004000 46d8671520Syasuoka #define COP_0_CVMCTL_IPREF 0x00002000 47d8671520Syasuoka #define COP_0_CVMCTL_USEUN 0x00001000 48d8671520Syasuoka #define COP_0_CVMCTL_DISIOCACHE 0x00000800 49d8671520Syasuoka #define COP_0_CVMCTL_IRAND 0x00000400 50d8671520Syasuoka #define COP_0_CVMCTL_IPPCI 0x00000380 51d8671520Syasuoka #define COP_0_CVMCTL_IPTI 0x00000070 52d8671520Syasuoka #define COP_0_CVMCTL_LE 0x00000002 53d8671520Syasuoka #define COP_0_CVMCTL_USELY 0x00000001 54d8671520Syasuoka 55*f4fee9beSvisa /* CvmMemCtl register */ 56*f4fee9beSvisa #define COP_0_CVMMEMCTL_LMTENA 0x0008000000000000ull 57*f4fee9beSvisa #define COP_0_CVMMEMCTL_LMTLINE_M 0x0007e00000000000ull 58*f4fee9beSvisa #define COP_0_CVMMEMCTL_LMTLINE_S 45 59*f4fee9beSvisa 60d8671520Syasuoka #endif /* _CN30XXCOREREG_H_ */ 61