1 /* 2 * THIS FILE IS AUTOMATICALLY GENERATED 3 * DONT EDIT THIS FILE 4 */ 5 6 /* $OpenBSD: cn30xxgmxreg.h,v 1.1 2011/06/16 11:22:30 syuu Exp $ */ 7 8 /* 9 * Copyright (c) 2007 Internet Initiative Japan, Inc. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * Cavium Networks OCTEON CN30XX Hardware Reference Manual 36 * CN30XX-HM-1.0 37 * 13.8 GMX Registers 38 */ 39 40 #ifndef _CN30XXGMXREG_H_ 41 #define _CN30XXGMXREG_H_ 42 43 #define GMX0_RX0_INT_REG 0x000 44 #define GMX0_RX0_INT_EN 0x008 45 #define GMX0_PRT0_CFG 0x010 46 #define GMX0_RX0_FRM_CTL 0x018 47 #define GMX0_RX0_FRM_CHK 0x020 48 #define GMX0_RX0_FRM_MIN 0x028 49 #define GMX0_RX0_FRM_MAX 0x030 50 #define GMX0_RX0_JABBER 0x038 51 #define GMX0_RX0_DECISION 0x040 52 #define GMX0_RX0_UDD_SKP 0x048 53 #define GMX0_RX0_STATS_CTL 0x050 54 #define GMX0_RX0_IFG 0x058 55 #define GMX0_RX0_RX_INBND 0x060 56 #define GMX0_RX0_STATS_PKTS 0x080 57 #define GMX0_RX0_STATS_OCTS 0x088 58 #define GMX0_RX0_STATS_PKTS_CTL 0x090 59 #define GMX0_RX0_STATS_OCTS_CTL 0x098 60 #define GMX0_RX0_STATS_PKTS_DMAC 0x0a0 61 #define GMX0_RX0_STATS_OCTS_DMAC 0x0a8 62 #define GMX0_RX0_STATS_PKTS_DRP 0x0b0 63 #define GMX0_RX0_STATS_OCTS_DRP 0x0b8 64 #define GMX0_RX0_STATS_PKTS_BAD 0x0c0 65 #define GMX0_RX0_ADR_CTL 0x100 66 #define GMX0_RX0_ADR_CAM_EN 0x108 67 #define GMX0_RX0_ADR_CAM0 0x180 68 #define GMX0_RX0_ADR_CAM1 0x188 69 #define GMX0_RX0_ADR_CAM2 0x190 70 #define GMX0_RX0_ADR_CAM3 0x198 71 #define GMX0_RX0_ADR_CAM4 0x1a0 72 #define GMX0_RX0_ADR_CAM5 0x1a8 73 #define GMX0_TX0_CLK 0x208 74 #define GMX0_TX0_THRESH 0x210 75 #define GMX0_TX0_APPEND 0x218 76 #define GMX0_TX0_SLOT 0x220 77 #define GMX0_TX0_BURST 0x228 78 #define GMX0_SMAC0 0x230 79 #define GMX0_TX0_PAUSE_PKT_TIME 0x238 80 #define GMX0_TX0_MIN_PKT 0x240 81 #define GMX0_TX0_PAUSE_PKT_INTERVAL 0x248 82 #define GMX0_TX0_SOFT_PAUSE 0x250 83 #define GMX0_TX0_PAUSE_TOGO 0x258 84 #define GMX0_TX0_PAUSE_ZERO 0x260 85 #define GMX0_TX0_STATS_CTL 0x268 86 #define GMX0_TX0_CTL 0x270 87 #define GMX0_TX0_STAT0 0x280 88 #define GMX0_TX0_STAT1 0x288 89 #define GMX0_TX0_STAT2 0x290 90 #define GMX0_TX0_STAT3 0x298 91 #define GMX0_TX0_STAT4 0x2a0 92 #define GMX0_TX0_STAT5 0x2a8 93 #define GMX0_TX0_STAT6 0x2b0 94 #define GMX0_TX0_STAT7 0x2b8 95 #define GMX0_TX0_STAT8 0x2c0 96 #define GMX0_TX0_STAT9 0x2c8 97 #define GMX0_BIST0 0x400 98 #define GMX0_RX_PRTS 0x410 99 #define GMX0_RX_BP_DROP0 0x420 100 #define GMX0_RX_BP_DROP1 0x428 101 #define GMX0_RX_BP_DROP2 0x430 102 #define GMX0_RX_BP_ON0 0x440 103 #define GMX0_RX_BP_ON1 0x448 104 #define GMX0_RX_BP_ON2 0x450 105 #define GMX0_RX_BP_OFF0 0x460 106 #define GMX0_RX_BP_OFF1 0x468 107 #define GMX0_RX_BP_OFF2 0x470 108 #define GMX0_TX_PRTS 0x480 109 #define GMX0_TX_IFG 0x488 110 #define GMX0_TX_JAM 0x490 111 #define GMX0_TX_COL_ATTEMPT 0x498 112 #define GMX0_TX_PAUSE_PKT_DMAC 0x4a0 113 #define GMX0_TX_PAUSE_PKT_TYPE 0x4a8 114 #define GMX0_TX_OVR_BP 0x4c8 115 #define GMX0_TX_BP 0x4d0 116 #define GMX0_TX_CORRUPT 0x4d8 117 #define GMX0_RX_PRT_INFO 0x4e8 118 #define GMX0_TX_LFSR 0x4f8 119 #define GMX0_TX_INT_REG 0x500 120 #define GMX0_TX_INT_EN 0x508 121 #define GMX0_NXA_ADR 0x510 122 #define GMX0_BAD_REG 0x518 123 #define GMX0_STAT_BP 0x520 124 #define GMX0_TX_CLK_MSK0 0x780 125 #define GMX0_TX_CLK_MSK1 0x788 126 #define GMX0_RX_TX_STATUS 0x7e8 127 #define GMX0_INF_MODE 0x7f8 128 129 /* -------------------------------------------------------------------------- */ 130 131 /* GMX Interrupt Registers */ 132 133 #define RXN_INT_REG_XXX_63_19 0xfffffffffff80000ULL 134 #define RXN_INT_REG_PHY_DUPX 0x0000000000040000ULL 135 #define RXN_INT_REG_PHY_SPD 0x0000000000020000ULL 136 #define RXN_INT_REG_PHY_LINK 0x0000000000010000ULL 137 #define RXN_INT_REG_IFGERR 0x0000000000008000ULL 138 #define RXN_INT_REG_COLDET 0x0000000000004000ULL 139 #define RXN_INT_REG_FALERR 0x0000000000002000ULL 140 #define RXN_INT_REG_RSVERR 0x0000000000001000ULL 141 #define RXN_INT_REG_PCTERR 0x0000000000000800ULL 142 #define RXN_INT_REG_OVRERR 0x0000000000000400ULL 143 #define RXN_INT_REG_NIBERR 0x0000000000000200ULL 144 #define RXN_INT_REG_SKPERR 0x0000000000000100ULL 145 #define RXN_INT_REG_RCVERR 0x0000000000000080ULL 146 #define RXN_INT_REG_LENERR 0x0000000000000040ULL 147 #define RXN_INT_REG_ALNERR 0x0000000000000020ULL 148 #define RXN_INT_REG_FCSERR 0x0000000000000010ULL 149 #define RXN_INT_REG_JABBER 0x0000000000000008ULL 150 #define RXN_INT_REG_MAXERR 0x0000000000000004ULL 151 #define RXN_INT_REG_CAREXT 0x0000000000000002ULL 152 #define RXN_INT_REG_MINERR 0x0000000000000001ULL 153 154 /* GMX Interrupt-Enable Registers */ 155 156 #define RXN_INT_EN_XXX_63_19 0xfffffffffff80000ULL 157 #define RXN_INT_EN_PHY_DUPX 0x0000000000040000ULL 158 #define RXN_INT_EN_PHY_SPD 0x0000000000020000ULL 159 #define RXN_INT_EN_PHY_LINK 0x0000000000010000ULL 160 #define RXN_INT_EN_IFGERR 0x0000000000008000ULL 161 #define RXN_INT_EN_COLDET 0x0000000000004000ULL 162 #define RXN_INT_EN_FALERR 0x0000000000002000ULL 163 #define RXN_INT_EN_RSVERR 0x0000000000001000ULL 164 #define RXN_INT_EN_PCTERR 0x0000000000000800ULL 165 #define RXN_INT_EN_OVRERR 0x0000000000000400ULL 166 #define RXN_INT_EN_NIBERR 0x0000000000000200ULL 167 #define RXN_INT_EN_SKPERR 0x0000000000000100ULL 168 #define RXN_INT_EN_RCVERR 0x0000000000000080ULL 169 #define RXN_INT_EN_LENERR 0x0000000000000040ULL 170 #define RXN_INT_EN_ALNERR 0x0000000000000020ULL 171 #define RXN_INT_EN_FCSERR 0x0000000000000010ULL 172 #define RXN_INT_EN_JABBER 0x0000000000000008ULL 173 #define RXN_INT_EN_MAXERR 0x0000000000000004ULL 174 #define RXN_INT_EN_CAREXT 0x0000000000000002ULL 175 #define RXN_INT_EN_MINERR 0x0000000000000001ULL 176 177 /* GMX Port Configuration Registers */ 178 179 #define PRTN_CFG_XXX_63_4 0xfffffffffffffff0ULL 180 #define PRTN_CFG_SLOTTIME 0x0000000000000008ULL 181 #define PRTN_CFG_DUPLEX 0x0000000000000004ULL 182 #define PRTN_CFG_SPEED 0x0000000000000002ULL 183 #define PRTN_CFG_EN 0x0000000000000001ULL 184 185 /* Frame Control Registers */ 186 187 #define RXN_FRM_CTL_XXX_63_11 0xfffffffffffff800ULL 188 #define RXN_FRM_CTL_NULL_DIS 0x0000000000000400ULL 189 #define RXN_FRM_CTL_PRE_ALIGN 0x0000000000000200ULL 190 #define RXN_FRM_CTL_PAD_LEN 0x0000000000000100ULL 191 #define RXN_FRM_CTL_VLAN_LEN 0x0000000000000080ULL 192 #define RXN_FRM_CTL_PRE_FREE 0x0000000000000040ULL 193 #define RXN_FRM_CTL_CTL_SMAC 0x0000000000000020ULL 194 #define RXN_FRM_CTL_CTL_MCST 0x0000000000000010ULL 195 #define RXN_FRM_CTL_CTL_BCK 0x0000000000000008ULL 196 #define RXN_FRM_CTL_CTL_DRP 0x0000000000000004ULL 197 #define RXN_FRM_CTL_PRE_STRP 0x0000000000000002ULL 198 #define RXN_FRM_CTL_PRE_CHK 0x0000000000000001ULL 199 200 /* Frame Check Registers */ 201 202 #define RXN_FRM_CKK_XXX_63_10 0xfffffffffffffc00ULL 203 #define RXN_FRM_CHK_NIBERR 0x0000000000000200ULL 204 #define RXN_FRM_CHK_SKPERR 0x0000000000000100ULL 205 #define RXN_FRM_CHK_RCVERR 0x0000000000000080ULL 206 #define RXN_FRM_CHK_LENERR 0x0000000000000040ULL 207 #define RXN_FRM_CHK_ALNERR 0x0000000000000020ULL 208 #define RXN_FRM_CHK_FCSERR 0x0000000000000010ULL 209 #define RXN_FRM_CHK_JABBER 0x0000000000000008ULL 210 #define RXN_FRM_CHK_MAXERR 0x0000000000000004ULL 211 #define RXN_FRM_CHK_CAREXT 0x0000000000000002ULL 212 #define RXN_FRM_CHK_MINERR 0x0000000000000001ULL 213 214 /* Frame Minimum-Length Registers */ 215 216 #define RXN_RRM_MIN_XXX_63_16 0xffffffffffff0000ULL 217 #define RXN_RRM_MIN_LEN 0x000000000000ffffULL 218 219 /* Frame Maximun-Length Registers */ 220 221 #define RXN_RRM_MAX_XXX_63_16 0xffffffffffff0000ULL 222 #define RXN_RRM_MAX_LEN 0x000000000000ffffULL 223 224 /* GMX Maximun Packet-Size Registers */ 225 226 #define RXN_JABBER_XXX_63_16 0xffffffffffff0000ULL 227 #define RXN_JABBER_CNT 0x000000000000ffffULL 228 229 /* GMX Packet Decision Registers */ 230 231 #define RXN_DECISION_XXX_63_5 0xffffffffffffffe0ULL 232 #define RXN_DECISION_CNT 0x000000000000001fULL 233 234 /* GMX User-Defined Data Skip Registers */ 235 236 #define RXN_UDD_SKP_XXX_63_9 0xfffffffffffffe00ULL 237 #define RXN_UDD_SKP_FCSSEL 0x0000000000000100ULL 238 #define RXN_UDD_SKP_XXX_7 0x0000000000000080ULL 239 #define RXN_UDD_SKP_LEN 0x000000000000007fULL 240 241 /* GMX RX Statistics Control Registers */ 242 243 #define RXN_STATS_CTL_XXX_63_1 0xfffffffffffffffeULL 244 #define RXN_STATS_CTL_RD_CLR 0x0000000000000001ULL 245 246 /* GMX Minimun Interface-Gap Cycles Registers */ 247 248 #define RXN_IFG_XXX_63_4 0xfffffffffffffff0ULL 249 #define RXN_IFG_IFG 0x000000000000000fULL 250 251 /* InBand Link Status Registers */ 252 253 #define RXN_RX_INBND_XXX_63_4 0xfffffffffffffff0ULL 254 #define RXN_RX_INBND_DUPLEX 0x0000000000000008ULL 255 #define RXN_RX_INBND_DUPLEX_SHIFT 3 256 #define RXN_RX_INBND_DUPLEX_HALF (0ULL << RXN_RX_INBND_DUPLEX_SHIFT) 257 #define RXN_RX_INBND_DUPLEX_FULL (1ULL << RXN_RX_INBND_DUPLEX_SHIFT) 258 #define RXN_RX_INBND_SPEED 0x0000000000000006ULL 259 #define RXN_RX_INBND_SPEED_SHIFT 1 260 #define RXN_RX_INBND_SPEED_2_5 (0ULL << RXN_RX_INBND_SPEED_SHIFT) 261 #define RXN_RX_INBND_SPEED_25 (1ULL << RXN_RX_INBND_SPEED_SHIFT) 262 #define RXN_RX_INBND_SPEED_125 (2ULL << RXN_RX_INBND_SPEED_SHIFT) 263 #define RXN_RX_INBND_SPEED_XXX_3 (3ULL << RXN_RX_INBND_SPEED_SHIFT) 264 #define RXN_RX_INBND_STATUS 0x0000000000000001ULL 265 266 /* GMX RX Good Packets Registers */ 267 268 #define RXN_STATS_PKTS_XXX_63_32 0xffffffff00000000ULL 269 #define RXN_STATS_PKTS_CNT 0x00000000ffffffffULL 270 271 /* GMX RX Good Packets Octet Registers */ 272 273 #define RXN_STATS_OCTS_XXX_63_48 0xffff000000000000ULL 274 #define RXN_STATS_OCTS_CNT 0x0000ffffffffffffULL 275 276 /* GMX RX Pause Packets Registers */ 277 278 #define RXN_STATS_PKTS_CTL_XXX_63_32 0xffffffff00000000ULL 279 #define RXN_STATS_PKTS_CTL_CNT 0x00000000ffffffffULL 280 281 /* GMX RX Pause Packets Octet Registers */ 282 283 #define RXN_STATS_OCTS_CTL_XXX_63_48 0xffff000000000000ULL 284 #define RXN_STATS_OCTS_CTL_CNT 0x0000ffffffffffffULL 285 286 /* GMX RX DMAC Packets Registers */ 287 288 #define RXN_STATS_PKTS_DMAC_XXX_63_32 0xffffffff00000000ULL 289 #define RXN_STATS_PKTS_DMAC_CNT 0x00000000ffffffffULL 290 291 /* GMX RX DMAC Packets Octet Registers */ 292 293 #define RXN_STATS_OCTS_DMAC_XXX_63_48 0xffff000000000000ULL 294 #define RXN_STATS_OCTS_DMAC_CNT 0x0000ffffffffffffULL 295 296 /* GMX RX Overflow Packets Registers */ 297 298 #define RXN_STATS_PKTS_DRP_XXX_63_48 0xffffffff00000000ULL 299 #define RXN_STATS_PKTS_DRP_CNT 0x00000000ffffffffULL 300 301 /* GMX RX Overflow Packets Octet Registers */ 302 303 #define RXN_STATS_OCTS_DRP_XXX_63_48 0xffff000000000000ULL 304 #define RXN_STATS_OCTS_DRP_CNT 0x0000ffffffffffffULL 305 306 /* GMX RX Bad Packets Registers */ 307 308 #define RXN_STATS_PKTS_BAD_XXX_63_48 0xffffffff00000000ULL 309 #define RXN_STATS_PKTS_BAD_CNT 0x00000000ffffffffULL 310 311 /* Address-Filtering Control Registers */ 312 313 #define RXN_ADR_CTL_XXX_63_4 0xfffffffffffffff0ULL 314 #define RXN_ADR_CTL_CAM_MODE 0x0000000000000008ULL 315 #define RXN_ADR_CTL_CAM_MODE_SHIFT 3 316 #define RXN_ADR_CTL_CAM_MODE_REJECT (0ULL << RXN_ADR_CTL_CAM_MODE_SHIFT) 317 #define RXN_ADR_CTL_CAM_MODE_ACCEPT (1ULL << RXN_ADR_CTL_CAM_MODE_SHIFT) 318 #define RXN_ADR_CTL_MCST 0x0000000000000006ULL 319 #define RXN_ADR_CTL_MCST_SHIFT 1 320 #define RXN_ADR_CTL_MCST_AFCAM (0ULL << RXN_ADR_CTL_MCST_SHIFT) 321 #define RXN_ADR_CTL_MCST_REJECT (1ULL << RXN_ADR_CTL_MCST_SHIFT) 322 #define RXN_ADR_CTL_MCST_ACCEPT (2ULL << RXN_ADR_CTL_MCST_SHIFT) 323 #define RXN_ADR_CTL_MCST_XXX_3 (3ULL << RXN_ADR_CTL_MCST_SHIFT) 324 #define RXN_ADR_CTL_BCST 0x0000000000000001ULL 325 326 /* Address-Filtering Control Enable Registers */ 327 328 #define RXN_ADR_CAM_EN_XXX_63_8 0xffffffffffffff00ULL 329 #define RXN_ADR_CAM_EN_EN 0x00000000000000ffULL 330 331 /* Address-Filtering CAM Control Registers */ 332 #define RXN_ADR_CAMN_ADR 0xffffffffffffffffULL 333 334 /* GMX TX Clock Generation Registers */ 335 336 #define TXN_CLK_XXX_63_6 0xffffffffffffffc0ULL 337 #define TXN_CLK_CLK_CNT 0x000000000000003fULL 338 339 /* TX Threshold Registers */ 340 341 #define TXN_THRESH_XXX_63_6 0xffffffffffffffc0ULL 342 #define TXN_THRESH_CNT 0x000000000000003fULL 343 344 /* TX Append Control Registers */ 345 346 #define TXN_APPEND_XXX_63_4 0xfffffffffffffff0ULL 347 #define TXN_APPEND_FORCE_FCS 0x0000000000000008ULL 348 #define TXN_APPEND_FCS 0x0000000000000004ULL 349 #define TXN_APPEND_PAD 0x0000000000000002ULL 350 #define TXN_APPEND_PREAMBLE 0x0000000000000001ULL 351 352 /* TX Slottime Counter Registers */ 353 354 #define TXN_SLOT_XXX_63_10 0xfffffffffffffc00ULL 355 #define TXN_SLOT_SLOT 0x00000000000003ffULL 356 357 /* TX Burst-Counter Registers */ 358 359 #define TXN_BURST_XXX_63_16 0xffffffffffff0000ULL 360 #define TXN_BURST_BURST 0x000000000000ffffULL 361 362 /* RGMII SMAC Registers */ 363 364 #define SMACN_XXX_63_48 0xffff000000000000ULL 365 #define SMACN_SMAC 0x0000ffffffffffffULL 366 367 /* TX Pause Packet Pause-Time Registers */ 368 369 #define TXN_PAUSE_PKT_TIME_XXX_63_16 0xffffffffffff0000ULL 370 #define TXN_PAUSE_PKT_TIME_TIME 0x000000000000ffffULL 371 372 /* RGMII TX Minimum-Size-Packet Registers */ 373 374 #define TXN_MIN_PKT_XXX_63_8 0xffffffffffffff00ULL 375 #define TXN_MIN_PKT_MIN_SIZE 0x00000000000000ffULL 376 377 /* TX Pause-Packet Transmission-Interval Registers */ 378 379 #define TXN_PAUSE_PKT_INTERVAL_XXX_63_16 0xffffffffffff0000ULL 380 #define TXN_PAUSE_PKT_INTERVAL_INTERVAL 0x000000000000ffffULL 381 382 /* TX Software-Pause Registers */ 383 384 #define TXN_SOFT_PAUSE_XXX_63_16 0xffffffffffff0000ULL 385 #define TXN_SOFT_PAUSE_TIME 0x000000000000ffffULL 386 387 /* TX Time-to-Backpressure Registers */ 388 389 #define TXN_PAUSE_TOGO_XXX_63_16 0xffffffffffff0000ULL 390 #define TXN_PAUSE_TOGO_TIME 0x000000000000ffffULL 391 392 /* TX Pause-Zero-Enable Registers */ 393 394 #define TXN_PAUSE_ZERO_XXX_63_1 0xfffffffffffffffeULL 395 #define TXN_PAUSE_ZERO_SEND 0x0000000000000001ULL 396 397 /* GMX TX Statistics Control Registers */ 398 399 #define TXN_STATS_CTL_XXX_63_1 0xfffffffffffffffeULL 400 #define TXN_STATS_CTL_RD_CLR 0x0000000000000001ULL 401 402 /* GMX TX Transmit Control Registers */ 403 404 #define TXN_CTL_XXX_63_2 0xfffffffffffffffcULL 405 #define TXN_CTL_XSDEF_EN 0x0000000000000002ULL 406 #define TXN_CTL_XSCOL_EN 0x0000000000000001ULL 407 408 /* Transmit Statistics Registers 0 */ 409 410 #define TXN_STAT0_XSDEF 0xffffffff00000000ULL 411 #define TXN_STAT0_XSCOL 0x00000000ffffffffULL 412 413 /* Transmit Statistics Registers 1 */ 414 415 #define TXN_STAT1_SCOL 0xffffffff00000000ULL 416 #define TXN_STAT1_MSCOL 0x00000000ffffffffULL 417 418 /* Transmit Statistics Registers 2 */ 419 420 #define TXN_STAT2_XXX_63_48 0xffff000000000000ULL 421 #define TXN_STAT2_OCTS 0x0000ffffffffffffULL 422 423 /* Transmit Statistics Registers 3 */ 424 425 #define TXN_STAT3_XXX_63_48 0xffffffff00000000ULL 426 #define TXN_STAT3_PKTS 0x00000000ffffffffULL 427 428 /* Transmit Statistics Registers 4 */ 429 430 #define TXN_STAT4_HIST1 0xffffffff00000000ULL 431 #define TXN_STAT4_HIST0 0x00000000ffffffffULL 432 433 /* Transmit Statistics Registers 5 */ 434 435 #define TXN_STAT5_HIST3 0xffffffff00000000ULL 436 #define TXN_STAT5_HIST2 0x00000000ffffffffULL 437 438 /* Transmit Statistics Registers 6 */ 439 440 #define TXN_STAT6_HIST5 0xffffffff00000000ULL 441 #define TXN_STAT6_HIST4 0x00000000ffffffffULL 442 443 /* Transmit Statistics Registers 7 */ 444 445 #define TXN_STAT7_HIST7 0xffffffff00000000ULL 446 #define TXN_STAT7_HIST6 0x00000000ffffffffULL 447 448 /* Transmit Statistics Registers 8 */ 449 450 #define TXN_STAT8_MCST 0xffffffff00000000ULL 451 #define TXN_STAT8_BCST 0x00000000ffffffffULL 452 453 /* Transmit Statistics Register 9 */ 454 455 #define TXN_STAT9_UNDFLW 0xffffffff00000000ULL 456 #define TXN_STAT9_CTL 0x00000000ffffffffULL 457 458 /* BMX BIST Results Register */ 459 460 #define BIST_XXX_63_10 0xfffffffffffffc00ULL 461 #define BIST_STATUS 0x00000000000003ffULL 462 463 /* RX Ports Register */ 464 465 #define RX_PRTS_XXX_63_3 0xfffffffffffffff8ULL 466 #define RX_PRTS_PRTS 0x0000000000000007ULL 467 468 /* RX FIFO Packet-Drop Registers */ 469 470 #define RX_BP_DROPN_XXX_63_6 0xffffffffffffffc0ULL 471 #define RX_BP_DROPN_MARK 0x000000000000003fULL 472 473 /* RX Backpressure On Registers */ 474 475 #define RX_BP_ONN_XXX_63_9 0xfffffffffffffe00ULL 476 #define RX_BP_ONN_MARK 0x00000000000001ffULL 477 478 /* RX Backpressure Off Registers */ 479 480 #define RX_BP_OFFN_XXX_63_6 0xffffffffffffffc0ULL 481 #define RX_BP_OFFN_MARK 0x000000000000003fULL 482 483 /* TX Ports Register */ 484 485 #define TX_PRTS_XXX_63_5 0xffffffffffffffe0ULL 486 #define TX_PRTS_PRTS 0x000000000000001fULL 487 488 /* TX Interframe Gap Register */ 489 490 #define TX_IFG_XXX_63_8 0xffffffffffffff00ULL 491 #define TX_IFG_IFG2 0x00000000000000f0ULL 492 #define TX_IFG_IFG1 0x000000000000000fULL 493 494 /* TX Jam Pattern Register */ 495 496 #define TX_JAM_XXX_63_8 0xffffffffffffff00ULL 497 #define TX_JAM_JAM 0x00000000000000ffULL 498 499 /* TX Collision Attempts Before Dropping Frame Register */ 500 501 #define TX_COL_ATTEMPT_XXX_63_5 0xffffffffffffffe0ULL 502 #define TX_COL_ATTEMPT_LIMIT 0x000000000000001fULL 503 504 /* TX Pause-Packet DMAC-Field Register */ 505 506 #define TX_PAUSE_PKT_DMAC_XXX_63_48 0xffff000000000000ULL 507 #define TX_PAUSE_PKT_DMAC_DMAC 0x0000ffffffffffffULL 508 509 /* TX Pause Packet Type Field Register */ 510 511 #define TX_PAUSE_PKT_TYPE_XXX_63_16 0xffffffffffff0000ULL 512 #define TX_PAUSE_PKT_TYPE_TYPE 0x000000000000ffffULL 513 514 /* TX Override Backpressure Register */ 515 516 #define TX_OVR_BP_XXX_63_12 0xfffffffffffff000ULL 517 #define TX_OVR_BP_XXX_11 0x0000000000000800ULL 518 #define TX_OVR_BP_EN 0x0000000000000700ULL 519 #define TX_OVR_BP_EN_SHIFT 8 520 #define TX_OVR_BP_XXX_7 0x0000000000000080ULL 521 #define TX_OVR_BP_BP 0x0000000000000070ULL 522 #define TX_OVR_BP_BP_SHIFT 4 523 #define TX_OVR_BP_XXX_3 0x0000000000000008ULL 524 #define TX_OVR_BP_IGN_FULL 0x0000000000000007ULL 525 #define TX_OVR_BP_IGN_FULL_SHIFT 0 526 527 /* TX Override Backpressure Register */ 528 529 #define TX_OVR_BP_XXX_63_12 0xfffffffffffff000ULL 530 #define TX_OVR_BP_XXX_11 0x0000000000000800ULL 531 #define TX_OVR_BP_EN 0x0000000000000700ULL 532 #define TX_OVR_BP_XXX_7 0x0000000000000080ULL 533 #define TX_OVR_BP_BP 0x0000000000000070ULL 534 #define TX_OVR_BP_XXX_3 0x0000000000000008ULL 535 #define TX_OVR_BP_IGN_FULL 0x0000000000000007ULL 536 537 /* TX Backpressure Status Register */ 538 539 #define TX_BP_SR_XXX_63_3 0xfffffffffffffff8ULL 540 #define TX_BP_SR_BP 0x0000000000000007ULL 541 542 /* TX Corrupt Packets Register */ 543 544 #define TX_CORRUPT_XXX_63_3 0xfffffffffffffff8ULL 545 #define TX_CORRUPT_CORRUPT 0x0000000000000007ULL 546 547 /* RX Port State Information Register */ 548 549 #define RX_PRT_INFO_XXX_63_19 0xfffffffffff80000ULL 550 #define RX_PRT_INFO_DROP 0x0000000000070000ULL 551 #define RX_PRT_INFO_XXX_15_3 0x000000000000fff8ULL 552 #define RX_PRT_INFO_COMMIT 0x0000000000000007ULL 553 554 /* TX LFSR Register */ 555 556 #define TX_LFSR_XXX_63_16 0xffffffffffff0000ULL 557 #define TX_LFSR_LFSR 0x000000000000ffffULL 558 559 /* TX Interrupt Register */ 560 561 #define TX_INT_REG_XXX_63_20 0xfffffffffff00000ULL 562 #define TX_INT_REG_XXX_19 0x0000000000080000ULL 563 #define TX_INT_REG_LATE_COL 0x0000000000070000ULL 564 #define TX_INT_REG_XXX_15 0x0000000000008000ULL 565 #define TX_INT_REG_XSDEF 0x0000000000007000ULL 566 #define TX_INT_REG_XXX_11 0x0000000000000800ULL 567 #define TX_INT_REG_XSCOL 0x0000000000000700ULL 568 #define TX_INT_REG_XXX_7_5 0x00000000000000e0ULL 569 #define TX_INT_REG_UNDFLW 0x000000000000001cULL 570 #define TX_INT_REG_XXX_1 0x0000000000000002ULL 571 #define TX_INT_REG_PKO_NXA 0x0000000000000001ULL 572 573 /* TX Interrupt Register */ 574 575 #define TX_INT_EN_XXX_63_20 0xfffffffffff00000ULL 576 #define TX_INT_EN_XXX_19 0x0000000000080000ULL 577 #define TX_INT_EN_LATE_COL 0x0000000000070000ULL 578 #define TX_INT_EN_XXX_15 0x0000000000008000ULL 579 #define TX_INT_EN_XSDEF 0x0000000000007000ULL 580 #define TX_INT_EN_XXX_11 0x0000000000000800ULL 581 #define TX_INT_EN_XSCOL 0x0000000000000700ULL 582 #define TX_INT_EN_XXX_7_5 0x00000000000000e0ULL 583 #define TX_INT_EN_UNDFLW 0x000000000000001cULL 584 #define TX_INT_EN_XXX_1 0x0000000000000002ULL 585 #define TX_INT_EN_PKO_NXA 0x0000000000000001ULL 586 587 /* Address-out-of-Range Error Register */ 588 589 #define NXA_ADR_XXX_63_6 0xffffffffffffffc0ULL 590 #define NXA_ADR_PRT 0x000000000000003fULL 591 592 /* GMX Miscellaneous Error Register */ 593 594 #define BAD_REG_XXX_63_31 0xffffffff80000000ULL 595 #define BAD_REG_INB_NXA 0x0000000078000000ULL 596 #define BAD_REG_STATOVR 0x0000000004000000ULL 597 #define BAD_REG_XXX_25 0x0000000002000000ULL 598 #define BAD_REG_LOSTSTAT 0x0000000001c00000ULL 599 #define BAD_REG_XXX_21_18 0x00000000003c0000ULL 600 #define BAD_REG_XXX_17_5 0x000000000003ffe0ULL 601 #define BAD_REG_OUT_OVR 0x000000000000001cULL 602 #define BAD_REG_XXX_1_0 0x0000000000000003ULL 603 604 /* GMX Backpressure Statistics Register */ 605 606 #define STAT_BP_XXX_63_17 0xfffffffffffe0000ULL 607 #define STAT_BP_BP 0x0000000000010000ULL 608 #define STAT_BP_CNT 0x000000000000ffffULL 609 610 /* Mode Change Mask Registers */ 611 612 #define TX_CLK_MSKN_XXX_63_1 0xfffffffffffffffeULL 613 #define TX_CLK_MSKN_MSK 0x0000000000000001ULL 614 615 /* GMX RX/TX Status Register */ 616 617 #define RX_TX_STATUS_XXX_63_7 0xffffffffffffff80ULL 618 #define RX_TX_STATUS_TX 0x0000000000000070ULL 619 #define RX_TX_STATUS_XXX_3 0x0000000000000008ULL 620 #define RX_TX_STATUS_RX 0x0000000000000007ULL 621 622 /* Interface Mode Register */ 623 624 #define INF_MODE_XXX_63_3 0xfffffffffffffff8ULL 625 #define INF_MODE_P0MII 0x0000000000000004ULL 626 #define INF_MODE_EN 0x0000000000000002ULL 627 #define INF_MODE_TYPE 0x0000000000000001ULL 628 629 /* -------------------------------------------------------------------------- */ 630 631 /* for bus_space(9) */ 632 633 #define GMX_IF_NUNITS 1 634 #define GMX_PORT_NUNITS 3 635 636 #define GMX0_BASE_PORT0 0x0001180008000000ULL 637 #define GMX0_BASE_PORT1 0x0001180008000800ULL 638 #define GMX0_BASE_PORT2 0x0001180008001000ULL 639 #define GMX0_BASE_PORT_SIZE 0x00800 640 #define GMX0_BASE_IF0 0x0001180008000000ULL 641 #define GMX0_BASE_IF_SIZE (GMX0_BASE_PORT_SIZE * GMX_PORT_NUNITS) 642 643 /* for bitmask_snprintf(9) */ 644 645 #define RXN_INT_REG_BITS \ 646 "\177" /* new format */ \ 647 "\177" /* seil ext */ \ 648 "\020" /* hex display */ \ 649 "\020" /* %016x format */ \ 650 "b\x12" "PHY_DUPX\0" \ 651 "b\x11" "PHY_SPD\0" \ 652 "b\x10" "PHY_LINK\0" \ 653 "b\x0f" "IFGERR\0" \ 654 "b\x0e" "COLDET\0" \ 655 "b\x0d" "FALERR\0" \ 656 "b\x0c" "RSVERR\0" \ 657 "b\x0b" "PCTERR\0" \ 658 "b\x0a" "OVRERR\0" \ 659 "b\x09" "NIBERR\0" \ 660 "b\x08" "SKPERR\0" \ 661 "b\x07" "RCVERR\0" \ 662 "b\x06" "LENERR\0" \ 663 "b\x05" "ALNERR\0" \ 664 "b\x04" "FCSERR\0" \ 665 "b\x03" "JABBER\0" \ 666 "b\x02" "MAXERR\0" \ 667 "b\x01" "CAREXT\0" \ 668 "b\x00" "MINERR\0" 669 #define RXN_INT_EN_BITS \ 670 "\177" /* new format */ \ 671 "\177" /* seil ext */ \ 672 "\020" /* hex display */ \ 673 "\020" /* %016x format */ \ 674 "b\x12" "PHY_DUPX\0" \ 675 "b\x11" "PHY_SPD\0" \ 676 "b\x10" "PHY_LINK\0" \ 677 "b\x0f" "IFGERR\0" \ 678 "b\x0e" "COLDET\0" \ 679 "b\x0d" "FALERR\0" \ 680 "b\x0c" "RSVERR\0" \ 681 "b\x0b" "PCTERR\0" \ 682 "b\x0a" "OVRERR\0" \ 683 "b\x09" "NIBERR\0" \ 684 "b\x08" "SKPERR\0" \ 685 "b\x07" "RCVERR\0" \ 686 "b\x06" "LENERR\0" \ 687 "b\x05" "ALNERR\0" \ 688 "b\x04" "FCSERR\0" \ 689 "b\x03" "JABBER\0" \ 690 "b\x02" "MAXERR\0" \ 691 "b\x01" "CAREXT\0" \ 692 "b\x00" "MINERR\0" 693 #define PRTN_CFG_BITS \ 694 "\177" /* new format */ \ 695 "\177" /* seil ext */ \ 696 "\020" /* hex display */ \ 697 "\020" /* %016x format */ \ 698 "b\x03" "SLOTTIME\0" \ 699 "b\x02" "DUPLEX\0" \ 700 "b\x01" "SPEED\0" \ 701 "b\x00" "EN\0" 702 #define RXN_FRM_CTL_BITS \ 703 "\177" /* new format */ \ 704 "\177" /* seil ext */ \ 705 "\020" /* hex display */ \ 706 "\020" /* %016x format */ \ 707 "b\x0a" "NULL_DIS\0" \ 708 "b\x09" "PRE_ALIGN\0" \ 709 "b\x08" "PAD_LEN\0" \ 710 "b\x07" "VLAN_LEN\0" \ 711 "b\x06" "PRE_FREE\0" \ 712 "b\x05" "CTL_SMAC\0" \ 713 "b\x04" "CTL_MCST\0" \ 714 "b\x03" "CTL_BCK\0" \ 715 "b\x02" "CTL_DRP\0" \ 716 "b\x01" "PRE_STRP\0" \ 717 "b\x00" "PRE_CHK\0" 718 #define RXN_FRM_CHK_BITS \ 719 "\177" /* new format */ \ 720 "\177" /* seil ext */ \ 721 "\020" /* hex display */ \ 722 "\020" /* %016x format */ \ 723 "b\x09" "NIBERR\0" \ 724 "b\x08" "SKPERR\0" \ 725 "b\x07" "RCVERR\0" \ 726 "b\x06" "LENERR\0" \ 727 "b\x05" "ALNERR\0" \ 728 "b\x04" "FCSERR\0" \ 729 "b\x03" "JABBER\0" \ 730 "b\x02" "MAXERR\0" \ 731 "b\x01" "CAREXT\0" \ 732 "b\x00" "MINERR\0" 733 /* RXN_FRM_MIN */ 734 /* RXN_FRM_MAX */ 735 #define RXN_JABBER_BITS \ 736 "\177" /* new format */ \ 737 "\177" /* seil ext */ \ 738 "\020" /* hex display */ \ 739 "\020" /* %016x format */ \ 740 "f\x00\x10" "CNT\0" 741 #define RXN_DECISION_BITS \ 742 "\177" /* new format */ \ 743 "\177" /* seil ext */ \ 744 "\020" /* hex display */ \ 745 "\020" /* %016x format */ \ 746 "f\x00\x05" "CNT\0" 747 #define RXN_UDD_SKP_BITS \ 748 "\177" /* new format */ \ 749 "\177" /* seil ext */ \ 750 "\020" /* hex display */ \ 751 "\020" /* %016x format */ \ 752 "b\x08" "FCSSEL\0" \ 753 "f\x00\x07" "LEN\0" 754 #define RXN_STATS_CTL_BITS \ 755 "\177" /* new format */ \ 756 "\177" /* seil ext */ \ 757 "\020" /* hex display */ \ 758 "\020" /* %016x format */ \ 759 "b\x00" "RD_CLR\0" 760 #define RXN_IFG_BITS \ 761 "\177" /* new format */ \ 762 "\177" /* seil ext */ \ 763 "\020" /* hex display */ \ 764 "\020" /* %016x format */ \ 765 "f\x00\x04" "IFG\0" 766 #define RXN_RX_INBND_BITS \ 767 "\177" /* new format */ \ 768 "\177" /* seil ext */ \ 769 "\020" /* hex display */ \ 770 "\020" /* %016x format */ \ 771 "b\x03" "DUPLEX\0" \ 772 "f\x01\x02" "SPEED\0" \ 773 "b\x00" "STATUS\0" 774 #define RXN_STATS_PKTS_BITS \ 775 "\177" /* new format */ \ 776 "\177" /* seil ext */ \ 777 "\020" /* hex display */ \ 778 "\020" /* %016x format */ \ 779 "f\x00\x20" "CNT\0" 780 #define RXN_STATS_OCTS_BITS \ 781 "\177" /* new format */ \ 782 "\177" /* seil ext */ \ 783 "\020" /* hex display */ \ 784 "\020" /* %016x format */ \ 785 "f\x00\x30" "CNT\0" 786 #define RXN_STATS_PKTS_CTL_BITS \ 787 "\177" /* new format */ \ 788 "\177" /* seil ext */ \ 789 "\020" /* hex display */ \ 790 "\020" /* %016x format */ \ 791 "f\x00\x20" "CNT\0" 792 #define RXN_STATS_OCTS_CTL_BITS \ 793 "\177" /* new format */ \ 794 "\177" /* seil ext */ \ 795 "\020" /* hex display */ \ 796 "\020" /* %016x format */ \ 797 "f\x00\x30" "CNT\0" 798 #define RXN_STATS_PKTS_DMAC_BITS \ 799 "\177" /* new format */ \ 800 "\177" /* seil ext */ \ 801 "\020" /* hex display */ \ 802 "\020" /* %016x format */ \ 803 "f\x00\x20" "CNT\0" 804 #define RXN_STATS_OCTS_DMAC_BITS \ 805 "\177" /* new format */ \ 806 "\177" /* seil ext */ \ 807 "\020" /* hex display */ \ 808 "\020" /* %016x format */ \ 809 "f\x00\x30" "CNT\0" 810 #define RXN_STATS_PKTS_DRP_BITS \ 811 "\177" /* new format */ \ 812 "\177" /* seil ext */ \ 813 "\020" /* hex display */ \ 814 "\020" /* %016x format */ \ 815 "f\x00\x20" "CNT\0" 816 #define RXN_STATS_OCTS_DRP_BITS \ 817 "\177" /* new format */ \ 818 "\177" /* seil ext */ \ 819 "\020" /* hex display */ \ 820 "\020" /* %016x format */ \ 821 "f\x00\x30" "CNT\0" 822 #define RXN_STATS_PKTS_BAD_BITS \ 823 "\177" /* new format */ \ 824 "\177" /* seil ext */ \ 825 "\020" /* hex display */ \ 826 "\020" /* %016x format */ \ 827 "f\x00\x20" "CNT\0" 828 #define RXN_ADR_CTL_BITS \ 829 "\177" /* new format */ \ 830 "\177" /* seil ext */ \ 831 "\020" /* hex display */ \ 832 "\020" /* %016x format */ \ 833 "b\x03" "CAM_MODE\0" \ 834 "f\x01\x02" "MCST\0" \ 835 "b\x00" "BCST\0" 836 #define RXN_ADR_CAM_EN_BITS \ 837 "\177" /* new format */ \ 838 "\177" /* seil ext */ \ 839 "\020" /* hex display */ \ 840 "\020" /* %016x format */ \ 841 "f\x00\x08" "EN\0" 842 /* RXN_ADR_CAM0 */ 843 /* RXN_ADR_CAM1 */ 844 /* RXN_ADR_CAM2 */ 845 /* RXN_ADR_CAM3 */ 846 /* RXN_ADR_CAM4 */ 847 /* RXN_ADR_CAM5 */ 848 #define TXN_CLK_BITS \ 849 "\177" /* new format */ \ 850 "\177" /* seil ext */ \ 851 "\020" /* hex display */ \ 852 "\020" /* %016x format */ \ 853 "f\x00\x06" "CLK_CNT\0" 854 #define TXN_THRESH_BITS \ 855 "\177" /* new format */ \ 856 "\177" /* seil ext */ \ 857 "\020" /* hex display */ \ 858 "\020" /* %016x format */ \ 859 "f\x00\x06" "CNT\0" 860 #define TXN_APPEND_BITS \ 861 "\177" /* new format */ \ 862 "\177" /* seil ext */ \ 863 "\020" /* hex display */ \ 864 "\020" /* %016x format */ \ 865 "b\x03" "FORCE_FCS\0" \ 866 "b\x02" "FCS\0" \ 867 "b\x01" "PAD\0" \ 868 "b\x00" "PREAMBLE\0" 869 #define TXN_SLOT_BITS \ 870 "\177" /* new format */ \ 871 "\177" /* seil ext */ \ 872 "\020" /* hex display */ \ 873 "\020" /* %016x format */ \ 874 "f\x00\x0a" "SLOT\0" 875 #define TXN_BURST_BITS \ 876 "\177" /* new format */ \ 877 "\177" /* seil ext */ \ 878 "\020" /* hex display */ \ 879 "\020" /* %016x format */ \ 880 "f\x00\x10" "BURST\0" 881 /* SMAC0 */ 882 #define TXN_PAUSE_PKT_TIME_BITS \ 883 "\177" /* new format */ \ 884 "\177" /* seil ext */ \ 885 "\020" /* hex display */ \ 886 "\020" /* %016x format */ \ 887 "f\x00\x10" "TIME\0" 888 #define TXN_MIN_PKT_BITS \ 889 "\177" /* new format */ \ 890 "\177" /* seil ext */ \ 891 "\020" /* hex display */ \ 892 "\020" /* %016x format */ \ 893 "f\x00\x08" "MIN_SIZE\0" 894 #define TXN_PAUSE_PKT_INTERVAL_BITS \ 895 "\177" /* new format */ \ 896 "\177" /* seil ext */ \ 897 "\020" /* hex display */ \ 898 "\020" /* %016x format */ \ 899 "f\x00\x10" "INTERVAL\0" 900 #define TXN_SOFT_PAUSE_BITS \ 901 "\177" /* new format */ \ 902 "\177" /* seil ext */ \ 903 "\020" /* hex display */ \ 904 "\020" /* %016x format */ \ 905 "f\x00\x10" "TIME\0" 906 #define TXN_PAUSE_TOGO_BITS \ 907 "\177" /* new format */ \ 908 "\177" /* seil ext */ \ 909 "\020" /* hex display */ \ 910 "\020" /* %016x format */ \ 911 "f\x00\x10" "TIME\0" 912 #define TXN_PAUSE_ZERO_BITS \ 913 "\177" /* new format */ \ 914 "\177" /* seil ext */ \ 915 "\020" /* hex display */ \ 916 "\020" /* %016x format */ \ 917 "b\x00" "SEND\0" 918 #define TXN_STATS_CTL_BITS \ 919 "\177" /* new format */ \ 920 "\177" /* seil ext */ \ 921 "\020" /* hex display */ \ 922 "\020" /* %016x format */ \ 923 "b\x00" "RD_CLR\0" 924 #define TXN_CTL_BITS \ 925 "\177" /* new format */ \ 926 "\177" /* seil ext */ \ 927 "\020" /* hex display */ \ 928 "\020" /* %016x format */ \ 929 "b\x01" "XSDEF_EN\0" \ 930 "b\x00" "XSCOL_EN\0" 931 #define TXN_STAT0_BITS \ 932 "\177" /* new format */ \ 933 "\177" /* seil ext */ \ 934 "\020" /* hex display */ \ 935 "\020" /* %016x format */ \ 936 "f\x20\x20" "XSDEF\0" \ 937 "f\x00\x20" "XSCOL\0" 938 #define TXN_STAT1_BITS \ 939 "\177" /* new format */ \ 940 "\177" /* seil ext */ \ 941 "\020" /* hex display */ \ 942 "\020" /* %016x format */ \ 943 "f\x20\x20" "SCOL\0" \ 944 "f\x00\x20" "MSCOL\0" 945 #define TXN_STAT2_BITS \ 946 "\177" /* new format */ \ 947 "\177" /* seil ext */ \ 948 "\020" /* hex display */ \ 949 "\020" /* %016x format */ \ 950 "f\x00\x30" "OCTS\0" 951 #define TXN_STAT3_BITS \ 952 "\177" /* new format */ \ 953 "\177" /* seil ext */ \ 954 "\020" /* hex display */ \ 955 "\020" /* %016x format */ \ 956 "f\x00\x20" "PKTS\0" 957 #define TXN_STAT4_BITS \ 958 "\177" /* new format */ \ 959 "\177" /* seil ext */ \ 960 "\020" /* hex display */ \ 961 "\020" /* %016x format */ \ 962 "f\x20\x20" "HIST1\0" \ 963 "f\x00\x20" "HIST0\0" 964 #define TXN_STAT5_BITS \ 965 "\177" /* new format */ \ 966 "\177" /* seil ext */ \ 967 "\020" /* hex display */ \ 968 "\020" /* %016x format */ \ 969 "f\x20\x20" "HIST3\0" \ 970 "f\x00\x20" "HIST2\0" 971 #define TXN_STAT6_BITS \ 972 "\177" /* new format */ \ 973 "\177" /* seil ext */ \ 974 "\020" /* hex display */ \ 975 "\020" /* %016x format */ \ 976 "f\x20\x20" "HIST5\0" \ 977 "f\x00\x20" "HIST4\0" 978 #define TXN_STAT7_BITS \ 979 "\177" /* new format */ \ 980 "\177" /* seil ext */ \ 981 "\020" /* hex display */ \ 982 "\020" /* %016x format */ \ 983 "f\x20\x20" "HIST7\0" \ 984 "f\x00\x20" "HIST6\0" 985 #define TXN_STAT8_BITS \ 986 "\177" /* new format */ \ 987 "\177" /* seil ext */ \ 988 "\020" /* hex display */ \ 989 "\020" /* %016x format */ \ 990 "f\x20\x20" "MCST\0" \ 991 "f\x00\x20" "BCST\0" 992 #define TXN_STAT9_BITS \ 993 "\177" /* new format */ \ 994 "\177" /* seil ext */ \ 995 "\020" /* hex display */ \ 996 "\020" /* %016x format */ \ 997 "f\x20\x20" "UNDFLW\0" \ 998 "f\x00\x20" "CTL\0" 999 /* BIST0 */ 1000 #define RX_PRTS_BITS \ 1001 "\177" /* new format */ \ 1002 "\177" /* seil ext */ \ 1003 "\020" /* hex display */ \ 1004 "\020" /* %016x format */ \ 1005 "f\x00\x03" "PRTS\0" 1006 #define RX_BP_DROPN_BITS \ 1007 "\177" /* new format */ \ 1008 "\177" /* seil ext */ \ 1009 "\020" /* hex display */ \ 1010 "\020" /* %016x format */ \ 1011 "f\x00\x06" "MARK\0" 1012 #define RX_BP_ONN_BITS \ 1013 "\177" /* new format */ \ 1014 "\177" /* seil ext */ \ 1015 "\020" /* hex display */ \ 1016 "\020" /* %016x format */ \ 1017 "f\x00\x09" "MARK\0" 1018 #define RX_BP_OFFN_BITS \ 1019 "\177" /* new format */ \ 1020 "\177" /* seil ext */ \ 1021 "\020" /* hex display */ \ 1022 "\020" /* %016x format */ \ 1023 "f\x00\x06" "MARK\0" 1024 #define TX_PRTS_BITS \ 1025 "\177" /* new format */ \ 1026 "\177" /* seil ext */ \ 1027 "\020" /* hex display */ \ 1028 "\020" /* %016x format */ \ 1029 "f\x00\x05" "PRTS\0" 1030 #define TX_IFG_BITS \ 1031 "\177" /* new format */ \ 1032 "\177" /* seil ext */ \ 1033 "\020" /* hex display */ \ 1034 "\020" /* %016x format */ \ 1035 "f\x04\x04" "IFG2\0" \ 1036 "f\x00\x04" "IFG1\0" 1037 #define TX_JAM_BITS \ 1038 "\177" /* new format */ \ 1039 "\177" /* seil ext */ \ 1040 "\020" /* hex display */ \ 1041 "\020" /* %016x format */ \ 1042 "f\x00\x08" "JAM\0" 1043 #define TX_COL_ATTEMPT_BITS \ 1044 "\177" /* new format */ \ 1045 "\177" /* seil ext */ \ 1046 "\020" /* hex display */ \ 1047 "\020" /* %016x format */ \ 1048 "f\x00\x05" "LIMIT\0" 1049 #define TX_PAUSE_PKT_DMAC_BITS \ 1050 "\177" /* new format */ \ 1051 "\177" /* seil ext */ \ 1052 "\020" /* hex display */ \ 1053 "\020" /* %016x format */ \ 1054 "f\x00\x30" "DMAC\0" 1055 #define TX_PAUSE_PKT_TYPE_BITS \ 1056 "\177" /* new format */ \ 1057 "\177" /* seil ext */ \ 1058 "\020" /* hex display */ \ 1059 "\020" /* %016x format */ \ 1060 "f\x00\x10" "TYPE\0" 1061 #define TX_OVR_BP_BITS \ 1062 "\177" /* new format */ \ 1063 "\177" /* seil ext */ \ 1064 "\020" /* hex display */ \ 1065 "\020" /* %016x format */ \ 1066 "f\x08\x03" "EN\0" \ 1067 "f\x04\x03" "BP\0" \ 1068 "f\x00\x03" "IGN_FULL\0" 1069 #define TX_BP_BITS \ 1070 "\177" /* new format */ \ 1071 "\177" /* seil ext */ \ 1072 "\020" /* hex display */ \ 1073 "\020" /* %016x format */ \ 1074 "f\x00\x03" "SR_BP\0" 1075 #define TX_CORRUPT_BITS \ 1076 "\177" /* new format */ \ 1077 "\177" /* seil ext */ \ 1078 "\020" /* hex display */ \ 1079 "\020" /* %016x format */ \ 1080 "f\x00\x03" "CORRUPT\0" 1081 #define RX_PRT_INFO_BITS \ 1082 "\177" /* new format */ \ 1083 "\177" /* seil ext */ \ 1084 "\020" /* hex display */ \ 1085 "\020" /* %016x format */ \ 1086 "f\x10\x03" "DROP\0" \ 1087 "f\x00\x03" "COMMIT\0" 1088 #define TX_LFSR_BITS \ 1089 "\177" /* new format */ \ 1090 "\177" /* seil ext */ \ 1091 "\020" /* hex display */ \ 1092 "\020" /* %016x format */ \ 1093 "f\x00\x10" "LFSR\0" 1094 #define TX_INT_REG_BITS \ 1095 "\177" /* new format */ \ 1096 "\177" /* seil ext */ \ 1097 "\020" /* hex display */ \ 1098 "\020" /* %016x format */ \ 1099 "f\x10\x03" "LATE_COL\0" \ 1100 "f\x0c\x03" "XSDEF\0" \ 1101 "f\x08\x03" "XSCOL\0" \ 1102 "f\x02\x03" "UNDFLW\0" \ 1103 "b\x00" "PKO_NXA\0" 1104 #define TX_INT_EN_BITS \ 1105 "\177" /* new format */ \ 1106 "\177" /* seil ext */ \ 1107 "\020" /* hex display */ \ 1108 "\020" /* %016x format */ \ 1109 "f\x10\x03" "LATE_COL\0" \ 1110 "f\x0c\x03" "XSDEF\0" \ 1111 "f\x08\x03" "XSCOL\0" \ 1112 "f\x02\x03" "UNDFLW\0" \ 1113 "b\x00" "PKO_NXA\0" 1114 #define NXA_ADR_BITS \ 1115 "\177" /* new format */ \ 1116 "\177" /* seil ext */ \ 1117 "\020" /* hex display */ \ 1118 "\020" /* %016x format */ \ 1119 "f\x00\x06" "PRT\0" 1120 #define BAD_REG_BITS \ 1121 "\177" /* new format */ \ 1122 "\177" /* seil ext */ \ 1123 "\020" /* hex display */ \ 1124 "\020" /* %016x format */ \ 1125 "f\x1b\x04" "INB_NXA\0" \ 1126 "b\x1a" "STATOVR\0" \ 1127 "f\x16\x03" "LOSTSTAT\0" \ 1128 "f\x02\x03" "OUT_OVR\0" 1129 #define STAT_BP_BITS \ 1130 "\177" /* new format */ \ 1131 "\177" /* seil ext */ \ 1132 "\020" /* hex display */ \ 1133 "\020" /* %016x format */ \ 1134 "b\x10" "BP\0" \ 1135 "f\x00\x10" "CNT\0" 1136 #define TX_CLK_MSKN_BITS \ 1137 "\177" /* new format */ \ 1138 "\177" /* seil ext */ \ 1139 "\020" /* hex display */ \ 1140 "\020" /* %016x format */ \ 1141 "b\x00" "MSK\0" 1142 #define RX_TX_STATUS_BITS \ 1143 "\177" /* new format */ \ 1144 "\177" /* seil ext */ \ 1145 "\020" /* hex display */ \ 1146 "\020" /* %016x format */ \ 1147 "f\x04\x03" "TX\0" \ 1148 "f\x00\x03" "RX\0" 1149 #define INF_MODE_BITS \ 1150 "\177" /* new format */ \ 1151 "\177" /* seil ext */ \ 1152 "\020" /* hex display */ \ 1153 "\020" /* %016x format */ \ 1154 "b\x02" "P0MII\0" \ 1155 "b\x01" "EN\0" \ 1156 "b\x00" "TYPE\0" 1157 1158 #define GMX0_RX0_INT_REG_BITS RXN_INT_REG_BITS 1159 #define GMX0_RX0_INT_EN_BITS RXN_INT_EN_BITS 1160 #define GMX0_PRT0_CFG_BITS PRTN_CFG_BITS 1161 #define GMX0_RX0_FRM_CTL_BITS RXN_FRM_CTL_BITS 1162 #define GMX0_RX0_FRM_CHK_BITS RXN_FRM_CHK_BITS 1163 #define GMX0_RX0_FRM_MIN_BITS NULL//RXN_FRM_MIN_BITS 1164 #define GMX0_RX0_FRM_MAX_BITS NULL//RXN_FRM_MAX_BITS 1165 #define GMX0_RX0_JABBER_BITS RXN_JABBER_BITS 1166 #define GMX0_RX0_DECISION_BITS RXN_DECISION_BITS 1167 #define GMX0_RX0_UDD_SKP_BITS RXN_UDD_SKP_BITS 1168 #define GMX0_RX0_STATS_CTL_BITS RXN_STATS_CTL_BITS 1169 #define GMX0_RX0_IFG_BITS RXN_IFG_BITS 1170 #define GMX0_RX0_RX_INBND_BITS RXN_RX_INBND_BITS 1171 #define GMX0_RX0_STATS_PKTS_BITS RXN_STATS_PKTS_BITS 1172 #define GMX0_RX0_STATS_OCTS_BITS RXN_STATS_OCTS_BITS 1173 #define GMX0_RX0_STATS_PKTS_CTL_BITS RXN_STATS_PKTS_CTL_BITS 1174 #define GMX0_RX0_STATS_OCTS_CTL_BITS RXN_STATS_OCTS_CTL_BITS 1175 #define GMX0_RX0_STATS_PKTS_DMAC_BITS RXN_STATS_PKTS_DMAC_BITS 1176 #define GMX0_RX0_STATS_OCTS_DMAC_BITS RXN_STATS_OCTS_DMAC_BITS 1177 #define GMX0_RX0_STATS_PKTS_DRP_BITS RXN_STATS_PKTS_DRP_BITS 1178 #define GMX0_RX0_STATS_OCTS_DRP_BITS RXN_STATS_OCTS_DRP_BITS 1179 #define GMX0_RX0_STATS_PKTS_BAD_BITS RXN_STATS_PKTS_BAD_BITS 1180 #define GMX0_RX0_ADR_CTL_BITS RXN_ADR_CTL_BITS 1181 #define GMX0_RX0_ADR_CAM_EN_BITS RXN_ADR_CAM_EN_BITS 1182 #define GMX0_RX0_ADR_CAM0_BITS NULL//RXN_ADR_CAM0_BITS 1183 #define GMX0_RX0_ADR_CAM1_BITS NULL//RXN_ADR_CAM1_BITS 1184 #define GMX0_RX0_ADR_CAM2_BITS NULL//RXN_ADR_CAM2_BITS 1185 #define GMX0_RX0_ADR_CAM3_BITS NULL//RXN_ADR_CAM3_BITS 1186 #define GMX0_RX0_ADR_CAM4_BITS NULL//RXN_ADR_CAM4_BITS 1187 #define GMX0_RX0_ADR_CAM5_BITS NULL//RXN_ADR_CAM5_BITS 1188 #define GMX0_TX0_CLK_BITS TXN_CLK_BITS 1189 #define GMX0_TX0_THRESH_BITS TXN_THRESH_BITS 1190 #define GMX0_TX0_APPEND_BITS TXN_APPEND_BITS 1191 #define GMX0_TX0_SLOT_BITS TXN_SLOT_BITS 1192 #define GMX0_TX0_BURST_BITS TXN_BURST_BITS 1193 #define GMX0_SMAC0_BITS NULL//SMAC0_BITS 1194 #define GMX0_TX0_PAUSE_PKT_TIME_BITS TXN_PAUSE_PKT_TIME_BITS 1195 #define GMX0_TX0_MIN_PKT_BITS TXN_MIN_PKT_BITS 1196 #define GMX0_TX0_PAUSE_PKT_INTERVAL_BITS TXN_PAUSE_PKT_INTERVAL_BITS 1197 #define GMX0_TX0_SOFT_PAUSE_BITS TXN_SOFT_PAUSE_BITS 1198 #define GMX0_TX0_PAUSE_TOGO_BITS TXN_PAUSE_TOGO_BITS 1199 #define GMX0_TX0_PAUSE_ZERO_BITS TXN_PAUSE_ZERO_BITS 1200 #define GMX0_TX0_STATS_CTL_BITS TXN_STATS_CTL_BITS 1201 #define GMX0_TX0_CTL_BITS TXN_CTL_BITS 1202 #define GMX0_TX0_STAT0_BITS TXN_STAT0_BITS 1203 #define GMX0_TX0_STAT1_BITS TXN_STAT1_BITS 1204 #define GMX0_TX0_STAT2_BITS TXN_STAT2_BITS 1205 #define GMX0_TX0_STAT3_BITS TXN_STAT3_BITS 1206 #define GMX0_TX0_STAT4_BITS TXN_STAT4_BITS 1207 #define GMX0_TX0_STAT5_BITS TXN_STAT5_BITS 1208 #define GMX0_TX0_STAT6_BITS TXN_STAT6_BITS 1209 #define GMX0_TX0_STAT7_BITS TXN_STAT7_BITS 1210 #define GMX0_TX0_STAT8_BITS TXN_STAT8_BITS 1211 #define GMX0_TX0_STAT9_BITS TXN_STAT9_BITS 1212 #define GMX0_BIST0_BITS NULL//BIST0_BITS 1213 #define GMX0_RX_PRTS_BITS RX_PRTS_BITS 1214 #define GMX0_RX_BP_DROP0_BITS RX_BP_DROPN_BITS 1215 #define GMX0_RX_BP_ON0_BITS RX_BP_ONN_BITS 1216 #define GMX0_RX_BP_OFF0_BITS RX_BP_OFFN_BITS 1217 #define GMX0_RX_BP_DROP1_BITS RX_BP_DROPN_BITS 1218 #define GMX0_RX_BP_ON1_BITS RX_BP_ONN_BITS 1219 #define GMX0_RX_BP_OFF1_BITS RX_BP_OFFN_BITS 1220 #define GMX0_RX_BP_DROP2_BITS RX_BP_DROPN_BITS 1221 #define GMX0_RX_BP_ON2_BITS RX_BP_ONN_BITS 1222 #define GMX0_RX_BP_OFF2_BITS RX_BP_OFFN_BITS 1223 #define GMX0_TX_PRTS_BITS TX_PRTS_BITS 1224 #define GMX0_TX_IFG_BITS TX_IFG_BITS 1225 #define GMX0_TX_JAM_BITS TX_JAM_BITS 1226 #define GMX0_TX_COL_ATTEMPT_BITS TX_COL_ATTEMPT_BITS 1227 #define GMX0_TX_PAUSE_PKT_DMAC_BITS TX_PAUSE_PKT_DMAC_BITS 1228 #define GMX0_TX_PAUSE_PKT_TYPE_BITS TX_PAUSE_PKT_TYPE_BITS 1229 #define GMX0_TX_OVR_BP_BITS TX_OVR_BP_BITS 1230 #define GMX0_TX_BP_BITS TX_BP_BITS 1231 #define GMX0_TX_CORRUPT_BITS TX_CORRUPT_BITS 1232 #define GMX0_RX_PRT_INFO_BITS RX_PRT_INFO_BITS 1233 #define GMX0_TX_LFSR_BITS TX_LFSR_BITS 1234 #define GMX0_TX_INT_REG_BITS TX_INT_REG_BITS 1235 #define GMX0_TX_INT_EN_BITS TX_INT_EN_BITS 1236 #define GMX0_NXA_ADR_BITS NXA_ADR_BITS 1237 #define GMX0_BAD_REG_BITS BAD_REG_BITS 1238 #define GMX0_STAT_BP_BITS STAT_BP_BITS 1239 #define GMX0_TX_CLK_MSK0_BITS TX_CLK_MSKN_BITS 1240 #define GMX0_TX_CLK_MSK1_BITS TX_CLK_MSKN_BITS 1241 #define GMX0_TX_CLK_MSK2_BITS TX_CLK_MSKN_BITS 1242 #define GMX0_RX_TX_STATUS_BITS RX_TX_STATUS_BITS 1243 #define GMX0_INF_MODE_BITS INF_MODE_BITS 1244 1245 #endif /* _CN30XXGMXREG_H_ */ 1246