1 /* 2 * THIS FILE IS AUTOMATICALLY GENERATED 3 * DONT EDIT THIS FILE 4 */ 5 6 /* $OpenBSD: cn30xxnpireg.h,v 1.1 2011/06/16 11:22:30 syuu Exp $ */ 7 8 /* 9 * Copyright (c) 2007 Internet Initiative Japan, Inc. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * Cavium Networks OCTEON CN30XX Hardware Reference Manual 36 * CN30XX-HM-1.0 37 * 9.15 NPI Registers 38 */ 39 40 #ifndef _CN30XXNPIREG_H_ 41 #define _CN30XXNPIREG_H_ 42 43 #define MPI_CFG 0x0001070000001000ULL 44 45 #define NPI_RSL_INT_BLOCKS 0x00011f0000000000ULL 46 #define NPI_DBG_SELECT 0x00011f0000000008ULL 47 #define NPI_CTL_STATUS 0x00011f0000000010ULL 48 #define NPI_INT_SUM 0x00011f0000000018ULL 49 #define NPI_INT_ENB 0x00011f0000000020ULL 50 #define NPI_MEM_ACCESS_SUBID3 0x00011f0000000028ULL 51 #define NPI_MEM_ACCESS_SUBID4 0x00011f0000000030ULL 52 #define NPI_MEM_ACCESS_SUBID5 0x00011f0000000038ULL 53 #define NPI_MEM_ACCESS_SUBID6 0x00011f0000000040ULL 54 #define NPI_PCI_READ_CMD 0x00011f0000000048ULL 55 #define NPI_NUM_DESC_OUTPUT0 0x00011f0000000050ULL 56 #define NPI_BASE_ADDR_INPUT0 0x00011f0000000070ULL 57 #define NPI_SIZE_INPUT0 0x00011f0000000078ULL 58 #define PCI_READ_TIMEOUT 0x00011f00000000b0ULL 59 #define NPI_BASE_ADDR_OUTPUT0 0x00011f00000000b8ULL 60 #define NPI_PCI_BURST_SIZE 0x00011f00000000d8ULL 61 #define NPI_BUFF_SIZE_OUTPUT0 0x00011f00000000e0ULL 62 #define NPI_OUTPUT_CONTROL 0x00011f0000000100ULL 63 #define NPI_LOWP_IBUFF_SADDR 0x00011f0000000108ULL 64 #define NPI_HIGHP_IBUFF_SADDR 0x00011f0000000110ULL 65 #define NPI_LOWP_DBELL 0x00011f0000000118ULL 66 #define NPI_HIGHP_DBELL 0x00011f0000000120ULL 67 #define NPI_DMA_CONTROL 0x00011f0000000128ULL 68 #define NPI_PCI_INT_ARB_CFG 0x00011f0000000130ULL 69 #define NPI_INPUT_CONTROL 0x00011f0000000138ULL 70 #define NPI_DMA_LOWP_COUNTS 0x00011f0000000140ULL 71 #define NPI_DMA_HIGHP_COUNTS 0x00011f0000000148ULL 72 #define NPI_DMA_LOWP_NADDR 0x00011f0000000150ULL 73 #define NPI_DMA_HIGHP_NADDR 0x00011f0000000158ULL 74 #define NPI_P0_PAIR_CNTS 0x00011f0000000160ULL 75 #define NPI_P0_DBPAIR_ADDR 0x00011f0000000180ULL 76 #define NPI_P0_INSTR_CNTS 0x00011f00000001a0ULL 77 #define NPI_P0_INSTR_ADDR 0x00011f00000001c0ULL 78 #define NPI_WIN_READ_TO 0x00011f00000001e0ULL 79 #define DBG_DATA 0x00011f00000001e8ULL 80 #define NPI_PORT_BP_CONTROL 0x00011f00000001f0ULL 81 #define NPI_PORT32_INSTR_HDR 0x00011f00000001f8ULL 82 #define NPI_BIST_STATUS 0x00011f00000003f8ULL 83 84 #define NPI_MSI_RCV 0x00011f0000001190ULL 85 86 #define NPI_RSL_INT_BLOCKS_XXX_63_31 0xffffffff80000000ULL 87 #define NPI_RSL_INT_BLOCKS_IOB 0x0000000040000000ULL 88 #define NPI_RSL_INT_BLOCKS_XXX_29_23 0x000000003f800000ULL 89 #define NPI_RSL_INT_BLOCKS_ASX0 0x0000000000400000ULL 90 #define NPI_RSL_INT_BLOCKS_XXX_21 0x0000000000200000ULL 91 #define NPI_RSL_INT_BLOCKS_PIP 0x0000000000100000ULL 92 #define NPI_RSL_INT_BLOCKS_XXX_19_18 0x00000000000c0000ULL 93 #define NPI_RSL_INT_BLOCKS_LMC 0x0000000000020000ULL 94 #define NPI_RSL_INT_BLOCKS_L2C 0x0000000000010000ULL 95 #define NPI_RSL_INT_BLOCKS_XXX_15_13 0x000000000000e000ULL 96 #define NPI_RSL_INT_BLOCKS_POW 0x0000000000001000ULL 97 #define NPI_RSL_INT_BLOCKS_TIM 0x0000000000000800ULL 98 #define NPI_RSL_INT_BLOCKS_PKO 0x0000000000000400ULL 99 #define NPI_RSL_INT_BLOCKS_IPD 0x0000000000000200ULL 100 #define NPI_RSL_INT_BLOCKS_XXX_8_6 0x00000000000001c0ULL 101 #define NPI_RSL_INT_BLOCKS_FPA 0x0000000000000020ULL 102 #define NPI_RSL_INT_BLOCKS_XXX_4 0x0000000000000010ULL 103 #define NPI_RSL_INT_BLOCKS_NPI 0x0000000000000008ULL 104 #define NPI_RSL_INT_BLOCKS_GMX1 0x0000000000000004ULL 105 #define NPI_RSL_INT_BLOCKS_GMX0 0x0000000000000002ULL 106 #define NPI_RSL_INT_BLOCKS_MIO 0x0000000000000001ULL 107 108 #define NPI_DBG_SELECT_XXX_63_16 0xffffffffffff0000ULL 109 #define NPI_DBG_SELECT_DBG_SEL 0x000000000000ffffULL 110 111 #define NPI_CTL_STATUS_XXX_63 0x8000000000000000ULL 112 #define NPI_DBG_SELECT_DBG_SEL 0x000000000000ffffULL 113 114 #define NPI_CTL_STATUS_XXX_63 0x8000000000000000ULL 115 #define NPI_CTL_STATUS_CHIP_REV 0x7f80000000000000ULL 116 #define NPI_CTL_STATUS_DIS_PNIW 0x0040000000000000ULL 117 #define NPI_CTL_STATUS_SPR5 0x0020000000000000ULL 118 #define NPI_CTL_STATUS_SPR4 0x0010000000000000ULL 119 #define NPI_CTL_STATUS_SPR8 0x0008000000000000ULL 120 #define NPI_CTL_STATUS_OUT0_ENB 0x0004000000000000ULL 121 #define NPI_CTL_STATUS_SPR3 0x0002000000000000ULL 122 #define NPI_CTL_STATUS_SPR2 0x0001000000000000ULL 123 #define NPI_CTL_STATUS_SPR7 0x0000800000000000ULL 124 #define NPI_CTL_STATUS_INS0_ENB 0x0000400000000000ULL 125 #define NPI_CTL_STATUS_SPR1 0x0000200000000000ULL 126 #define NPI_CTL_STATUS_SPR0 0x0000100000000000ULL 127 #define NPI_CTL_STATUS_SPR6 0x0000080000000000ULL 128 #define NPI_CTL_STATUS_INS0_64B 0x0000040000000000ULL 129 #define NPI_CTL_STATUS_PCI_WDIS 0x0000020000000000ULL 130 #define NPI_CTL_STATUS_WAIT_COM 0x0000010000000000ULL 131 #define NPI_CTL_STATUS_SPARES1 0x000000e000000000ULL 132 #define NPI_CTL_STATUS_MAX_WORD 0x0000001f00000000ULL 133 #define NPI_CTL_STATUS_SPARES0 0x00000000fffffc00ULL 134 #define NPI_CTL_STATUS_TIMER 0x00000000000003ffULL 135 136 #define NPI_INT_SUM_XXX_63_62 0xc000000000000000ULL 137 #define NPI_INT_SUM_Q1_A_F 0x2000000000000000ULL 138 #define NPI_INT_SUM_Q1_S_E 0x1000000000000000ULL 139 #define NPI_INT_SUM_PDF_P_F 0x0800000000000000ULL 140 #define NPI_INT_SUM_PDF_P_E 0x0400000000000000ULL 141 #define NPI_INT_SUM_PCF_P_F 0x0200000000000000ULL 142 #define NPI_INT_SUM_PCF_P_E 0x0100000000000000ULL 143 #define NPI_INT_SUM_RDX_S_E 0x0080000000000000ULL 144 #define NPI_INT_SUM_RWX_S_E 0x0040000000000000ULL 145 #define NPI_INT_SUM_PNC_A_F 0x0020000000000000ULL 146 #define NPI_INT_SUM_PNC_S_F 0x0010000000000000ULL 147 #define NPI_INT_SUM_COM_A_F 0x0008000000000000ULL 148 #define NPI_INT_SUM_COM_S_E 0x0004000000000000ULL 149 #define NPI_INT_SUM_Q3_A_F 0x0002000000000000ULL 150 #define NPI_INT_SUM_Q3_S_E 0x0001000000000000ULL 151 #define NPI_INT_SUM_Q2_A_F 0x0000800000000000ULL 152 #define NPI_INT_SUM_Q2_S_E 0x0000400000000000ULL 153 #define NPI_INT_SUM_PCR_A_F 0x0000200000000000ULL 154 #define NPI_INT_SUM_PCR_S_E 0x0000100000000000ULL 155 #define NPI_INT_SUM_FCR_A_F 0x0000080000000000ULL 156 #define NPI_INT_SUM_FCR_S_E 0x0000040000000000ULL 157 #define NPI_INT_SUM_IOBDMA 0x0000020000000000ULL 158 #define NPI_INT_SUM_P_DPERR 0x0000010000000000ULL 159 #define NPI_INT_SUM_WIN_RTO 0x0000008000000000ULL 160 #define NPI_INT_SUM_SPR17 0x0000004000000000ULL 161 #define NPI_INT_SUM_SPR16 0x0000002000000000ULL 162 #define NPI_INT_SUM_SPR26 0x0000001000000000ULL 163 #define NPI_INT_SUM_IO_PPERR 0x0000000800000000ULL 164 #define NPI_INT_SUM_SPR15 0x0000000400000000ULL 165 #define NPI_INT_SUM_SPR14 0x0000000200000000ULL 166 #define NPI_INT_SUM_SPR25 0x0000000100000000ULL 167 #define NPI_INT_SUM_P0_PTOUT 0x0000000080000000ULL 168 #define NPI_INT_SUM_SPR13 0x0000000040000000ULL 169 #define NPI_INT_SUM_SPR12 0x0000000020000000ULL 170 #define NPI_INT_SUM_SPR24 0x0000000010000000ULL 171 #define NPI_INT_SUM_P0_PPERR 0x0000000008000000ULL 172 #define NPI_INT_SUM_SPR11 0x0000000004000000ULL 173 #define NPI_INT_SUM_SPR10 0x0000000002000000ULL 174 #define NPI_INT_SUM_SPR23 0x0000000001000000ULL 175 #define NPI_INT_SUM_G0_RTOUT 0x0000000000800000ULL 176 #define NPI_INT_SUM_SPR9 0x0000000000400000ULL 177 #define NPI_INT_SUM_SPR8 0x0000000000200000ULL 178 #define NPI_INT_SUM_SPR22 0x0000000000100000ULL 179 #define NPI_INT_SUM_P0_PERR 0x0000000000080000ULL 180 #define NPI_INT_SUM_SPR7 0x0000000000040000ULL 181 #define NPI_INT_SUM_SPR6 0x0000000000020000ULL 182 #define NPI_INT_SUM_SPR21 0x0000000000010000ULL 183 #define NPI_INT_SUM_P0_RTOUT 0x0000000000008000ULL 184 #define NPI_INT_SUM_SPR5 0x0000000000004000ULL 185 #define NPI_INT_SUM_SPR4 0x0000000000002000ULL 186 #define NPI_INT_SUM_SPR20 0x0000000000001000ULL 187 #define NPI_INT_SUM_IO_OVERF 0x0000000000000800ULL 188 #define NPI_INT_SUM_SPR3 0x0000000000000400ULL 189 #define NPI_INT_SUM_SPR2 0x0000000000000200ULL 190 #define NPI_INT_SUM_SPR19 0x0000000000000100ULL 191 #define NPI_INT_SUM_IO_RTOUT 0x0000000000000080ULL 192 #define NPI_INT_SUM_SPR1 0x0000000000000040ULL 193 #define NPI_INT_SUM_SPR0 0x0000000000000020ULL 194 #define NPI_INT_SUM_SPR18 0x0000000000000010ULL 195 #define NPI_INT_SUM_PO0_2SML 0x0000000000000008ULL 196 #define NPI_INT_SUM_PCI_RSL 0x0000000000000004ULL 197 #define NPI_INT_SUM_RML_TWO 0x0000000000000002ULL 198 #define NPI_INT_SUM_RML_RTO 0x0000000000000001ULL 199 200 #define NPI_INT_ENB_XXX_63_62 0xc000000000000000ULL 201 #define NPI_INT_ENB_Q1_A_F 0x2000000000000000ULL 202 #define NPI_INT_ENB_Q1_S_E 0x1000000000000000ULL 203 #define NPI_INT_ENB_PDF_P_F 0x0800000000000000ULL 204 #define NPI_INT_ENB_PDF_P_E 0x0400000000000000ULL 205 #define NPI_INT_ENB_PCF_P_F 0x0200000000000000ULL 206 #define NPI_INT_ENB_PCF_P_E 0x0100000000000000ULL 207 #define NPI_INT_ENB_RDX_S_E 0x0080000000000000ULL 208 #define NPI_INT_ENB_RWX_S_E 0x0040000000000000ULL 209 #define NPI_INT_ENB_PNC_A_F 0x0020000000000000ULL 210 #define NPI_INT_ENB_PNC_S_F 0x0010000000000000ULL 211 #define NPI_INT_ENB_COM_A_F 0x0008000000000000ULL 212 #define NPI_INT_ENB_COM_S_E 0x0004000000000000ULL 213 #define NPI_INT_ENB_Q3_A_F 0x0002000000000000ULL 214 #define NPI_INT_ENB_Q3_S_E 0x0001000000000000ULL 215 #define NPI_INT_ENB_Q2_A_F 0x0000800000000000ULL 216 #define NPI_INT_ENB_Q2_S_E 0x0000400000000000ULL 217 #define NPI_INT_ENB_PCR_A_F 0x0000200000000000ULL 218 #define NPI_INT_ENB_PCR_S_E 0x0000100000000000ULL 219 #define NPI_INT_ENB_FCR_A_F 0x0000080000000000ULL 220 #define NPI_INT_ENB_FCR_S_E 0x0000040000000000ULL 221 #define NPI_INT_ENB_IOBDMA 0x0000020000000000ULL 222 #define NPI_INT_ENB_P_DPERR 0x0000010000000000ULL 223 #define NPI_INT_ENB_WIN_RTO 0x0000008000000000ULL 224 #define NPI_INT_ENB_SPR17 0x0000004000000000ULL 225 #define NPI_INT_ENB_SPR16 0x0000002000000000ULL 226 #define NPI_INT_ENB_SPR26 0x0000001000000000ULL 227 #define NPI_INT_ENB_IO_PPERR 0x0000000800000000ULL 228 #define NPI_INT_ENB_SPR15 0x0000000400000000ULL 229 #define NPI_INT_ENB_SPR14 0x0000000200000000ULL 230 #define NPI_INT_ENB_SPR25 0x0000000100000000ULL 231 #define NPI_INT_ENB_P0_PTOUT 0x0000000080000000ULL 232 #define NPI_INT_ENB_SPR13 0x0000000040000000ULL 233 #define NPI_INT_ENB_SPR12 0x0000000020000000ULL 234 #define NPI_INT_ENB_SPR24 0x0000000010000000ULL 235 #define NPI_INT_ENB_P0_PPERR 0x0000000008000000ULL 236 #define NPI_INT_ENB_SPR11 0x0000000004000000ULL 237 #define NPI_INT_ENB_SPR10 0x0000000002000000ULL 238 #define NPI_INT_ENB_SPR23 0x0000000001000000ULL 239 #define NPI_INT_ENB_G0_RTOUT 0x0000000000800000ULL 240 #define NPI_INT_ENB_SPR9 0x0000000000400000ULL 241 #define NPI_INT_ENB_SPR8 0x0000000000200000ULL 242 #define NPI_INT_ENB_SPR22 0x0000000000100000ULL 243 #define NPI_INT_ENB_P0_PERR 0x0000000000080000ULL 244 #define NPI_INT_ENB_SPR7 0x0000000000040000ULL 245 #define NPI_INT_ENB_SPR6 0x0000000000020000ULL 246 #define NPI_INT_ENB_SPR21 0x0000000000010000ULL 247 #define NPI_INT_ENB_P0_RTOUT 0x0000000000008000ULL 248 #define NPI_INT_ENB_SPR5 0x0000000000004000ULL 249 #define NPI_INT_ENB_SPR4 0x0000000000002000ULL 250 #define NPI_INT_ENB_SPR20 0x0000000000001000ULL 251 #define NPI_INT_ENB_IO_OVERF 0x0000000000000800ULL 252 #define NPI_INT_ENB_SPR3 0x0000000000000400ULL 253 #define NPI_INT_ENB_SPR2 0x0000000000000200ULL 254 #define NPI_INT_ENB_SPR19 0x0000000000000100ULL 255 #define NPI_INT_ENB_IO_RTOUT 0x0000000000000080ULL 256 #define NPI_INT_ENB_SPR1 0x0000000000000040ULL 257 #define NPI_INT_ENB_SPR0 0x0000000000000020ULL 258 #define NPI_INT_ENB_SPR18 0x0000000000000010ULL 259 #define NPI_INT_ENB_PO0_2SML 0x0000000000000008ULL 260 #define NPI_INT_ENB_PCI_RSL 0x0000000000000004ULL 261 #define NPI_INT_ENB_RML_TWO 0x0000000000000002ULL 262 #define NPI_INT_ENB_RML_RTO 0x0000000000000001ULL 263 264 #define NPI_MEM_ACCESS_SUBIDX_XXX_63_38 0xffffffc000000000ULL 265 #define NPI_MEM_ACCESS_SUBIDX_SHORT 0x0000002000000000ULL 266 #define NPI_MEM_ACCESS_SUBIDX_NMERGE 0x0000001000000000ULL 267 #define NPI_MEM_ACCESS_SUBIDX_ESR 0x0000000c00000000ULL 268 #define NPI_MEM_ACCESS_SUBIDX_ESW 0x0000000300000000ULL 269 #define NPI_MEM_ACCESS_SUBIDX_NSR 0x0000000080000000ULL 270 #define NPI_MEM_ACCESS_SUBIDX_NSW 0x0000000040000000ULL 271 #define NPI_MEM_ACCESS_SUBIDX_ROR 0x0000000020000000ULL 272 #define NPI_MEM_ACCESS_SUBIDX_ROW 0x0000000010000000ULL 273 #define NPI_MEM_ACCESS_SUBIDX_BA 0x000000000fffffffULL 274 275 #define NPI_PCI_READ_CMD_XXX_63_11 0xfffffffffffff800ULL 276 #define NPI_PCI_READ_CMD_CMD_SIZE 0x00000000000007ffULL 277 278 #define NPI_NUM_DESC_OUTPUT0_XXX_63_32 0xffffffff00000000ULL 279 #define NPI_NUM_DESC_OUTPUT0_SIZE 0x00000000ffffffffULL 280 281 #define NPI_BASE_ADDR_INPUT0_BADDR 0xfffffffffffffff8ULL 282 #define NPI_BASE_ADDR_INPUT0_XXX_2_0 0x0000000000000007ULL 283 284 #define NPI_SIZE_INPUT0_XXX_63_32 0xffffffff00000000ULL 285 #define NPI_SIZE_INPUT0_SIZE 0x00000000ffffffffULL 286 287 #define PCI_READ_TIMEOUT_XXX_63_32 0xffffffff00000000ULL 288 #define PCI_READ_TIMEOUT_ENB 0x0000000080000000ULL 289 #define PCI_READ_TIMEOUT_CNT 0x000000007fffffffULL 290 291 #define NPI_BASE_ADDR_OUTPUT0_BADDR 0xfffffffffffffff8ULL 292 #define NPI_BASE_ADDR_OUTPUT0_XXX_2_0 0x0000000000000007ULL 293 294 #define NPI_PCI_BURST_SIZE_XXX_63_14 0xffffffffffffc000ULL 295 #define NPI_PCI_BURST_SIZE_WR_BRST 0x0000000000003f80ULL 296 #define NPI_PCI_BURST_SIZE_RD_BRST 0x000000000000007fULL 297 298 #define NPI_BUFF_SIZE_OUTPUT0_XXX_63_23 0xffffffffff800000ULL 299 #define NPI_BUFF_SIZE_OUTPUT0_ISIZE 0x00000000007f0000ULL 300 #define NPI_BUFF_SIZE_OUTPUT0_BSIZE 0x000000000000ffffULL 301 302 #define NPI_OUTPUT_CONTROL_XXX_63_48 0xffff000000000000ULL 303 #define NPI_OUTPUT_CONTROL_SPR5 0x0000e00000000000ULL 304 #define NPI_OUTPUT_CONTROL_P0_BMODE 0x0000100000000000ULL 305 #define NPI_OUTPUT_CONTROL_SPR4 0x00000fff00000000ULL 306 #define NPI_OUTPUT_CONTROL_O0_ES 0x00000000c0000000ULL 307 #define NPI_OUTPUT_CONTROL_O0_NS 0x0000000020000000ULL 308 #define NPI_OUTPUT_CONTROL_O0_RO 0x0000000010000000ULL 309 #define NPI_OUTPUT_CONTROL_SPR3 0x000000000e000000ULL 310 #define NPI_OUTPUT_CONTROL_O0_CSRM 0x0000000001000000ULL 311 #define NPI_OUTPUT_CONTROL_SPR2 0x0000000000f00000ULL 312 #define NPI_OUTPUT_CONTROL_SPR1 0x00000000000e0000ULL 313 #define NPI_OUTPUT_CONTROL_IPTR_O0 0x0000000000010000ULL 314 #define NPI_OUTPUT_CONTROL_SPR0 0x000000000000fff0ULL 315 #define NPI_OUTPUT_CONTROL_ESR_SL0 0x000000000000000cULL 316 #define NPI_OUTPUT_CONTROL_NSR_SL0 0x0000000000000002ULL 317 #define NPI_OUTPUT_CONTROL_ROR_SL0 0x0000000000000001ULL 318 319 #define NPI_LOWP_IBUFF_SADDR_XXX_63_36 0xfffffff000000000ULL 320 #define NPI_LOWP_IBUFF_SADDR_SADDR 0x0000000fffffffffULL 321 322 #define NPI_HIGHP_IBUFF_SADDR_XXX_63_36 0xfffffff000000000ULL 323 #define NPI_HIGHP_IBUFF_SADDR_SADDR 0x0000000fffffffffULL 324 325 #define NPI_LOWP_DBELL_XXX_63_16 0xffffffffffff0000ULL 326 #define NPI_LOWP_DBELL_DBELL 0x000000000000ffffULL 327 328 #define NPI_HIGHP_DBELL_XXX_63_16 0xffffffffffff0000ULL 329 #define NPI_HIGHP_DBELL_DBELL 0x000000000000ffffULL 330 331 #define NPI_DMA_CONTROL_XXX_63_36 0xfffffff000000000ULL 332 #define NPI_DMA_CONTROL_B0_LEND 0x0000000800000000ULL 333 #define NPI_DMA_CONTROL_DWB_DENB 0x0000000400000000ULL 334 #define NPI_DMA_CONTROL_DWB_ICHK 0x00000003fe000000ULL 335 #define NPI_DMA_CONTROL_FPA_QUE 0x0000000001c00000ULL 336 #define NPI_DMA_CONTROL_O_ADD1 0x0000000000200000ULL 337 #define NPI_DMA_CONTROL_O_RO 0x0000000000100000ULL 338 #define NPI_DMA_CONTROL_O_NS 0x0000000000080000ULL 339 #define NPI_DMA_CONTROL_O_ES 0x0000000000060000ULL 340 #define NPI_DMA_CONTROL_O_MODE 0x0000000000010000ULL 341 #define NPI_DMA_CONTROL_HP_ENB 0x0000000000008000ULL 342 #define NPI_DMA_CONTROL_LP_ENB 0x0000000000004000ULL 343 #define NPI_DMA_CONTROL_CSIZE 0x0000000000003fffULL 344 345 #define NPI_PCI_INT_ARB_CFG_XXX_63_5 0xffffffffffffffe0ULL 346 #define NPI_PCI_INT_ARB_CFG_EN 0x0000000000000010ULL 347 #define NPI_PCI_INT_ARB_CFG_PARK_MOD 0x0000000000000008ULL 348 #define NPI_PCI_INT_ARB_CFG_PARK_DEV 0x0000000000000007ULL 349 350 #define NPI_INPUT_CONTROL_XXX_63_22 0xffffffffffc00000ULL 351 #define NPI_INPUT_CONTROL_PBP_DHI 0x00000000003ffe00ULL 352 #define NPI_INPUT_CONTROL_D_NSR 0x0000000000000100ULL 353 #define NPI_INPUT_CONTROL_D_ESR 0x00000000000000c0ULL 354 #define NPI_INPUT_CONTROL_D_ROR 0x0000000000000020ULL 355 #define NPI_INPUT_CONTROL_USE_CSR 0x0000000000000010ULL 356 #define NPI_INPUT_CONTROL_NSR 0x0000000000000008ULL 357 #define NPI_INPUT_CONTROL_ESR 0x0000000000000006ULL 358 #define NPI_INPUT_CONTROL_ROR 0x0000000000000001ULL 359 360 #define NPI_DMA_LOWP_COUNTS_XXX_63_39 0xffffff8000000000ULL 361 #define NPI_DMA_LOWP_COUNTS_FCNT 0x0000007f00000000ULL 362 #define NPI_DMA_LOWP_COUNTS_DBELL 0x00000000ffffffffULL 363 364 #define NPI_DMA_HIGHP_COUNTS_XXX_63_39 0xffffff8000000000ULL 365 #define NPI_DMA_HIGHP_COUNTS_FCNT 0x0000007f00000000ULL 366 #define NPI_DMA_HIGHP_COUNTS_DBELL 0x00000000ffffffffULL 367 368 #define NPI_DMA_LOWP_NADDR_XXX_63_40 0xffffff0000000000ULL 369 #define NPI_DMA_LOWP_NADDR_STATE 0x000000f000000000ULL 370 #define NPI_DMA_LOWP_NADDR_ADDR 0x0000000fffffffffULL 371 372 #define NPI_DMA_HIGHP_NADDR_XXX_63_40 0xffffff0000000000ULL 373 #define NPI_DMA_HIGHP_NADDR_STATE 0x000000f000000000ULL 374 #define NPI_DMA_HIGHP_NADDR_ADDR 0x0000000fffffffffULL 375 376 #define NPI_P0_PAIR_CNTS_XXX_63_37 0xffffffe000000000ULL 377 #define NPI_P0_PAIR_CNTS_FCNT 0xffffffff00000000ULL 378 #define NPI_P0_PAIR_CNTS_AVAIL 0x00000000c0000000ULL 379 380 #define NPI_P0_DBPAIR_ADDR_XXX_63 0x8000000000000000ULL 381 #define NPI_P0_DBPAIR_ADDR_STATE 0x6000000000000000ULL 382 #define NPI_P0_DBPAIR_ADDR_NADDR 0x1fffffffffffffffULL 383 384 #define NPI_P0_INSTR_CNTS_XXX_63_38 0xffffffc000000000ULL 385 #define NPI_P0_INSTR_CNTS_FCNT 0x0000003f00000000ULL 386 #define NPI_P0_INSTR_CNTS_AVAIL 0x00000000ffffffffULL 387 388 #define NPI_P0_INSTR_ADDR_STATE 0xe000000000000000ULL 389 #define NPI_P0_INSTR_ADDR_NADDR 0x1fffffffffffffffULL 390 391 #define NPI_WIN_READ_TO_XXX_63_32 0xffffffff00000000ULL 392 #define NPI_WIN_READ_TO_TIME 0x00000000ffffffffULL 393 394 #define DBG_DATA_XXX_63_31 0xffffffff80000000ULL 395 #define DBG_DATA_PLL_MUL 0x0000000070000000ULL 396 #define DBG_DATA_XXX_27_23 0x000000000f800000ULL 397 #define DBG_DATA_C_MUL 0x00000000007c0000ULL 398 #define DBG_DATA_DSEL_EXT 0x0000000000020000ULL 399 #define DBG_DATA_DATA 0x000000000001ffffULL 400 401 #define NPI_PORT_BP_CONTROL_XXX_63_5 0xffffffffffffffe0ULL 402 #define NPI_PORT_BP_CONTROL_BP_ON 0x0000000000000010ULL 403 #define NPI_PORT_BP_CONTROL_ENB 0x000000000000000fULL 404 405 #define NPI_PORT32_INSTR_HDR_XXX_63_44 0xfffff00000000000ULL 406 #define NPI_PORT32_INSTR_HDR_PBP 0x0000080000000000ULL 407 #define NPI_PORT32_INSTR_HDR_XXX_42_38 0x000007c000000000ULL 408 #define NPI_PORT32_INSTR_HDR_RPARMODE 0x0000003000000000ULL 409 #define NPI_PORT32_INSTR_HDR_XXX_35 0x0000000800000000ULL 410 #define NPI_PORT32_INSTR_HDR_RSKP_LEN 0x00000007f0000000ULL 411 #define NPI_PORT32_INSTR_HDR_XXX_27_22 0x000000000fc00000ULL 412 #define NPI_PORT32_INSTR_HDR_USE_IHDR 0x0000000000200000ULL 413 #define NPI_PORT32_INSTR_HDR_XXX_20_16 0x00000000001f0000ULL 414 #define NPI_PORT32_INSTR_HDR_PAR_MODE 0x000000000000c000ULL 415 #define NPI_PORT32_INSTR_HDR_XXX_13 0x0000000000002000ULL 416 #define NPI_PORT32_INSTR_HDR_SKP_LEN 0x0000000000001fc0ULL 417 #define NPI_PORT32_INSTR_HDR_XXX_5_0 0x000000000000003fULL 418 419 #define NPI_BIST_STATUS_XXX_63_20 0xfffffffffff00000ULL 420 #define NPI_BIST_STATUS_CSR_BS 0x0000000000080000ULL 421 #define NPI_BIST_STATUS_DIF_BS 0x0000000000040000ULL 422 #define NPI_BIST_STATUS_RDP_BS 0x0000000000020000ULL 423 #define NPI_BIST_STATUS_PCNC_BS 0x0000000000010000ULL 424 #define NPI_BIST_STATUS_PCN_BS 0x0000000000008000ULL 425 #define NPI_BIST_STATUS_RDN_BS 0x0000000000004000ULL 426 #define NPI_BIST_STATUS_PCAC_BS 0x0000000000002000ULL 427 #define NPI_BIST_STATUS_PCAD_BS 0x0000000000001000ULL 428 #define NPI_BIST_STATUS_RDNL_BS 0x0000000000000800ULL 429 #define NPI_BIST_STATUS_PGF_BS 0x0000000000000400ULL 430 #define NPI_BIST_STATUS_PIG_BS 0x0000000000000200ULL 431 #define NPI_BIST_STATUS_POF0_BS 0x0000000000000100ULL 432 #define NPI_BIST_STATUS_POF1_BS 0x0000000000000080ULL 433 #define NPI_BIST_STATUS_POF2_BS 0x0000000000000040ULL 434 #define NPI_BIST_STATUS_POF3_BS 0x0000000000000020ULL 435 #define NPI_BIST_STATUS_POS_BS 0x0000000000000010ULL 436 #define NPI_BIST_STATUS_NUS_BS 0x0000000000000008ULL 437 #define NPI_BIST_STATUS_DOB_BS 0x0000000000000004ULL 438 #define NPI_BIST_STATUS_PDF_BS 0x0000000000000002ULL 439 #define NPI_BIST_STATUS_DPI_BS 0x0000000000000001ULL 440 441 #endif /* _CN30XXNPIREG_H_ */ 442