1 /* $OpenBSD: cn30xxpow.c,v 1.16 2017/12/05 15:26:47 visa Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 32 #include <machine/bus.h> 33 #include <machine/octeonvar.h> 34 35 #include <octeon/dev/iobusvar.h> 36 #include <octeon/dev/cn30xxpowreg.h> 37 #include <octeon/dev/cn30xxpowvar.h> 38 39 void cn30xxpow_bootstrap(struct octeon_config *); 40 41 void cn30xxpow_init(struct cn30xxpow_softc *); 42 void cn30xxpow_init_regs(struct cn30xxpow_softc *); 43 void cn30xxpow_config_int(struct cn30xxpow_softc *, int, 44 uint64_t, uint64_t, uint64_t); 45 46 struct cn30xxpow_softc cn30xxpow_softc; 47 48 /* -------------------------------------------------------------------------- */ 49 50 /* ---- operation primitive functions */ 51 52 /* 5.11.1 Load Operations */ 53 54 /* 5.11.2 IOBDMA Operations */ 55 56 /* 5.11.3 Store Operations */ 57 58 /* -------------------------------------------------------------------------- */ 59 60 /* ---- utility functions */ 61 62 void 63 cn30xxpow_work_request_async(uint64_t scraddr, uint64_t wait) 64 { 65 cn30xxpow_ops_get_work_iobdma(scraddr, wait); 66 } 67 68 uint64_t * 69 cn30xxpow_work_response_async(uint64_t scraddr) 70 { 71 uint64_t result; 72 73 octeon_synciobdma(); 74 result = octeon_cvmseg_read_8(scraddr); 75 76 return (result & POW_IOBDMA_GET_WORK_RESULT_NO_WORK) ? 77 NULL : 78 (uint64_t *)PHYS_TO_XKPHYS( 79 result & POW_IOBDMA_GET_WORK_RESULT_ADDR, CCA_CACHED); 80 } 81 82 /* -------------------------------------------------------------------------- */ 83 84 /* ---- initialization and configuration */ 85 86 void 87 cn30xxpow_bootstrap(struct octeon_config *mcp) 88 { 89 struct cn30xxpow_softc *sc = &cn30xxpow_softc; 90 91 sc->sc_regt = mcp->mc_iobus_bust; 92 /* XXX */ 93 94 cn30xxpow_init(sc); 95 } 96 97 void 98 cn30xxpow_config_int(struct cn30xxpow_softc *sc, int group, 99 uint64_t tc_thr, uint64_t ds_thr, uint64_t iq_thr) 100 { 101 uint64_t wq_int_thr; 102 103 wq_int_thr = 104 POW_WQ_INT_THRX_TC_EN | 105 (tc_thr << POW_WQ_INT_THRX_TC_THR_SHIFT) | 106 (ds_thr << POW_WQ_INT_THRX_DS_THR_SHIFT) | 107 (iq_thr << POW_WQ_INT_THRX_IQ_THR_SHIFT); 108 _POW_WR8(sc, POW_WQ_INT_THR0_OFFSET + (group * 8), wq_int_thr); 109 } 110 111 /* 112 * interrupt threshold configuration 113 * 114 * => DS / IQ 115 * => ... 116 * => time counter threshold 117 * => unit is 1msec 118 * => each group can set timeout 119 * => temporary disable bit 120 * => use CIU generic timer 121 */ 122 123 void 124 cn30xxpow_config(struct cn30xxpow_softc *sc, int group) 125 { 126 127 cn30xxpow_config_int(sc, group, 128 0x0f, /* TC */ 129 0x00, /* DS */ 130 0x00); /* IQ */ 131 } 132 133 void 134 cn30xxpow_init(struct cn30xxpow_softc *sc) 135 { 136 cn30xxpow_init_regs(sc); 137 138 sc->sc_int_pc_base = 10000; 139 cn30xxpow_config_int_pc(sc, sc->sc_int_pc_base); 140 } 141 142 void 143 cn30xxpow_init_regs(struct cn30xxpow_softc *sc) 144 { 145 int status; 146 147 status = bus_space_map(sc->sc_regt, POW_BASE, POW_SIZE, 0, 148 &sc->sc_regh); 149 if (status != 0) 150 panic("can't map %s space", "pow register"); 151 } 152