1 /* 2 * THIS FILE IS AUTOMATICALLY GENERATED 3 * DONT EDIT THIS FILE 4 */ 5 6 /* $OpenBSD: cn30xxsmireg.h,v 1.2 2017/05/02 13:26:49 visa Exp $ */ 7 8 /* 9 * Copyright (c) 2007 Internet Initiative Japan, Inc. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * Cavium Networks OCTEON CN30XX Hardware Reference Manual 36 * CN30XX-HM-1.0 37 * 18.3 SMI Registers 38 */ 39 40 #ifndef _CN30XXSMIREG_H_ 41 #define _CN30XXSMIREG_H_ 42 43 #define SMI_CMD_OFFSET 0x00ULL 44 #define SMI_WR_DAT_OFFSET 0x08ULL 45 #define SMI_RD_DAT_OFFSET 0x10ULL 46 #define SMI_CLK_OFFSET 0x18ULL 47 #define SMI_EN_OFFSET 0x20ULL 48 49 /* SMI CMD */ 50 #define SMI_CMD_63_17 0xfffffffffffe0000ULL 51 #define SMI_CMD_PHY_OP 0x0000000000010000ULL 52 #define SMI_CMD_15_13 0x000000000000e000ULL 53 #define SMI_CMD_PHY_ADR 0x0000000000001f00ULL 54 #define SMI_CMD_PHY_ADR_SHIFT 8 55 #define SMI_CMD_7_5 0x00000000000000e0ULL 56 #define SMI_CMD_REG_ADR 0x000000000000001fULL 57 #define SMI_CMD_REG_ADR_SHIFT 0 58 59 /* SMI_WR_DAT */ 60 #define SMI_WR_DAT_63_18 0xfffffffffffc0000ULL 61 #define SMI_WR_DAT_PENDING 0x0000000000020000ULL 62 #define SMI_WR_DAT_VAL 0x0000000000010000ULL 63 #define SMI_WR_DAT_DAT 0x000000000000ffffULL 64 65 /* SMI_RD_DAT */ 66 #define SMI_RD_DAT_63_18 0xfffffffffffc0000ULL 67 #define SMI_RD_DAT_PENDING 0x0000000000020000ULL 68 #define SMI_RD_DAT_VAL 0x0000000000010000ULL 69 #define SMI_RD_DAT_DAT 0x000000000000ffffULL 70 71 /* SMI_CLK */ 72 #define SMI_CLK_63_21 0xffffffffffe00000ULL 73 #define SMI_CLK_SAMPLE_HI 0x00000000001f0000ULL 74 #define SMI_CLK_15_14 0x000000000000c000ULL 75 #define SMI_CLK_CLK_IDLE 0x0000000000002000ULL 76 #define SMI_CLK_PREAMBLE 0x0000000000001000ULL 77 #define SMI_CLK_SAMPLE 0x0000000000000f00ULL 78 #define SMI_CLK_PHASE 0x00000000000000ffULL 79 80 /* SMI_EN */ 81 #define SMI_EN_63_1 0xfffffffffffffffeULL 82 #define SMI_EN_EN 0x0000000000000001ULL 83 84 /* XXX */ 85 86 #endif /* _CN30XXSMIREG_H_ */ 87