1 /* $OpenBSD: octmmc.c,v 1.14 2019/10/07 22:40:35 cheloha Exp $ */ 2 3 /* 4 * Copyright (c) 2016, 2017 Visa Hankala 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* Driver for OCTEON MMC host controller. */ 20 21 #include <sys/param.h> 22 #include <sys/systm.h> 23 #include <sys/device.h> 24 #include <sys/endian.h> 25 #include <sys/malloc.h> 26 #include <sys/mutex.h> 27 #include <sys/rwlock.h> 28 #include <sys/kernel.h> 29 30 #include <dev/ofw/fdt.h> 31 #include <dev/ofw/ofw_gpio.h> 32 #include <dev/ofw/openfirm.h> 33 #include <dev/sdmmc/sdmmcchip.h> 34 #include <dev/sdmmc/sdmmcvar.h> 35 #include <dev/sdmmc/sdmmc_ioreg.h> 36 37 #include <mips64/cache.h> 38 39 #include <machine/bus.h> 40 #include <machine/fdt.h> 41 #include <machine/octeonreg.h> 42 #include <machine/octeonvar.h> 43 #include <machine/octeon_model.h> 44 45 #include <octeon/dev/octmmcreg.h> 46 47 #define OCTMMC_BLOCK_SIZE 512 48 #define OCTMMC_CMD_TIMEOUT 5 /* in seconds */ 49 #define OCTMMC_MAX_DMASEG MIN(MAXPHYS, (1u << 18)) 50 #define OCTMMC_MAX_NDMASEG_6130 1 51 #define OCTMMC_MAX_NDMASEG_7890 16 52 #define OCTMMC_MAX_FREQ 52000 /* in kHz */ 53 #define OCTMMC_MAX_BUSES 4 54 #define OCTMMC_MAX_INTRS 4 55 56 #define DEF_STS_MASK 0xe4390080ul 57 #define PIO_STS_MASK 0x00b00000ul 58 59 #define MMC_RD_8(sc, reg) \ 60 bus_space_read_8((sc)->sc_iot, (sc)->sc_mmc_ioh, (reg)) 61 #define MMC_WR_8(sc, reg, val) \ 62 bus_space_write_8((sc)->sc_iot, (sc)->sc_mmc_ioh, (reg), (val)) 63 #define DMA_WR_8(sc, reg, val) \ 64 bus_space_write_8((sc)->sc_iot, (sc)->sc_dma_ioh, (reg), (val)) 65 #define FIFO_WR_8(sc, reg, val) \ 66 bus_space_write_8((sc)->sc_iot, (sc)->sc_fifo_ioh, (reg), (val)) 67 68 #define divround(n, d) (((n) + (d) / 2) / (d)) 69 70 struct octmmc_softc; 71 72 struct octmmc_bus { 73 struct octmmc_softc *bus_hc; 74 struct device *bus_sdmmc; 75 uint32_t bus_id; 76 uint32_t bus_cmd_skew; 77 uint32_t bus_dat_skew; 78 uint32_t bus_max_freq; /* in kHz */ 79 uint64_t bus_switch; 80 uint64_t bus_rca; 81 uint64_t bus_wdog; 82 uint32_t bus_cd_gpio[3]; 83 }; 84 85 struct octmmc_softc { 86 struct device sc_dev; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_mmc_ioh; 89 bus_space_handle_t sc_dma_ioh; 90 bus_space_handle_t sc_fifo_ioh; 91 bus_dma_tag_t sc_dmat; 92 bus_dmamap_t sc_dma_data; 93 caddr_t sc_bounce_buf; 94 bus_dma_segment_t sc_bounce_seg; 95 void *sc_ihs[OCTMMC_MAX_INTRS]; 96 int sc_nihs; 97 98 struct octmmc_bus sc_buses[OCTMMC_MAX_BUSES]; 99 struct octmmc_bus *sc_current_bus; 100 101 uint64_t sc_current_switch; 102 uint64_t sc_intr_status; 103 struct mutex sc_intr_mtx; 104 105 int sc_hwrev; 106 #define OCTMMC_HWREV_6130 0 107 #define OCTMMC_HWREV_7890 1 108 }; 109 110 int octmmc_match(struct device *, void *, void *); 111 void octmmc_attach(struct device *, struct device *, void *); 112 113 int octmmc_host_reset(sdmmc_chipset_handle_t); 114 uint32_t octmmc_host_ocr(sdmmc_chipset_handle_t); 115 int octmmc_host_maxblklen(sdmmc_chipset_handle_t); 116 int octmmc_card_detect(sdmmc_chipset_handle_t); 117 int octmmc_bus_width(sdmmc_chipset_handle_t, int); 118 int octmmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 119 int octmmc_bus_clock(sdmmc_chipset_handle_t, int, int); 120 void octmmc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 121 122 void octmmc_exec_dma(struct octmmc_bus *, struct sdmmc_command *); 123 void octmmc_exec_pio(struct octmmc_bus *, struct sdmmc_command *); 124 125 void octmmc_acquire(struct octmmc_bus *); 126 void octmmc_release(struct octmmc_bus *); 127 128 paddr_t octmmc_dma_load_6130(struct octmmc_softc *, struct sdmmc_command *); 129 void octmmc_dma_load_7890(struct octmmc_softc *, struct sdmmc_command *); 130 void octmmc_dma_unload_6130(struct octmmc_softc *, paddr_t); 131 void octmmc_dma_unload_7890(struct octmmc_softc *); 132 uint64_t octmmc_crtype_fixup(struct sdmmc_command *); 133 void octmmc_get_response(struct octmmc_softc *, struct sdmmc_command *); 134 int octmmc_init_bus(struct octmmc_bus *); 135 int octmmc_intr(void *); 136 int octmmc_wait_intr(struct octmmc_softc *, uint64_t, int); 137 138 const struct cfattach octmmc_ca = { 139 sizeof(struct octmmc_softc), octmmc_match, octmmc_attach 140 }; 141 142 struct cfdriver octmmc_cd = { 143 NULL, "octmmc", DV_DULL 144 }; 145 146 struct sdmmc_chip_functions octmmc_funcs = { 147 .host_reset = octmmc_host_reset, 148 .host_ocr = octmmc_host_ocr, 149 .host_maxblklen = octmmc_host_maxblklen, 150 .card_detect = octmmc_card_detect, 151 .bus_power = octmmc_bus_power, 152 .bus_clock = octmmc_bus_clock, 153 .bus_width = octmmc_bus_width, 154 .exec_command = octmmc_exec_command, 155 }; 156 157 static const int octmmc_6130_interrupts[] = { 0, 1, -1 }; 158 static const int octmmc_7890_interrupts[] = { 1, 2, 3, 4, -1 }; 159 160 struct rwlock octmmc_lock = RWLOCK_INITIALIZER("octmmclk"); 161 162 int 163 octmmc_match(struct device *parent, void *match, void *aux) 164 { 165 struct fdt_attach_args *fa = aux; 166 167 return OF_is_compatible(fa->fa_node, "cavium,octeon-6130-mmc") || 168 OF_is_compatible(fa->fa_node, "cavium,octeon-7890-mmc"); 169 } 170 171 void 172 octmmc_attach(struct device *parent, struct device *self, void *aux) 173 { 174 struct sdmmcbus_attach_args saa; 175 struct fdt_attach_args *fa = aux; 176 struct octmmc_softc *sc = (struct octmmc_softc *)self; 177 struct octmmc_bus *bus; 178 void *ih; 179 const int *interrupts; 180 uint64_t reg; 181 uint32_t bus_id, bus_width; 182 int i, node; 183 int maxsegs, rsegs; 184 185 if (OF_is_compatible(fa->fa_node, "cavium,octeon-7890-mmc")) { 186 sc->sc_hwrev = OCTMMC_HWREV_7890; 187 interrupts = octmmc_7890_interrupts; 188 maxsegs = OCTMMC_MAX_NDMASEG_7890; 189 } else { 190 sc->sc_hwrev = OCTMMC_HWREV_6130; 191 interrupts = octmmc_6130_interrupts; 192 maxsegs = OCTMMC_MAX_NDMASEG_6130; 193 } 194 195 if (fa->fa_nreg < 2) { 196 printf(": expected 2 IO spaces, got %d\n", fa->fa_nreg); 197 return; 198 } 199 200 sc->sc_iot = fa->fa_iot; 201 sc->sc_dmat = fa->fa_dmat; 202 if (bus_space_map(sc->sc_iot, fa->fa_reg[0].addr, fa->fa_reg[0].size, 0, 203 &sc->sc_mmc_ioh)) { 204 printf(": could not map MMC registers\n"); 205 goto error; 206 } 207 if (bus_space_map(sc->sc_iot, fa->fa_reg[1].addr, fa->fa_reg[1].size, 0, 208 &sc->sc_dma_ioh)) { 209 printf(": could not map DMA registers\n"); 210 goto error; 211 } 212 if (sc->sc_hwrev == OCTMMC_HWREV_7890 && 213 bus_space_map(sc->sc_iot, fa->fa_reg[1].addr - 214 MIO_EMM_DMA_FIFO_REGSIZE, MIO_EMM_DMA_FIFO_REGSIZE, 0, 215 &sc->sc_fifo_ioh)) { 216 printf(": could not map FIFO registers\n"); 217 goto error; 218 } 219 if (bus_dmamem_alloc(sc->sc_dmat, OCTMMC_MAX_DMASEG, 0, 0, 220 &sc->sc_bounce_seg, 1, &rsegs, BUS_DMA_NOWAIT)) { 221 printf(": could not allocate bounce buffer\n"); 222 goto error; 223 } 224 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_bounce_seg, rsegs, 225 OCTMMC_MAX_DMASEG, &sc->sc_bounce_buf, 226 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) { 227 printf(": could not map bounce buffer\n"); 228 goto error_free; 229 } 230 if (bus_dmamap_create(sc->sc_dmat, OCTMMC_MAX_DMASEG, maxsegs, 231 OCTMMC_MAX_DMASEG, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 232 &sc->sc_dma_data)) { 233 printf(": could not create data dmamap\n"); 234 goto error_unmap; 235 } 236 237 /* Disable all buses. */ 238 reg = MMC_RD_8(sc, MIO_EMM_CFG); 239 reg &= ~((1u << OCTMMC_MAX_BUSES) - 1); 240 MMC_WR_8(sc, MIO_EMM_CFG, reg); 241 242 /* Clear any pending interrupts. */ 243 reg = MMC_RD_8(sc, MIO_EMM_INT); 244 MMC_WR_8(sc, MIO_EMM_INT, reg); 245 246 for (i = 0; interrupts[i] != -1; i++) { 247 KASSERT(i < OCTMMC_MAX_INTRS); 248 ih = octeon_intr_establish_fdt_idx(fa->fa_node, interrupts[i], 249 IPL_SDMMC | IPL_MPSAFE, octmmc_intr, sc, DEVNAME(sc)); 250 if (ih == NULL) { 251 printf(": could not establish interrupt %d\n", i); 252 goto error_intr; 253 } 254 sc->sc_ihs[i] = ih; 255 sc->sc_nihs++; 256 } 257 258 printf("\n"); 259 260 sc->sc_current_bus = NULL; 261 sc->sc_current_switch = ~0ull; 262 263 mtx_init(&sc->sc_intr_mtx, IPL_SDMMC); 264 265 for (node = OF_child(fa->fa_node); node != 0; node = OF_peer(node)) { 266 if (!OF_is_compatible(node, "cavium,octeon-6130-mmc-slot")) 267 continue; 268 bus_id = OF_getpropint(node, "reg", (uint32_t)-1); 269 if (bus_id >= OCTMMC_MAX_BUSES) 270 continue; 271 272 bus = &sc->sc_buses[bus_id]; 273 bus->bus_hc = sc; 274 bus->bus_id = bus_id; 275 bus->bus_cmd_skew = OF_getpropint(node, 276 "cavium,cmd-clk-skew", 0); 277 bus->bus_dat_skew = OF_getpropint(node, 278 "cavium,dat-clk-skew", 0); 279 280 bus->bus_max_freq = OF_getpropint(node, 281 "spi-max-frequency", 0) / 1000; 282 if (bus->bus_max_freq == 0 || 283 bus->bus_max_freq > OCTMMC_MAX_FREQ) 284 bus->bus_max_freq = OCTMMC_MAX_FREQ; 285 286 bus_width = OF_getpropint(node, "bus-width", 0); 287 if (bus_width == 0) 288 bus_width = OF_getpropint(node, 289 "cavium,bus-max-width", 8); 290 291 OF_getpropintarray(node, "cd-gpios", bus->bus_cd_gpio, 292 sizeof(bus->bus_cd_gpio)); 293 if (bus->bus_cd_gpio[0] != 0) 294 gpio_controller_config_pin(bus->bus_cd_gpio, 295 GPIO_CONFIG_INPUT); 296 297 if (octmmc_init_bus(bus)) { 298 printf("%s: could not init bus %d\n", DEVNAME(sc), 299 bus_id); 300 continue; 301 } 302 303 memset(&saa, 0, sizeof(saa)); 304 saa.saa_busname = "sdmmc"; 305 saa.sct = &octmmc_funcs; 306 saa.sch = bus; 307 saa.caps = SMC_CAPS_MMC_HIGHSPEED; 308 if (bus_width >= 8) 309 saa.caps |= SMC_CAPS_8BIT_MODE; 310 if (bus_width >= 4) 311 saa.caps |= SMC_CAPS_4BIT_MODE; 312 313 bus->bus_sdmmc = config_found(&sc->sc_dev, &saa, NULL); 314 if (bus->bus_sdmmc == NULL) 315 printf("%s: bus %d: could not attach sdmmc\n", 316 DEVNAME(sc), bus_id); 317 } 318 return; 319 320 error_intr: 321 for (i = 0; i < sc->sc_nihs; i++) 322 octeon_intr_disestablish_fdt(sc->sc_ihs[i]); 323 error_unmap: 324 bus_dmamem_unmap(sc->sc_dmat, sc->sc_bounce_buf, OCTMMC_MAX_DMASEG); 325 error_free: 326 bus_dmamem_free(sc->sc_dmat, &sc->sc_bounce_seg, rsegs); 327 error: 328 if (sc->sc_dma_data != NULL) 329 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dma_data); 330 if (sc->sc_fifo_ioh != 0) 331 bus_space_unmap(sc->sc_iot, sc->sc_fifo_ioh, 332 MIO_EMM_DMA_FIFO_REGSIZE); 333 if (sc->sc_dma_ioh != 0) 334 bus_space_unmap(sc->sc_iot, sc->sc_dma_ioh, fa->fa_reg[1].size); 335 if (sc->sc_mmc_ioh != 0) 336 bus_space_unmap(sc->sc_iot, sc->sc_mmc_ioh, fa->fa_reg[0].size); 337 } 338 339 void 340 octmmc_acquire(struct octmmc_bus *bus) 341 { 342 struct octmmc_softc *sc = bus->bus_hc; 343 uint64_t period, sample; 344 345 splassert(IPL_SDMMC); 346 347 rw_enter_write(&octmmc_lock); 348 349 /* Acquire the bootbus. */ 350 octeon_xkphys_write_8(MIO_BOOT_CFG, 0); 351 352 if (sc->sc_current_bus == bus && 353 sc->sc_current_switch == bus->bus_switch) 354 return; 355 356 /* Save relative card address. */ 357 if (sc->sc_current_bus != NULL) 358 sc->sc_current_bus->bus_rca = MMC_RD_8(sc, MIO_EMM_RCA); 359 360 sc->sc_current_bus = NULL; 361 sc->sc_current_switch = ~0ull; 362 363 /* Set bus parameters. */ 364 MMC_WR_8(sc, MIO_EMM_SWITCH, bus->bus_switch & 365 ~MIO_EMM_SWITCH_BUS_ID); 366 MMC_WR_8(sc, MIO_EMM_SWITCH, bus->bus_switch); 367 368 /* Set relative card address. */ 369 MMC_WR_8(sc, MIO_EMM_RCA, bus->bus_rca); 370 371 /* Set command timeout. */ 372 MMC_WR_8(sc, MIO_EMM_WDOG, bus->bus_wdog); 373 374 /* Set sampling skew parameters. */ 375 period = 1000000000000ull / octeon_ioclock_speed(); 376 sample = (divround(bus->bus_cmd_skew, period) << 377 MIO_EMM_SAMPLE_CMD_CNT_SHIFT) & 378 MIO_EMM_SAMPLE_CMD_CNT; 379 sample |= (divround(bus->bus_dat_skew, period) << 380 MIO_EMM_SAMPLE_DAT_CNT_SHIFT) & 381 MIO_EMM_SAMPLE_DAT_CNT; 382 MMC_WR_8(bus->bus_hc, MIO_EMM_SAMPLE, sample); 383 384 sc->sc_current_bus = bus; 385 sc->sc_current_switch = bus->bus_switch; 386 return; 387 } 388 389 void 390 octmmc_release(struct octmmc_bus *bus) 391 { 392 rw_exit_write(&octmmc_lock); 393 } 394 395 int 396 octmmc_init_bus(struct octmmc_bus *bus) 397 { 398 struct octmmc_softc *sc = bus->bus_hc; 399 uint64_t init_freq = SDMMC_SDCLK_400KHZ; 400 uint64_t period; 401 uint64_t reg; 402 int s; 403 404 period = divround(octeon_ioclock_speed(), init_freq * 1000 * 2); 405 if (period > MIO_EMM_SWITCH_CLK_MAX) 406 period = MIO_EMM_SWITCH_CLK_MAX; 407 408 /* Set initial parameters. */ 409 bus->bus_switch = (uint64_t)bus->bus_id << MIO_EMM_SWITCH_BUS_ID_SHIFT; 410 bus->bus_switch |= 10ull << MIO_EMM_SWITCH_POWER_CLASS_SHIFT; 411 bus->bus_switch |= period << MIO_EMM_SWITCH_CLK_HI_SHIFT; 412 bus->bus_switch |= period << MIO_EMM_SWITCH_CLK_LO_SHIFT; 413 bus->bus_rca = 1; 414 415 /* Make hardware timeout happen before timeout in software. */ 416 bus->bus_wdog = init_freq * 900 * OCTMMC_CMD_TIMEOUT; 417 if (bus->bus_wdog > MIO_EMM_WDOG_CLK_CNT) 418 bus->bus_wdog = MIO_EMM_WDOG_CLK_CNT; 419 420 s = splsdmmc(); 421 422 /* Enable the bus. */ 423 reg = MMC_RD_8(sc, MIO_EMM_CFG); 424 reg |= 1u << bus->bus_id; 425 MMC_WR_8(sc, MIO_EMM_CFG, reg); 426 427 octmmc_acquire(bus); 428 429 /* 430 * Enable interrupts. 431 * 432 * The mask register is present only on the revision 6130 controller 433 * where interrupt causes share an interrupt vector. 434 * The 7890 controller has a separate vector for each interrupt cause. 435 */ 436 if (sc->sc_hwrev == OCTMMC_HWREV_6130) { 437 MMC_WR_8(sc, MIO_EMM_INT_EN, 438 MIO_EMM_INT_CMD_ERR | MIO_EMM_INT_CMD_DONE | 439 MIO_EMM_INT_DMA_ERR | MIO_EMM_INT_DMA_DONE); 440 } 441 442 MMC_WR_8(sc, MIO_EMM_STS_MASK, DEF_STS_MASK); 443 444 octmmc_release(bus); 445 446 splx(s); 447 448 return 0; 449 } 450 451 int 452 octmmc_intr(void *arg) 453 { 454 struct octmmc_softc *sc = arg; 455 uint64_t isr; 456 457 /* Get and acknowledge pending interrupts. */ 458 isr = MMC_RD_8(sc, MIO_EMM_INT); 459 if (isr == 0) 460 return 0; 461 MMC_WR_8(sc, MIO_EMM_INT, isr); 462 463 if (ISSET(isr, MIO_EMM_INT_CMD_DONE) || 464 ISSET(isr, MIO_EMM_INT_CMD_ERR) || 465 ISSET(isr, MIO_EMM_INT_DMA_DONE) || 466 ISSET(isr, MIO_EMM_INT_DMA_ERR)) { 467 mtx_enter(&sc->sc_intr_mtx); 468 sc->sc_intr_status |= isr; 469 wakeup(&sc->sc_intr_status); 470 mtx_leave(&sc->sc_intr_mtx); 471 } 472 473 return 1; 474 } 475 476 int 477 octmmc_host_reset(sdmmc_chipset_handle_t sch) 478 { 479 struct octmmc_bus *bus = sch; 480 int s; 481 482 /* Force reswitch. */ 483 bus->bus_hc->sc_current_switch = ~0ull; 484 485 s = splsdmmc(); 486 octmmc_acquire(bus); 487 octmmc_release(bus); 488 splx(s); 489 490 return 0; 491 } 492 493 uint32_t 494 octmmc_host_ocr(sdmmc_chipset_handle_t sch) 495 { 496 /* The hardware does only 3.3V. */ 497 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 498 } 499 500 int 501 octmmc_host_maxblklen(sdmmc_chipset_handle_t sch) 502 { 503 return OCTMMC_BLOCK_SIZE; 504 } 505 506 int 507 octmmc_card_detect(sdmmc_chipset_handle_t sch) 508 { 509 struct octmmc_bus *bus = sch; 510 511 if (bus->bus_cd_gpio[0] != 0) 512 return gpio_controller_get_pin(bus->bus_cd_gpio); 513 514 return 1; 515 } 516 517 int 518 octmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 519 { 520 if (ocr == 0) 521 octmmc_host_reset(sch); 522 523 return 0; 524 } 525 526 int 527 octmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 528 { 529 struct octmmc_bus *bus = sch; 530 uint64_t ioclock = octeon_ioclock_speed(); 531 uint64_t period; 532 533 if (freq == 0) 534 return 0; 535 if (freq > bus->bus_max_freq) 536 freq = bus->bus_max_freq; 537 period = divround(ioclock, freq * 1000 * 2); 538 if (period > MIO_EMM_SWITCH_CLK_MAX) 539 period = MIO_EMM_SWITCH_CLK_MAX; 540 541 bus->bus_switch &= ~MIO_EMM_SWITCH_CLK_HI; 542 bus->bus_switch &= ~MIO_EMM_SWITCH_CLK_LO; 543 bus->bus_switch |= period << MIO_EMM_SWITCH_CLK_HI_SHIFT; 544 bus->bus_switch |= period << MIO_EMM_SWITCH_CLK_LO_SHIFT; 545 546 /* Make hardware timeout happen before timeout in software. */ 547 bus->bus_wdog = freq * 900 * OCTMMC_CMD_TIMEOUT; 548 549 if (timing) 550 bus->bus_switch |= MIO_EMM_SWITCH_HS_TIMING; 551 else 552 bus->bus_switch &= ~MIO_EMM_SWITCH_HS_TIMING; 553 554 return 0; 555 } 556 557 int 558 octmmc_bus_width(sdmmc_chipset_handle_t sch, int width) 559 { 560 struct octmmc_bus *bus = sch; 561 uint64_t bus_width; 562 563 switch (width) { 564 case 1: 565 bus_width = 0; 566 break; 567 case 4: 568 bus_width = 1; 569 break; 570 case 8: 571 bus_width = 2; 572 break; 573 default: 574 return ENOTSUP; 575 } 576 bus->bus_switch &= ~MIO_EMM_SWITCH_BUS_WIDTH; 577 bus->bus_switch |= bus_width << MIO_EMM_SWITCH_BUS_WIDTH_SHIFT; 578 579 return 0; 580 } 581 582 void 583 octmmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 584 { 585 struct octmmc_bus *bus = sch; 586 587 /* 588 * Refuse SDIO probe. Proper SDIO operation is not possible 589 * because of a lack of card interrupt handling. 590 */ 591 if (cmd->c_opcode == SD_IO_SEND_OP_COND) { 592 cmd->c_error = ENOTSUP; 593 return; 594 } 595 596 /* 597 * The DMA mode can only do data block transfers. Other commands have 598 * to use the PIO mode. Single-block transfers can use PIO because 599 * it has low setup overhead. 600 */ 601 if (cmd->c_opcode == MMC_READ_BLOCK_MULTIPLE || 602 cmd->c_opcode == MMC_WRITE_BLOCK_MULTIPLE) 603 octmmc_exec_dma(bus, cmd); 604 else 605 octmmc_exec_pio(bus, cmd); 606 } 607 608 void 609 octmmc_exec_dma(struct octmmc_bus *bus, struct sdmmc_command *cmd) 610 { 611 struct octmmc_softc *sc = bus->bus_hc; 612 uint64_t dmacmd, status; 613 paddr_t locked_block = 0; 614 int bounce = 0; 615 int s; 616 617 if (cmd->c_datalen > OCTMMC_MAX_DMASEG) { 618 cmd->c_error = ENOMEM; 619 return; 620 } 621 622 s = splsdmmc(); 623 octmmc_acquire(bus); 624 625 /* 626 * Attempt to use the buffer directly for DMA. In case the region 627 * is not physically contiguous, bounce the data. 628 */ 629 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dma_data, cmd->c_data, 630 cmd->c_datalen, NULL, BUS_DMA_WAITOK)) { 631 cmd->c_error = bus_dmamap_load(sc->sc_dmat, sc->sc_dma_data, 632 sc->sc_bounce_buf, cmd->c_datalen, NULL, BUS_DMA_WAITOK); 633 if (cmd->c_error != 0) 634 goto dma_out; 635 636 bounce = 1; 637 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 638 memcpy(sc->sc_bounce_buf, cmd->c_data, cmd->c_datalen); 639 } 640 641 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_data, 0, cmd->c_datalen, 642 ISSET(cmd->c_flags, SCF_CMD_READ) ? BUS_DMASYNC_PREREAD : 643 BUS_DMASYNC_PREWRITE); 644 645 if (sc->sc_hwrev == OCTMMC_HWREV_7890) 646 octmmc_dma_load_7890(sc, cmd); 647 else 648 locked_block = octmmc_dma_load_6130(sc, cmd); 649 650 /* Set status mask. */ 651 MMC_WR_8(sc, MIO_EMM_STS_MASK, DEF_STS_MASK); 652 653 mtx_enter(&sc->sc_intr_mtx); 654 655 /* Prepare and issue the command. */ 656 dmacmd = MIO_EMM_DMA_DMA_VAL | MIO_EMM_DMA_MULTI | MIO_EMM_DMA_SECTOR; 657 dmacmd |= (uint64_t)bus->bus_id << MIO_EMM_DMA_BUS_ID_SHIFT; 658 dmacmd |= (uint64_t)(cmd->c_datalen / cmd->c_blklen) << 659 MIO_EMM_DMA_BLOCK_CNT_SHIFT; 660 dmacmd |= cmd->c_arg; 661 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 662 dmacmd |= MIO_EMM_DMA_RW; 663 MMC_WR_8(sc, MIO_EMM_DMA, dmacmd); 664 665 wait_intr: 666 cmd->c_error = octmmc_wait_intr(sc, MIO_EMM_INT_CMD_ERR | 667 MIO_EMM_INT_DMA_DONE | MIO_EMM_INT_DMA_ERR, OCTMMC_CMD_TIMEOUT); 668 669 status = MMC_RD_8(sc, MIO_EMM_RSP_STS); 670 671 /* Check DMA engine error. */ 672 if (ISSET(sc->sc_intr_status, MIO_EMM_INT_DMA_ERR)) { 673 printf("%s: dma error\n", bus->bus_sdmmc->dv_xname); 674 675 if (ISSET(status, MIO_EMM_RSP_STS_DMA_PEND)) { 676 /* Try to stop the DMA engine. */ 677 dmacmd = MMC_RD_8(sc, MIO_EMM_DMA); 678 dmacmd |= MIO_EMM_DMA_DMA_VAL | MIO_EMM_DMA_DAT_NULL; 679 dmacmd &= ~MIO_EMM_DMA_BUS_ID; 680 dmacmd |= (uint64_t)bus->bus_id << 681 MIO_EMM_DMA_BUS_ID_SHIFT; 682 MMC_WR_8(sc, MIO_EMM_DMA, dmacmd); 683 goto wait_intr; 684 } 685 cmd->c_error = EIO; 686 } 687 688 mtx_leave(&sc->sc_intr_mtx); 689 690 if (cmd->c_error != 0) 691 goto unload_dma; 692 693 /* Check command status. */ 694 if (((status & MIO_EMM_RSP_STS_CMD_IDX) >> 695 MIO_EMM_RSP_STS_CMD_IDX_SHIFT) != cmd->c_opcode || 696 ISSET(status, MIO_EMM_RSP_STS_BLK_CRC_ERR) || 697 ISSET(status, MIO_EMM_RSP_STS_DBUF_ERR) || 698 ISSET(status, MIO_EMM_RSP_STS_RSP_BAD_STS) || 699 ISSET(status, MIO_EMM_RSP_STS_RSP_CRC_ERR)) { 700 cmd->c_error = EIO; 701 goto unload_dma; 702 } 703 if (ISSET(status, MIO_EMM_RSP_STS_BLK_TIMEOUT) || 704 ISSET(status, MIO_EMM_RSP_STS_RSP_TIMEOUT)) { 705 cmd->c_error = ETIMEDOUT; 706 goto unload_dma; 707 } 708 709 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 710 octmmc_get_response(sc, cmd); 711 712 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_data, 0, cmd->c_datalen, 713 ISSET(cmd->c_flags, SCF_CMD_READ) ? BUS_DMASYNC_POSTREAD : 714 BUS_DMASYNC_POSTWRITE); 715 716 if (bounce && ISSET(cmd->c_flags, SCF_CMD_READ)) 717 memcpy(cmd->c_data, sc->sc_bounce_buf, cmd->c_datalen); 718 719 unload_dma: 720 if (sc->sc_hwrev == OCTMMC_HWREV_7890) 721 octmmc_dma_unload_7890(sc); 722 else 723 octmmc_dma_unload_6130(sc, locked_block); 724 725 bus_dmamap_unload(sc->sc_dmat, sc->sc_dma_data); 726 727 dma_out: 728 octmmc_release(bus); 729 splx(s); 730 } 731 732 void 733 octmmc_exec_pio(struct octmmc_bus *bus, struct sdmmc_command *cmd) 734 { 735 struct octmmc_softc *sc = bus->bus_hc; 736 unsigned char *ptr; 737 uint64_t index, piocmd, status, value; 738 unsigned int i; 739 int s; 740 741 if (cmd->c_datalen > OCTMMC_BLOCK_SIZE || 742 cmd->c_datalen % sizeof(uint64_t) != 0) { 743 cmd->c_error = EINVAL; 744 return; 745 } 746 747 s = splsdmmc(); 748 octmmc_acquire(bus); 749 750 /* If this is a write, copy data to the controller's buffer. */ 751 if (cmd->c_data != NULL && !ISSET(cmd->c_flags, SCF_CMD_READ)) { 752 /* Reset index and set autoincrement. */ 753 MMC_WR_8(sc, MIO_EMM_BUF_IDX, MIO_EMM_BUF_IDX_INC); 754 755 ptr = cmd->c_data; 756 for (i = 0; i < cmd->c_datalen / sizeof(value); i++) { 757 memcpy(&value, ptr, sizeof(value)); 758 MMC_WR_8(sc, MIO_EMM_BUF_DAT, value); 759 ptr += sizeof(value); 760 } 761 } 762 763 /* Set status mask. */ 764 MMC_WR_8(sc, MIO_EMM_STS_MASK, PIO_STS_MASK); 765 766 mtx_enter(&sc->sc_intr_mtx); 767 768 /* Issue the command. */ 769 piocmd = MIO_EMM_CMD_CMD_VAL; 770 piocmd |= (uint64_t)bus->bus_id << MIO_EMM_CMD_BUS_ID_SHIFT; 771 piocmd |= (uint64_t)cmd->c_opcode << MIO_EMM_CMD_CMD_IDX_SHIFT; 772 piocmd |= cmd->c_arg; 773 piocmd |= octmmc_crtype_fixup(cmd); 774 MMC_WR_8(sc, MIO_EMM_CMD, piocmd); 775 776 cmd->c_error = octmmc_wait_intr(sc, MIO_EMM_INT_CMD_DONE, 777 OCTMMC_CMD_TIMEOUT); 778 779 mtx_leave(&sc->sc_intr_mtx); 780 781 if (cmd->c_error != 0) 782 goto pio_out; 783 if (ISSET(sc->sc_intr_status, MIO_EMM_INT_CMD_ERR)) { 784 cmd->c_error = EIO; 785 goto pio_out; 786 } 787 788 /* Check command status. */ 789 status = MMC_RD_8(sc, MIO_EMM_RSP_STS); 790 if (((status & MIO_EMM_RSP_STS_CMD_IDX) >> 791 MIO_EMM_RSP_STS_CMD_IDX_SHIFT) != cmd->c_opcode || 792 ISSET(status, MIO_EMM_RSP_STS_BLK_CRC_ERR) || 793 ISSET(status, MIO_EMM_RSP_STS_DBUF_ERR) || 794 ISSET(status, MIO_EMM_RSP_STS_RSP_BAD_STS) || 795 ISSET(status, MIO_EMM_RSP_STS_RSP_CRC_ERR)) { 796 cmd->c_error = EIO; 797 goto pio_out; 798 } 799 if (ISSET(status, MIO_EMM_RSP_STS_BLK_TIMEOUT) || 800 ISSET(status, MIO_EMM_RSP_STS_RSP_TIMEOUT)) { 801 cmd->c_error = ETIMEDOUT; 802 goto pio_out; 803 } 804 805 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 806 octmmc_get_response(sc, cmd); 807 808 /* If this is a read, copy data from the controller's buffer. */ 809 if (cmd->c_data != NULL && ISSET(cmd->c_flags, SCF_CMD_READ)) { 810 /* Reset index, set autoincrement and select the buffer. */ 811 index = MIO_EMM_BUF_IDX_INC; 812 index |= (status >> MIO_EMM_RSP_STS_DBUF_SHIFT) << 813 MIO_EMM_BUF_IDX_BUF_NUM_SHIFT; 814 MMC_WR_8(sc, MIO_EMM_BUF_IDX, MIO_EMM_BUF_IDX_INC); 815 816 ptr = cmd->c_data; 817 for (i = 0; i < cmd->c_datalen / sizeof(value); i++) { 818 value = MMC_RD_8(sc, MIO_EMM_BUF_DAT); 819 memcpy(ptr, &value, sizeof(value)); 820 ptr += sizeof(value); 821 } 822 } 823 824 pio_out: 825 octmmc_release(bus); 826 splx(s); 827 } 828 829 paddr_t 830 octmmc_dma_load_6130(struct octmmc_softc *sc, struct sdmmc_command *cmd) 831 { 832 uint64_t dmacfg; 833 paddr_t locked_block = 0; 834 835 /* 836 * The DMA hardware has a silicon bug that can corrupt data 837 * (erratum EMMC-17978). As a workaround, Linux locks the second last 838 * block of a transfer into the L2 cache if the opcode is multi-block 839 * write and there are more than two data blocks to write. 840 * In Linux, it is not described under what circumstances 841 * the corruption can happen. 842 * Lacking better information, use the same workaround here. 843 */ 844 if (cmd->c_opcode == MMC_WRITE_BLOCK_MULTIPLE && 845 cmd->c_datalen > OCTMMC_BLOCK_SIZE * 2) { 846 locked_block = sc->sc_dma_data->dm_segs[0].ds_addr + 847 sc->sc_dma_data->dm_segs[0].ds_len - OCTMMC_BLOCK_SIZE * 2; 848 Octeon_lock_secondary_cache(curcpu(), locked_block, 849 OCTMMC_BLOCK_SIZE); 850 } 851 852 /* Set up the DMA engine. */ 853 dmacfg = MIO_NDF_DMA_CFG_EN; 854 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 855 dmacfg |= MIO_NDF_DMA_CFG_RW; 856 dmacfg |= (sc->sc_dma_data->dm_segs[0].ds_len / sizeof(uint64_t) - 1) 857 << MIO_NDF_DMA_CFG_SIZE_SHIFT; 858 dmacfg |= sc->sc_dma_data->dm_segs[0].ds_addr; 859 DMA_WR_8(sc, MIO_NDF_DMA_CFG, dmacfg); 860 861 return locked_block; 862 } 863 864 void 865 octmmc_dma_unload_6130(struct octmmc_softc *sc, paddr_t locked_block) 866 { 867 if (locked_block != 0) 868 Octeon_unlock_secondary_cache(curcpu(), locked_block, 869 OCTMMC_BLOCK_SIZE); 870 } 871 872 void 873 octmmc_dma_load_7890(struct octmmc_softc *sc, struct sdmmc_command *cmd) 874 { 875 bus_dma_segment_t *seg; 876 uint64_t fifocmd; 877 int i; 878 879 /* Enable the FIFO. */ 880 FIFO_WR_8(sc, MIO_EMM_DMA_FIFO_CFG, 0); 881 882 for (i = 0; i < sc->sc_dma_data->dm_nsegs; i++) { 883 seg = &sc->sc_dma_data->dm_segs[i]; 884 885 fifocmd = (seg->ds_len / sizeof(uint64_t) - 1) << 886 MIO_EMM_DMA_FIFO_CMD_SIZE_SHIFT; 887 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 888 fifocmd |= MIO_EMM_DMA_FIFO_CMD_RW; 889 if (i < sc->sc_dma_data->dm_nsegs - 1) 890 fifocmd |= MIO_EMM_DMA_FIFO_CMD_INTDIS; 891 892 /* Create a FIFO entry. */ 893 FIFO_WR_8(sc, MIO_EMM_DMA_FIFO_ADR, seg->ds_addr); 894 FIFO_WR_8(sc, MIO_EMM_DMA_FIFO_CMD, fifocmd); 895 } 896 } 897 898 void 899 octmmc_dma_unload_7890(struct octmmc_softc *sc) 900 { 901 /* Disable the FIFO. */ 902 FIFO_WR_8(sc, MIO_EMM_DMA_FIFO_CFG, MIO_EMM_DMA_FIFO_CFG_CLR); 903 } 904 905 /* 906 * The controller uses MMC command and response types by default. 907 * When the command and response types of an SD opcode differ from those 908 * of an overlapping MMC opcode, it is necessary to fix the types. 909 * Fixing is also needed with a non-overlapping SD opcode when the command 910 * is a data transfer (adtc) or if a response is expected. 911 */ 912 uint64_t 913 octmmc_crtype_fixup(struct sdmmc_command *cmd) 914 { 915 uint64_t cxor = 0; 916 uint64_t rxor = 0; 917 918 switch (cmd->c_opcode) { 919 case SD_IO_SEND_OP_COND: 920 cxor = 0x00; 921 rxor = 0x02; 922 break; 923 case SD_SEND_IF_COND: 924 /* The opcode overlaps with MMC_SEND_EXT_CSD. */ 925 if (SCF_CMD(cmd->c_flags) == SCF_CMD_BCR) { 926 cxor = 0x01; 927 rxor = 0x00; 928 } 929 break; 930 case SD_APP_OP_COND: 931 cxor = 0x00; 932 rxor = 0x03; 933 break; 934 case SD_IO_RW_DIRECT: 935 case SD_IO_RW_EXTENDED: 936 cxor = 0x00; 937 rxor = 0x01; 938 break; 939 } 940 return (cxor << MIO_EMM_CMD_CTYPE_XOR_SHIFT) | 941 (rxor << MIO_EMM_CMD_RTYPE_XOR_SHIFT); 942 } 943 944 void 945 octmmc_get_response(struct octmmc_softc *sc, struct sdmmc_command *cmd) 946 { 947 uint64_t hi, lo; 948 949 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 950 hi = MMC_RD_8(sc, MIO_EMM_RSP_HI); 951 lo = MMC_RD_8(sc, MIO_EMM_RSP_LO); 952 953 /* Discard the checksum. */ 954 lo = (lo >> 8) | (hi << 56); 955 hi >>= 8; 956 957 /* The stack expects long response in little endian order. */ 958 cmd->c_resp[0] = htole32(lo & 0xffffffffu); 959 cmd->c_resp[1] = htole32(lo >> 32); 960 cmd->c_resp[2] = htole32(hi & 0xffffffffu); 961 cmd->c_resp[3] = htole32(hi >> 32); 962 } else { 963 cmd->c_resp[0] = MMC_RD_8(sc, MIO_EMM_RSP_LO) >> 8; 964 } 965 } 966 967 int 968 octmmc_wait_intr(struct octmmc_softc *sc, uint64_t mask, int secs) 969 { 970 MUTEX_ASSERT_LOCKED(&sc->sc_intr_mtx); 971 972 mask |= MIO_EMM_INT_CMD_ERR | MIO_EMM_INT_DMA_ERR; 973 974 sc->sc_intr_status = 0; 975 while ((sc->sc_intr_status & mask) == 0) { 976 if (msleep_nsec(&sc->sc_intr_status, &sc->sc_intr_mtx, PWAIT, 977 "hcintr", SEC_TO_NSEC(secs)) == EWOULDBLOCK) 978 return ETIMEDOUT; 979 } 980 return 0; 981 } 982