1 /* $OpenBSD: octuctlreg.h,v 1.2 2017/07/25 11:01:28 jmatthew Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Jonathan Matthew <jmatthew@openbsd.org> 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _OCTUCTLREG_H_ 20 #define _OCTUCTLREG_H_ 21 22 /* 23 * UCTL - octeon II usb controller interface 24 */ 25 26 #define UCTL_CLK_TARGET_FREQ 130000000ull 27 28 #define UCTL_CLK_RST_CTL 0x00 29 #define UCTL_CLK_RST_CTL_HRST (1 << 0) 30 #define UCTL_CLK_RST_CTL_P_PRST (1 << 1) 31 #define UCTL_CLK_RST_CTL_P_POR (1 << 2) 32 #define UCTL_CLK_RST_CTL_P_COM_ON (1 << 3) 33 #define UCTL_CLK_RST_CTL_P_REFCLK_DIV_SHIFT 5 34 #define UCTL_CLK_RST_CTL_P_REFCLK_SEL_SHIFT 7 35 #define UCTL_CLK_RST_CTL_H_DIV_SHIFT 9 36 #define UCTL_CLK_RST_CTL_O_CLKDIV_EN (1 << 13) 37 #define UCTL_CLK_RST_CTL_H_CLKDIV_EN (1 << 14) 38 #define UCTL_CLK_RST_CTL_H_CLKDIV_RST (1 << 15) 39 #define UCTL_CLK_RST_CTL_H_CLKDIV_BYP (1 << 16) 40 #define UCTL_CLK_RST_CTL_O_CLKDIV_RST (1 << 17) 41 #define UCTL_CLK_RST_CTL_APP_START_CLK (1 << 18) 42 #define UCTL_CLK_RST_CTL_OHCI_SUSP_LGCY (1 << 19) 43 #define UCTL_CLK_RST_CTL_OHCI_SM (1 << 20) 44 #define UCTL_CLK_RST_CTL_OHCI_CLKCKTRST (1 << 21) 45 #define UCTL_CLK_RST_CTL_EHCI_SM (1 << 22) 46 47 #define UCTL_UPHY_STATUS 0x08 48 49 #define UCTL_UPHY_PORTX_STATUS 0x10 50 #define UCTL_UPHY_PORTX_STATUS_TXVREF_SHIFT 28 51 #define UCTL_UPHY_PORTX_STATUS_TXRISETUNE (1 << 27) 52 #define UCTL_UPHY_PORTX_STATUS_TXPREEMPHTUNE (1 << 26) 53 54 #define UCTL_IF_ENA 0x30 55 #define UCTL_IF_ENA_EN (1 << 0) 56 57 #define UCTL_EHCI_CTL 0x80 58 #define UCTL_EHCI_CTL_L2C_ADDR_MSB_MASK 0xff 59 #define UCTL_EHCI_CTL_L2C_ADDR_MSB_SHIFT 0 60 #define UCTL_EHCI_CTL_EHCI_64B_ADDR_EN (1 << 8) 61 #define UCTL_EHCI_CTL_L2C_DESC_EMOD_SHIFT 10 62 #define UCTL_EHCI_CTL_L2C_BUFF_EMOD_SHIFT 12 63 64 #define UCTL_OHCI_CTL 0x88 65 #define UCTL_OHCI_CTL_L2C_ADDR_MSB_MASK 0xff 66 #define UCTL_OHCI_CTL_L2C_ADDR_MSB_SHIFT 0 67 #define UCTL_OHCI_CTL_L2C_DESC_EMOD_SHIFT 10 68 #define UCTL_OHCI_CTL_L2C_BUFF_EMOD_SHIFT 12 69 70 #endif /* _OCTUCTLREG_H_ */ 71