1 /* $OpenBSD: cpu.h,v 1.68 2020/06/05 14:25:05 naddy Exp $ */ 2 /* $NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $ */ 3 4 /* 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 #ifndef _POWERPC_CPU_H_ 35 #define _POWERPC_CPU_H_ 36 37 #include <machine/frame.h> 38 39 #include <sys/device.h> 40 #include <sys/sched.h> 41 #include <sys/srp.h> 42 43 struct cpu_info { 44 struct device *ci_dev; /* our device */ 45 struct schedstate_percpu ci_schedstate; /* scheduler state */ 46 47 struct proc *ci_curproc; 48 49 struct pcb *ci_curpcb; 50 struct pmap *ci_curpm; 51 struct proc *ci_fpuproc; 52 struct proc *ci_vecproc; 53 int ci_cpuid; 54 55 volatile int ci_want_resched; 56 volatile int ci_cpl; 57 volatile int ci_ipending; 58 59 volatile int ci_flags; 60 #define CI_FLAGS_SLEEPING 2 61 62 #if defined(MULTIPROCESSOR) 63 struct srp_hazard ci_srp_hazards[SRP_HAZARD_NUM]; 64 #endif 65 66 int ci_intrdepth; 67 char *ci_intstk; 68 #define CPUSAVE_LEN 8 69 register_t ci_tempsave[CPUSAVE_LEN]; 70 register_t ci_ddbsave[CPUSAVE_LEN]; 71 #define DISISAVE_LEN 4 72 register_t ci_disisave[DISISAVE_LEN]; 73 74 volatile u_int64_t ci_nexttimerevent; 75 volatile u_int64_t ci_prevtb; 76 volatile u_int64_t ci_lasttb; 77 volatile u_int64_t ci_nextstatevent; 78 int ci_statspending; 79 80 volatile int ci_ddb_paused; 81 #define CI_DDB_RUNNING 0 82 #define CI_DDB_SHOULDSTOP 1 83 #define CI_DDB_STOPPED 2 84 #define CI_DDB_ENTERDDB 3 85 #define CI_DDB_INDDB 4 86 87 u_int32_t ci_randseed; 88 89 #ifdef DIAGNOSTIC 90 int ci_mutex_level; 91 #endif 92 #ifdef GPROF 93 struct gmonparam *ci_gmon; 94 #endif 95 }; 96 97 static __inline struct cpu_info * 98 curcpu(void) 99 { 100 struct cpu_info *ci; 101 102 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 103 return ci; 104 } 105 106 #define curpcb (curcpu()->ci_curpcb) 107 #define curpm (curcpu()->ci_curpm) 108 109 #define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0) 110 111 #ifdef MULTIPROCESSOR 112 113 #define PPC_MAXPROCS 4 114 115 static __inline int 116 cpu_number(void) 117 { 118 int pir; 119 120 pir = curcpu()->ci_cpuid; 121 return pir; 122 } 123 124 void cpu_boot_secondary_processors(void); 125 126 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 127 #define CPU_INFO_ITERATOR int 128 #define CPU_INFO_FOREACH(cii, ci) \ 129 for (cii = 0, ci = &cpu_info[0]; cii < ncpusfound; cii++, ci++) 130 131 void cpu_unidle(struct cpu_info *); 132 133 #else 134 135 #define PPC_MAXPROCS 1 136 137 #define cpu_number() 0 138 139 #define CPU_IS_PRIMARY(ci) 1 140 #define CPU_INFO_ITERATOR int 141 #define CPU_INFO_FOREACH(cii, ci) \ 142 for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL) 143 144 #define cpu_unidle(ci) 145 146 #endif 147 148 #define CPU_BUSY_CYCLE() do {} while (0) 149 150 #define MAXCPUS PPC_MAXPROCS 151 152 extern struct cpu_info cpu_info[PPC_MAXPROCS]; 153 154 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 155 #define CLKF_PC(frame) ((frame)->srr0) 156 #define CLKF_INTR(frame) ((frame)->depth != 0) 157 158 extern int ppc_cpuidle; 159 extern int ppc_proc_is_64b; 160 extern int ppc_nobat; 161 162 void cpu_bootstrap(void); 163 164 static inline unsigned int 165 cpu_rnd_messybits(void) 166 { 167 unsigned int hi, lo; 168 169 __asm volatile("mftbu %0; mftb %1" : "=r" (hi), "=r" (lo)); 170 171 return (hi ^ lo); 172 } 173 174 /* 175 * This is used during profiling to integrate system time. 176 */ 177 #define PROC_PC(p) (trapframe(p)->srr0) 178 #define PROC_STACK(p) (trapframe(p)->fixreg[1]) 179 180 void delay(unsigned); 181 #define DELAY(n) delay(n) 182 183 #define aston(p) ((p)->p_md.md_astpending = 1) 184 185 /* 186 * Preempt the current process if in interrupt from user mode, 187 * or after the current trap/syscall if in system mode. 188 */ 189 #define need_resched(ci) \ 190 do { \ 191 ci->ci_want_resched = 1; \ 192 if (ci->ci_curproc != NULL) \ 193 aston(ci->ci_curproc); \ 194 } while (0) 195 #define clear_resched(ci) (ci)->ci_want_resched = 0 196 197 #define need_proftick(p) aston(p) 198 199 void signotify(struct proc *); 200 201 extern char *bootpath; 202 203 #ifndef CACHELINESIZE 204 #define CACHELINESIZE 32 /* For now XXX */ 205 #endif 206 207 static __inline void 208 syncicache(void *from, int len) 209 { 210 int l; 211 char *p = from; 212 213 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 214 l = len; 215 216 do { 217 __asm volatile ("dcbst 0,%0" :: "r"(p)); 218 p += CACHELINESIZE; 219 } while ((l -= CACHELINESIZE) > 0); 220 __asm volatile ("sync"); 221 p = from; 222 l = len; 223 do { 224 __asm volatile ("icbi 0,%0" :: "r"(p)); 225 p += CACHELINESIZE; 226 } while ((l -= CACHELINESIZE) > 0); 227 __asm volatile ("isync"); 228 } 229 230 static __inline void 231 invdcache(void *from, int len) 232 { 233 int l; 234 char *p = from; 235 236 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 237 l = len; 238 239 do { 240 __asm volatile ("dcbi 0,%0" :: "r"(p)); 241 p += CACHELINESIZE; 242 } while ((l -= CACHELINESIZE) > 0); 243 __asm volatile ("sync"); 244 } 245 246 static __inline void 247 flushdcache(void *from, int len) 248 { 249 int l; 250 char *p = from; 251 252 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 253 l = len; 254 255 do { 256 __asm volatile ("dcbf 0,%0" :: "r"(p)); 257 p += CACHELINESIZE; 258 } while ((l -= CACHELINESIZE) > 0); 259 __asm volatile ("sync"); 260 } 261 262 #define FUNC_SPR(n, name) \ 263 static __inline u_int32_t ppc_mf ## name (void) \ 264 { \ 265 u_int32_t ret; \ 266 __asm volatile ("mfspr %0," # n : "=r" (ret)); \ 267 return ret; \ 268 } \ 269 static __inline void ppc_mt ## name (u_int32_t val) \ 270 { \ 271 __asm volatile ("mtspr "# n ",%0" :: "r" (val)); \ 272 } \ 273 274 FUNC_SPR(0, mq) 275 FUNC_SPR(1, xer) 276 FUNC_SPR(4, rtcu) 277 FUNC_SPR(5, rtcl) 278 FUNC_SPR(8, lr) 279 FUNC_SPR(9, ctr) 280 FUNC_SPR(18, dsisr) 281 FUNC_SPR(19, dar) 282 FUNC_SPR(22, dec) 283 FUNC_SPR(25, sdr1) 284 FUNC_SPR(26, srr0) 285 FUNC_SPR(27, srr1) 286 FUNC_SPR(256, vrsave) 287 FUNC_SPR(272, sprg0) 288 FUNC_SPR(273, sprg1) 289 FUNC_SPR(274, sprg2) 290 FUNC_SPR(275, sprg3) 291 FUNC_SPR(280, asr) 292 FUNC_SPR(282, ear) 293 FUNC_SPR(287, pvr) 294 FUNC_SPR(311, hior) 295 FUNC_SPR(528, ibat0u) 296 FUNC_SPR(529, ibat0l) 297 FUNC_SPR(530, ibat1u) 298 FUNC_SPR(531, ibat1l) 299 FUNC_SPR(532, ibat2u) 300 FUNC_SPR(533, ibat2l) 301 FUNC_SPR(534, ibat3u) 302 FUNC_SPR(535, ibat3l) 303 FUNC_SPR(560, ibat4u) 304 FUNC_SPR(561, ibat4l) 305 FUNC_SPR(562, ibat5u) 306 FUNC_SPR(563, ibat5l) 307 FUNC_SPR(564, ibat6u) 308 FUNC_SPR(565, ibat6l) 309 FUNC_SPR(566, ibat7u) 310 FUNC_SPR(567, ibat7l) 311 FUNC_SPR(536, dbat0u) 312 FUNC_SPR(537, dbat0l) 313 FUNC_SPR(538, dbat1u) 314 FUNC_SPR(539, dbat1l) 315 FUNC_SPR(540, dbat2u) 316 FUNC_SPR(541, dbat2l) 317 FUNC_SPR(542, dbat3u) 318 FUNC_SPR(543, dbat3l) 319 FUNC_SPR(568, dbat4u) 320 FUNC_SPR(569, dbat4l) 321 FUNC_SPR(570, dbat5u) 322 FUNC_SPR(571, dbat5l) 323 FUNC_SPR(572, dbat6u) 324 FUNC_SPR(573, dbat6l) 325 FUNC_SPR(574, dbat7u) 326 FUNC_SPR(575, dbat7l) 327 FUNC_SPR(1009, hid1) 328 FUNC_SPR(1010, iabr) 329 FUNC_SPR(1017, l2cr) 330 FUNC_SPR(1018, l3cr) 331 FUNC_SPR(1013, dabr) 332 FUNC_SPR(1023, pir) 333 334 static __inline u_int32_t 335 ppc_mftbl (void) 336 { 337 int ret; 338 __asm volatile ("mftb %0" : "=r" (ret)); 339 return ret; 340 } 341 342 343 static __inline u_int64_t 344 ppc_mftb(void) 345 { 346 u_long scratch; 347 u_int64_t tb; 348 349 __asm volatile ("1: mftbu %0; mftb %L0; mftbu %1;" 350 " cmpw 0,%0,%1; bne 1b" : "=r"(tb), "=r"(scratch)); 351 return tb; 352 } 353 354 static __inline void 355 ppc_mttb(u_int64_t tb) 356 { 357 __asm volatile ("mttbl %0" :: "r"(0)); 358 __asm volatile ("mttbu %0" :: "r"((u_int32_t)(tb >> 32))); 359 __asm volatile ("mttbl %0" :: "r"((u_int32_t)(tb & 0xffffffff))); 360 } 361 362 static __inline u_int32_t 363 ppc_mfmsr (void) 364 { 365 int ret; 366 __asm volatile ("mfmsr %0" : "=r" (ret)); 367 return ret; 368 } 369 370 static __inline void 371 ppc_mtmsr (u_int32_t val) 372 { 373 __asm volatile ("mtmsr %0" :: "r" (val)); 374 } 375 376 static __inline void 377 ppc_mtsrin(u_int32_t val, u_int32_t sn_shifted) 378 { 379 __asm volatile ("mtsrin %0,%1" :: "r"(val), "r"(sn_shifted)); 380 } 381 382 u_int64_t ppc64_mfscomc(void); 383 void ppc_mtscomc(u_int32_t); 384 void ppc64_mtscomc(u_int64_t); 385 u_int64_t ppc64_mfscomd(void); 386 void ppc_mtscomd(u_int32_t); 387 u_int32_t ppc_mfhid0(void); 388 void ppc_mthid0(u_int32_t); 389 u_int64_t ppc64_mfhid1(void); 390 void ppc64_mthid1(u_int64_t); 391 u_int64_t ppc64_mfhid4(void); 392 void ppc64_mthid4(u_int64_t); 393 u_int64_t ppc64_mfhid5(void); 394 void ppc64_mthid5(u_int64_t); 395 396 #include <machine/psl.h> 397 398 /* 399 * General functions to enable and disable interrupts 400 * without having inlined assembly code in many functions. 401 */ 402 static __inline void 403 ppc_intr_enable(int enable) 404 { 405 u_int32_t msr; 406 if (enable != 0) { 407 msr = ppc_mfmsr(); 408 msr |= PSL_EE; 409 ppc_mtmsr(msr); 410 } 411 } 412 413 static __inline int 414 ppc_intr_disable(void) 415 { 416 u_int32_t emsr, dmsr; 417 emsr = ppc_mfmsr(); 418 dmsr = emsr & ~PSL_EE; 419 ppc_mtmsr(dmsr); 420 return (emsr & PSL_EE); 421 } 422 423 static __inline u_long 424 intr_disable(void) 425 { 426 return ppc_intr_disable(); 427 } 428 429 static __inline void 430 intr_restore(u_long s) 431 { 432 ppc_intr_enable(s); 433 } 434 435 int ppc_cpuspeed(int *); 436 437 /* 438 * PowerPC CPU types 439 */ 440 #define PPC_CPU_MPC601 1 441 #define PPC_CPU_MPC603 3 442 #define PPC_CPU_MPC604 4 443 #define PPC_CPU_MPC603e 6 444 #define PPC_CPU_MPC603ev 7 445 #define PPC_CPU_MPC750 8 446 #define PPC_CPU_MPC604ev 9 447 #define PPC_CPU_MPC7400 12 448 #define PPC_CPU_IBM970 0x0039 449 #define PPC_CPU_IBM970FX 0x003c 450 #define PPC_CPU_IBM970MP 0x0044 451 #define PPC_CPU_IBM750FX 0x7000 452 #define PPC_CPU_MPC7410 0x800c 453 #define PPC_CPU_MPC7447A 0x8003 454 #define PPC_CPU_MPC7448 0x8004 455 #define PPC_CPU_MPC7450 0x8000 456 #define PPC_CPU_MPC7455 0x8001 457 #define PPC_CPU_MPC7457 0x8002 458 #define PPC_CPU_MPC83xx 0x8083 459 460 /* 461 * This needs to be included late since it relies on definitions higher 462 * up in this file. 463 */ 464 #if defined(MULTIPROCESSOR) && defined(_KERNEL) 465 #include <sys/mplock.h> 466 #endif 467 468 #endif /* _POWERPC_CPU_H_ */ 469