1 /* 2 * Copyright (c) 2019 Brian Bamsch <bbamsch@google.com> 3 * Copyright (c) 2014 Dale Rahn <drahn@dalerahn.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 #ifndef _RISCV64_PTE_H_ 18 #define _RISCV64_PTE_H_ 19 20 #include "machine/vmparam.h" 21 22 #define Lx_TABLE_ALIGN (4096) 23 24 /* Block and Page attributes */ 25 /* Bits 9:8 are reserved for software */ 26 #define PTE_ATTR_MASK (0x3ffUL) 27 #define PTE_SW_MANAGED (1 << 9) 28 #define PTE_SW_WIRED (1 << 8) 29 #define PTE_D (1 << 7) /* Dirty */ 30 #define PTE_A (1 << 6) /* Accessed */ 31 #define PTE_G (1 << 5) /* Global */ 32 #define PTE_U (1 << 4) /* User */ 33 #define PTE_X (1 << 3) /* Execute */ 34 #define PTE_W (1 << 2) /* Write */ 35 #define PTE_R (1 << 1) /* Read */ 36 #define PTE_V (1 << 0) /* Valid */ 37 #define PTE_RWX (PTE_R | PTE_W | PTE_X) 38 #define PTE_RX (PTE_R | PTE_X) 39 #define PTE_KERN (PTE_V | PTE_R | PTE_W | PTE_A | PTE_D) 40 #define PTE_PROMOTE (PTE_V | PTE_RWX | PTE_D | PTE_A | PTE_G | PTE_U | \ 41 PTE_SW_MANAGED | PTE_SW_WIRED 42 43 /* Level 0 table, 512GiB per entry */ 44 #define L0_SHIFT 39 45 46 /* Level 1 table, 1GiB per entry */ 47 #define L1_SHIFT 30 48 #define L1_SIZE (1UL << L1_SHIFT) 49 #define L1_OFFSET (L1_SIZE - 1) 50 51 /* Level 2 table, 2MiB per entry */ 52 #define L2_SHIFT 21 53 #define L2_SIZE (1UL << L2_SHIFT) 54 #define L2_OFFSET (L2_SIZE - 1) 55 56 /* Level 3 table, 4KiB per entry */ 57 #define L3_SHIFT 12 58 #define L3_SIZE (1UL << L3_SHIFT) 59 #define L3_OFFSET (L3_SIZE - 1) 60 61 /* page mapping */ 62 #define Ln_ENTRIES_SHIFT 9 63 #define Ln_ENTRIES (1 << Ln_ENTRIES_SHIFT) 64 #define Ln_ADDR_MASK (Ln_ENTRIES - 1) 65 #define Ln_TABLE_MASK ((1 << 12) - 1) 66 67 /* physical page number mask */ 68 #define PTE_RPGN (((1ULL << 56) - 1) & ~PAGE_MASK) 69 70 #define PTE_PPN0_S 10 71 #define PTE_PPN1_S 19 72 #define PTE_PPN2_S 28 73 #define PTE_PPN3_S 37 74 #define PTE_SIZE 8 75 76 #ifndef _LOCORE 77 typedef uint64_t pt_entry_t; /* page table entry */ 78 typedef uint64_t pn_t; /* page number */ 79 #endif /* !_LOCORE */ 80 81 #endif /* _RISCV64_PTE_H_ */ 82