xref: /openbsd/sys/arch/sh/include/bscreg.h (revision 76d0caae)
1 /*	$OpenBSD: bscreg.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $	*/
2 /*	$NetBSD: bscreg.h,v 1.6 2005/12/11 12:18:58 christos Exp $	*/
3 
4 /*-
5  * Copyright (C) 1999 SAITOH Masanobu.  All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. The name of the author may not be used to endorse or promote products
16  *    derived from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #ifndef _SH_BSCREG_H_
31 #define	_SH_BSCREG_H_
32 #include <sh/devreg.h>
33 
34 /*
35  * Bus State Controller
36  */
37 
38 #define	SH3_BCR1		0xffffff60	/* 16bit */
39 #define	SH3_BCR2		0xffffff62	/* 16bit */
40 #define	SH3_WCR1		0xffffff64	/* 16bit */
41 #define	SH3_WCR2		0xffffff66	/* 16bit */
42 #define	SH3_MCR			0xffffff68	/* 16bit */
43 #define	SH3_DCR			0xffffff6a	/* 16bit */
44 #define	SH3_PCR			0xffffff6c	/* 16bit */
45 #define	SH3_RTCSR		0xffffff6e	/* 16bit */
46 #define	SH3_RTCNT		0xffffff70	/* 16bit */
47 #define	SH3_RTCOR		0xffffff72	/* 16bit */
48 #define	SH3_RFCR		0xffffff74	/* 16bit */
49 #define	SH3_BCR3		0xffffff7e	/* 16bit */
50 
51 #define	SH4_BCR1		0xff800000	/* 32bit */
52 #define	SH4_BCR2		0xff800004	/* 16bit */
53 #define	SH4_WCR1		0xff800008	/* 32bit */
54 #define	SH4_WCR2		0xff80000c	/* 32bit */
55 #define	SH4_WCR3		0xff800010	/* 32bit */
56 #define	SH4_MCR			0xff800014	/* 32bit */
57 #define	SH4_PCR			0xff800018	/* 16bit */
58 #define	SH4_RTCSR		0xff80001c	/* 16bit */
59 #define	SH4_RTCNT		0xff800020	/* 16bit */
60 #define	SH4_RTCOR		0xff800024	/* 16bit */
61 #define	SH4_RFCR		0xff800028	/* 16bit */
62 #define	SH4_BCR3		0xff800050	/* 16bit: SH7751R */
63 #define	SH4_BCR4		0xfe0a00f0	/* 32bit: SH7751R */
64 
65 #define	BCR1_MASTER		(1 << 30)
66 #define	BCR1_BREQEN		(1 << 19)
67 
68 #define	BCR2_PORTEN		(1 << 0)
69 
70 #endif	/* !_SH_BSCREG_H_ */
71