1 /* $OpenBSD: creator.c,v 1.53 2020/05/25 09:55:48 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/kernel.h> 32 #include <sys/device.h> 33 #include <sys/conf.h> 34 #include <sys/malloc.h> 35 36 #include <machine/bus.h> 37 #include <machine/autoconf.h> 38 #include <machine/openfirm.h> 39 40 #include <dev/wscons/wsconsio.h> 41 #include <dev/wscons/wsdisplayvar.h> 42 #include <dev/rasops/rasops.h> 43 #include <machine/fbvar.h> 44 45 #include <sparc64/dev/creatorreg.h> 46 #include <sparc64/dev/creatorvar.h> 47 48 int creator_match(struct device *, void *, void *); 49 void creator_attach(struct device *, struct device *, void *); 50 int creator_ioctl(void *, u_long, caddr_t, int, struct proc *); 51 paddr_t creator_mmap(void *, off_t, int); 52 53 void creator_ras_fifo_wait(struct creator_softc *, int); 54 void creator_ras_wait(struct creator_softc *); 55 void creator_ras_init(struct creator_softc *); 56 int creator_ras_copyrows(void *, int, int, int); 57 int creator_ras_erasecols(void *, int, int, int, uint32_t); 58 int creator_ras_eraserows(void *, int, int, uint32_t); 59 void creator_ras_fill(struct creator_softc *); 60 void creator_ras_setfg(struct creator_softc *, int32_t); 61 62 int creator_setcursor(struct creator_softc *, struct wsdisplay_cursor *); 63 int creator_updatecursor(struct creator_softc *, u_int); 64 void creator_curs_enable(struct creator_softc *, u_int); 65 66 #ifndef SMALL_KERNEL 67 void creator_load_firmware(struct device *); 68 #endif /* SMALL_KERNEL */ 69 void creator_load_sram(struct creator_softc *, u_int32_t *, u_int32_t); 70 71 struct wsdisplay_accessops creator_accessops = { 72 .ioctl = creator_ioctl, 73 .mmap = creator_mmap 74 }; 75 76 struct cfdriver creator_cd = { 77 NULL, "creator", DV_DULL 78 }; 79 80 struct cfattach creator_ca = { 81 sizeof(struct creator_softc), creator_match, creator_attach 82 }; 83 84 int 85 creator_match(parent, match, aux) 86 struct device *parent; 87 void *match, *aux; 88 { 89 struct mainbus_attach_args *ma = aux; 90 91 if (strcmp(ma->ma_name, "SUNW,ffb") == 0 || 92 strcmp(ma->ma_name, "SUNW,afb") == 0) 93 return (1); 94 return (0); 95 } 96 97 void 98 creator_attach(parent, self, aux) 99 struct device *parent, *self; 100 void *aux; 101 { 102 struct creator_softc *sc = (struct creator_softc *)self; 103 struct mainbus_attach_args *ma = aux; 104 extern int fbnode; 105 int i, nregs; 106 char *model; 107 int btype; 108 109 sc->sc_bt = ma->ma_bustag; 110 111 nregs = min(ma->ma_nreg, FFB_NREGS); 112 113 if (nregs <= FFB_REG_DFB24) { 114 printf(": no dfb24 regs found\n"); 115 return; 116 } 117 118 if (bus_space_map(sc->sc_bt, ma->ma_reg[FFB_REG_DFB24].ur_paddr, 119 ma->ma_reg[FFB_REG_DFB24].ur_len, BUS_SPACE_MAP_LINEAR, 120 &sc->sc_pixel_h)) { 121 printf(": failed to map dfb24\n"); 122 return; 123 } 124 125 if (bus_space_map(sc->sc_bt, ma->ma_reg[FFB_REG_FBC].ur_paddr, 126 ma->ma_reg[FFB_REG_FBC].ur_len, 0, &sc->sc_fbc_h)) { 127 printf(": failed to map fbc\n"); 128 goto unmap_dfb24; 129 } 130 131 if (bus_space_map(sc->sc_bt, ma->ma_reg[FFB_REG_DAC].ur_paddr, 132 ma->ma_reg[FFB_REG_DAC].ur_len, 0, &sc->sc_dac_h)) { 133 printf(": failed to map dac\n"); 134 goto unmap_fbc; 135 } 136 137 for (i = 0; i < nregs; i++) { 138 sc->sc_addrs[i] = ma->ma_reg[i].ur_paddr; 139 sc->sc_sizes[i] = ma->ma_reg[i].ur_len; 140 } 141 sc->sc_nreg = nregs; 142 143 sc->sc_console = (fbnode == ma->ma_node); 144 sc->sc_node = ma->ma_node; 145 146 if (strcmp(ma->ma_name, "SUNW,afb") == 0) 147 sc->sc_type = FFB_AFB; 148 149 /* 150 * Prom reports only the length of the fcode header, we need 151 * the whole thing. 152 */ 153 sc->sc_sizes[0] = 0x00400000; 154 155 if (sc->sc_type == FFB_CREATOR) { 156 btype = getpropint(sc->sc_node, "board_type", 0); 157 if ((btype & 7) == 3) 158 printf(": Creator3D"); 159 else 160 printf(": Creator"); 161 } else 162 printf(": Elite3D"); 163 164 model = getpropstring(sc->sc_node, "model"); 165 if (model == NULL || strlen(model) == 0) 166 model = "unknown"; 167 168 DAC_WRITE(sc, FFB_DAC_TYPE, DAC_TYPE_GETREV); 169 sc->sc_dacrev = DAC_READ(sc, FFB_DAC_VALUE) >> 28; 170 171 printf(", model %s, dac %u", model, sc->sc_dacrev); 172 173 if (sc->sc_type == FFB_AFB) 174 sc->sc_dacrev = 10; 175 176 fb_setsize(&sc->sc_sunfb, 32, 1152, 900, sc->sc_node, 0); 177 /* linesize has a fixed value, compensate */ 178 sc->sc_sunfb.sf_linebytes = 8192; 179 sc->sc_sunfb.sf_fbsize = sc->sc_sunfb.sf_height * 8192; 180 181 printf(", %dx%d\n", sc->sc_sunfb.sf_width, sc->sc_sunfb.sf_height); 182 183 sc->sc_sunfb.sf_ro.ri_bits = (void *)bus_space_vaddr(sc->sc_bt, 184 sc->sc_pixel_h); 185 sc->sc_sunfb.sf_ro.ri_hw = sc; 186 fbwscons_init(&sc->sc_sunfb, 0, sc->sc_console); 187 188 if ((sc->sc_sunfb.sf_dev.dv_cfdata->cf_flags & CREATOR_CFFLAG_NOACCEL) 189 == 0) { 190 sc->sc_sunfb.sf_ro.ri_ops.eraserows = creator_ras_eraserows; 191 sc->sc_sunfb.sf_ro.ri_ops.erasecols = creator_ras_erasecols; 192 sc->sc_sunfb.sf_ro.ri_ops.copyrows = creator_ras_copyrows; 193 creator_ras_init(sc); 194 195 #ifndef SMALL_KERNEL 196 /* 197 * Elite3D cards need a firmware for accelerated X to 198 * work. Console framebuffer acceleration will work 199 * without it though, so doing this late should be 200 * fine. 201 */ 202 if (sc->sc_type == FFB_AFB) 203 config_mountroot(self, creator_load_firmware); 204 #endif /* SMALL_KERNEL */ 205 } 206 207 if (sc->sc_console) 208 fbwscons_console_init(&sc->sc_sunfb, -1); 209 210 fbwscons_attach(&sc->sc_sunfb, &creator_accessops, sc->sc_console); 211 return; 212 213 unmap_fbc: 214 bus_space_unmap(sc->sc_bt, sc->sc_fbc_h, 215 ma->ma_reg[FFB_REG_FBC].ur_len); 216 unmap_dfb24: 217 bus_space_unmap(sc->sc_bt, sc->sc_pixel_h, 218 ma->ma_reg[FFB_REG_DFB24].ur_len); 219 } 220 221 int 222 creator_ioctl(v, cmd, data, flags, p) 223 void *v; 224 u_long cmd; 225 caddr_t data; 226 int flags; 227 struct proc *p; 228 { 229 struct creator_softc *sc = v; 230 struct wsdisplay_cursor *curs; 231 struct wsdisplay_fbinfo *wdf; 232 struct wsdisplay_curpos *pos; 233 u_char r[2], g[2], b[2]; 234 int error; 235 236 switch (cmd) { 237 case WSDISPLAYIO_GTYPE: 238 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 239 break; 240 case WSDISPLAYIO_SMODE: 241 sc->sc_mode = *(u_int *)data; 242 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 243 struct rasops_info *ri = &sc->sc_sunfb.sf_ro; 244 uint32_t attr; 245 246 if ((sc->sc_sunfb.sf_dev.dv_cfdata->cf_flags & 247 CREATOR_CFFLAG_NOACCEL) == 0) 248 creator_ras_init(sc); 249 250 /* Clear screen. */ 251 ri->ri_ops.pack_attr(ri, 252 WSCOL_BLACK, WSCOL_WHITE, WSATTR_WSCOLORS, &attr); 253 ri->ri_ops.eraserows(ri, 0, ri->ri_rows, attr); 254 } 255 break; 256 case WSDISPLAYIO_GINFO: 257 wdf = (void *)data; 258 wdf->height = sc->sc_sunfb.sf_height; 259 wdf->width = sc->sc_sunfb.sf_width; 260 wdf->depth = 32; 261 wdf->cmsize = 0; 262 break; 263 case WSDISPLAYIO_GETSUPPORTEDDEPTH: 264 *(u_int *)data = WSDISPLAYIO_DEPTH_24_32; 265 break; 266 case WSDISPLAYIO_LINEBYTES: 267 *(u_int *)data = sc->sc_sunfb.sf_linebytes; 268 break; 269 case WSDISPLAYIO_GCURSOR: 270 curs = (struct wsdisplay_cursor *)data; 271 if (curs->which & WSDISPLAY_CURSOR_DOCUR) 272 curs->enable = sc->sc_curs_enabled; 273 if (curs->which & WSDISPLAY_CURSOR_DOPOS) { 274 curs->pos.x = sc->sc_curs_pos.x; 275 curs->pos.y = sc->sc_curs_pos.y; 276 } 277 if (curs->which & WSDISPLAY_CURSOR_DOHOT) { 278 curs->hot.x = sc->sc_curs_hot.x; 279 curs->hot.y = sc->sc_curs_hot.y; 280 } 281 if (curs->which & WSDISPLAY_CURSOR_DOCMAP) { 282 curs->cmap.index = 0; 283 curs->cmap.count = 2; 284 r[0] = sc->sc_curs_fg >> 0; 285 g[0] = sc->sc_curs_fg >> 8; 286 b[0] = sc->sc_curs_fg >> 16; 287 r[1] = sc->sc_curs_bg >> 0; 288 g[1] = sc->sc_curs_bg >> 8; 289 b[1] = sc->sc_curs_bg >> 16; 290 error = copyout(r, curs->cmap.red, sizeof(r)); 291 if (error) 292 return (error); 293 error = copyout(g, curs->cmap.green, sizeof(g)); 294 if (error) 295 return (error); 296 error = copyout(b, curs->cmap.blue, sizeof(b)); 297 if (error) 298 return (error); 299 } 300 if (curs->which & WSDISPLAY_CURSOR_DOSHAPE) { 301 size_t l; 302 303 curs->size.x = sc->sc_curs_size.x; 304 curs->size.y = sc->sc_curs_size.y; 305 l = (sc->sc_curs_size.x * sc->sc_curs_size.y) / NBBY; 306 error = copyout(sc->sc_curs_image, curs->image, l); 307 if (error) 308 return (error); 309 error = copyout(sc->sc_curs_mask, curs->mask, l); 310 if (error) 311 return (error); 312 } 313 break; 314 case WSDISPLAYIO_SCURPOS: 315 pos = (struct wsdisplay_curpos *)data; 316 sc->sc_curs_pos.x = pos->x; 317 sc->sc_curs_pos.y = pos->y; 318 creator_updatecursor(sc, WSDISPLAY_CURSOR_DOPOS); 319 break; 320 case WSDISPLAYIO_GCURPOS: 321 pos = (struct wsdisplay_curpos *)data; 322 pos->x = sc->sc_curs_pos.x; 323 pos->y = sc->sc_curs_pos.y; 324 break; 325 case WSDISPLAYIO_SCURSOR: 326 curs = (struct wsdisplay_cursor *)data; 327 return (creator_setcursor(sc, curs)); 328 case WSDISPLAYIO_GCURMAX: 329 pos = (struct wsdisplay_curpos *)data; 330 pos->x = CREATOR_CURS_MAX; 331 pos->y = CREATOR_CURS_MAX; 332 break; 333 case WSDISPLAYIO_SVIDEO: 334 case WSDISPLAYIO_GVIDEO: 335 break; 336 337 case WSDISPLAYIO_GETCMAP: 338 case WSDISPLAYIO_PUTCMAP: 339 default: 340 return -1; /* not supported yet */ 341 } 342 343 return (0); 344 } 345 346 int 347 creator_setcursor(struct creator_softc *sc, struct wsdisplay_cursor *curs) 348 { 349 u_int8_t r[2], g[2], b[2], image[128], mask[128]; 350 int error; 351 size_t imcount; 352 353 /* 354 * Do stuff that can generate errors first, then we'll blast it 355 * all at once. 356 */ 357 if (curs->which & WSDISPLAY_CURSOR_DOCMAP) { 358 if (curs->cmap.count < 2) 359 return (EINVAL); 360 error = copyin(curs->cmap.red, r, sizeof(r)); 361 if (error) 362 return (error); 363 error = copyin(curs->cmap.green, g, sizeof(g)); 364 if (error) 365 return (error); 366 error = copyin(curs->cmap.blue, b, sizeof(b)); 367 if (error) 368 return (error); 369 } 370 371 if (curs->which & WSDISPLAY_CURSOR_DOSHAPE) { 372 if (curs->size.x > CREATOR_CURS_MAX || 373 curs->size.y > CREATOR_CURS_MAX) 374 return (EINVAL); 375 imcount = (curs->size.x * curs->size.y) / NBBY; 376 error = copyin(curs->image, image, imcount); 377 if (error) 378 return (error); 379 error = copyin(curs->mask, mask, imcount); 380 if (error) 381 return (error); 382 } 383 384 /* 385 * Ok, everything is in kernel space and sane, update state. 386 */ 387 388 if (curs->which & WSDISPLAY_CURSOR_DOCUR) 389 sc->sc_curs_enabled = curs->enable; 390 if (curs->which & WSDISPLAY_CURSOR_DOPOS) { 391 sc->sc_curs_pos.x = curs->pos.x; 392 sc->sc_curs_pos.y = curs->pos.y; 393 } 394 if (curs->which & WSDISPLAY_CURSOR_DOHOT) { 395 sc->sc_curs_hot.x = curs->hot.x; 396 sc->sc_curs_hot.y = curs->hot.y; 397 } 398 if (curs->which & WSDISPLAY_CURSOR_DOCMAP) { 399 sc->sc_curs_fg = ((r[0] << 0) | (g[0] << 8) | (b[0] << 16)); 400 sc->sc_curs_bg = ((r[1] << 0) | (g[1] << 8) | (b[1] << 16)); 401 } 402 if (curs->which & WSDISPLAY_CURSOR_DOSHAPE) { 403 sc->sc_curs_size.x = curs->size.x; 404 sc->sc_curs_size.y = curs->size.y; 405 bcopy(image, sc->sc_curs_image, imcount); 406 bcopy(mask, sc->sc_curs_mask, imcount); 407 } 408 409 creator_updatecursor(sc, curs->which); 410 411 return (0); 412 } 413 414 void 415 creator_curs_enable(struct creator_softc *sc, u_int ena) 416 { 417 u_int32_t v; 418 419 DAC_WRITE(sc, FFB_DAC_TYPE2, DAC_TYPE2_CURSENAB); 420 if (sc->sc_dacrev <= 2) 421 v = ena ? 3 : 0; 422 else 423 v = ena ? 0 : 3; 424 DAC_WRITE(sc, FFB_DAC_VALUE2, v); 425 } 426 427 int 428 creator_updatecursor(struct creator_softc *sc, u_int which) 429 { 430 creator_curs_enable(sc, 0); 431 432 if (which & WSDISPLAY_CURSOR_DOCMAP) { 433 DAC_WRITE(sc, FFB_DAC_TYPE2, DAC_TYPE2_CURSCMAP); 434 DAC_WRITE(sc, FFB_DAC_VALUE2, sc->sc_curs_fg); 435 DAC_WRITE(sc, FFB_DAC_VALUE2, sc->sc_curs_bg); 436 } 437 438 if (which & (WSDISPLAY_CURSOR_DOPOS | WSDISPLAY_CURSOR_DOHOT)) { 439 u_int32_t x, y; 440 441 x = sc->sc_curs_pos.x + CREATOR_CURS_MAX - sc->sc_curs_hot.x; 442 y = sc->sc_curs_pos.y + CREATOR_CURS_MAX - sc->sc_curs_hot.y; 443 DAC_WRITE(sc, FFB_DAC_TYPE2, DAC_TYPE2_CURSPOS); 444 DAC_WRITE(sc, FFB_DAC_VALUE2, 445 ((x & 0xffff) << 16) | (y & 0xffff)); 446 } 447 448 if (which & WSDISPLAY_CURSOR_DOCUR) 449 creator_curs_enable(sc, sc->sc_curs_enabled); 450 451 return (0); 452 } 453 454 const struct creator_mappings { 455 bus_addr_t uoff; 456 bus_addr_t poff; 457 bus_size_t ulen; 458 } creator_map[] = { 459 { FFB_VOFF_SFB8R, FFB_POFF_SFB8R, FFB_VLEN_SFB8R }, 460 { FFB_VOFF_SFB8G, FFB_POFF_SFB8G, FFB_VLEN_SFB8G }, 461 { FFB_VOFF_SFB8B, FFB_POFF_SFB8B, FFB_VLEN_SFB8B }, 462 { FFB_VOFF_SFB8X, FFB_POFF_SFB8X, FFB_VLEN_SFB8X }, 463 { FFB_VOFF_SFB32, FFB_POFF_SFB32, FFB_VLEN_SFB32 }, 464 { FFB_VOFF_SFB64, FFB_POFF_SFB64, FFB_VLEN_SFB64 }, 465 { FFB_VOFF_FBC_REGS, FFB_POFF_FBC_REGS, FFB_VLEN_FBC_REGS }, 466 { FFB_VOFF_BM_FBC_REGS, FFB_POFF_BM_FBC_REGS, FFB_VLEN_BM_FBC_REGS }, 467 { FFB_VOFF_DFB8R, FFB_POFF_DFB8R, FFB_VLEN_DFB8R }, 468 { FFB_VOFF_DFB8G, FFB_POFF_DFB8G, FFB_VLEN_DFB8G }, 469 { FFB_VOFF_DFB8B, FFB_POFF_DFB8B, FFB_VLEN_DFB8B }, 470 { FFB_VOFF_DFB8X, FFB_POFF_DFB8X, FFB_VLEN_DFB8X }, 471 { FFB_VOFF_DFB24, FFB_POFF_DFB24, FFB_VLEN_DFB24 }, 472 { FFB_VOFF_DFB32, FFB_POFF_DFB32, FFB_VLEN_DFB32 }, 473 { FFB_VOFF_DFB422A, FFB_POFF_DFB422A, FFB_VLEN_DFB422A }, 474 { FFB_VOFF_DFB422AD, FFB_POFF_DFB422AD, FFB_VLEN_DFB422AD }, 475 { FFB_VOFF_DFB24B, FFB_POFF_DFB24B, FFB_VLEN_DFB24B }, 476 { FFB_VOFF_DFB422B, FFB_POFF_DFB422B, FFB_VLEN_DFB422B }, 477 { FFB_VOFF_DFB422BD, FFB_POFF_DFB422BD, FFB_VLEN_DFB422BD }, 478 { FFB_VOFF_SFB16Z, FFB_POFF_SFB16Z, FFB_VLEN_SFB16Z }, 479 { FFB_VOFF_SFB8Z, FFB_POFF_SFB8Z, FFB_VLEN_SFB8Z }, 480 { FFB_VOFF_SFB422, FFB_POFF_SFB422, FFB_VLEN_SFB422 }, 481 { FFB_VOFF_SFB422D, FFB_POFF_SFB422D, FFB_VLEN_SFB422D }, 482 { FFB_VOFF_FBC_KREGS, FFB_POFF_FBC_KREGS, FFB_VLEN_FBC_KREGS }, 483 { FFB_VOFF_DAC, FFB_POFF_DAC, FFB_VLEN_DAC }, 484 { FFB_VOFF_PROM, FFB_POFF_PROM, FFB_VLEN_PROM }, 485 { FFB_VOFF_EXP, FFB_POFF_EXP, FFB_VLEN_EXP }, 486 }; 487 #define CREATOR_NMAPPINGS nitems(creator_map) 488 489 paddr_t 490 creator_mmap(vsc, off, prot) 491 void *vsc; 492 off_t off; 493 int prot; 494 { 495 paddr_t x; 496 struct creator_softc *sc = vsc; 497 int i; 498 499 switch (sc->sc_mode) { 500 case WSDISPLAYIO_MODE_MAPPED: 501 /* Turn virtual offset into physical offset */ 502 for (i = 0; i < CREATOR_NMAPPINGS; i++) { 503 if (off >= creator_map[i].uoff && 504 off < (creator_map[i].uoff + creator_map[i].ulen)) 505 break; 506 } 507 if (i == CREATOR_NMAPPINGS) 508 break; 509 510 off -= creator_map[i].uoff; 511 off += creator_map[i].poff; 512 off += sc->sc_addrs[0]; 513 514 /* Map based on physical offset */ 515 for (i = 0; i < sc->sc_nreg; i++) { 516 /* Before this set? */ 517 if (off < sc->sc_addrs[i]) 518 continue; 519 /* After this set? */ 520 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 521 continue; 522 523 x = bus_space_mmap(sc->sc_bt, 0, off, prot, 524 BUS_SPACE_MAP_LINEAR); 525 return (x); 526 } 527 break; 528 case WSDISPLAYIO_MODE_DUMBFB: 529 if (sc->sc_nreg <= FFB_REG_DFB24) 530 break; 531 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 532 return (bus_space_mmap(sc->sc_bt, 533 sc->sc_addrs[FFB_REG_DFB24], off, prot, 534 BUS_SPACE_MAP_LINEAR)); 535 break; 536 } 537 538 return (-1); 539 } 540 541 void 542 creator_ras_fifo_wait(sc, n) 543 struct creator_softc *sc; 544 int n; 545 { 546 int32_t cache = sc->sc_fifo_cache; 547 548 if (cache < n) { 549 do { 550 cache = FBC_READ(sc, FFB_FBC_UCSR); 551 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 552 } while (cache < n); 553 } 554 sc->sc_fifo_cache = cache - n; 555 } 556 557 void 558 creator_ras_wait(sc) 559 struct creator_softc *sc; 560 { 561 u_int32_t ucsr, r; 562 563 while (1) { 564 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 565 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 566 break; 567 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 568 if (r != 0) 569 FBC_WRITE(sc, FFB_FBC_UCSR, r); 570 } 571 } 572 573 void 574 creator_ras_init(sc) 575 struct creator_softc *sc; 576 { 577 creator_ras_fifo_wait(sc, 7); 578 FBC_WRITE(sc, FFB_FBC_PPC, 579 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | 580 FBC_PPC_APE_DIS | FBC_PPC_CS_CONST); 581 FBC_WRITE(sc, FFB_FBC_FBC, 582 FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 583 FFB_FBC_XE_OFF | FFB_FBC_RGBE_MASK); 584 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 585 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 586 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 587 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 588 sc->sc_fg_cache = 0; 589 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 590 creator_ras_wait(sc); 591 } 592 593 int 594 creator_ras_eraserows(cookie, row, n, attr) 595 void *cookie; 596 int row, n; 597 uint32_t attr; 598 { 599 struct rasops_info *ri = cookie; 600 struct creator_softc *sc = ri->ri_hw; 601 int bg, fg; 602 603 if (row < 0) { 604 n += row; 605 row = 0; 606 } 607 if (row + n > ri->ri_rows) 608 n = ri->ri_rows - row; 609 if (n <= 0) 610 return 0; 611 612 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 613 creator_ras_fill(sc); 614 creator_ras_setfg(sc, ri->ri_devcmap[bg]); 615 creator_ras_fifo_wait(sc, 4); 616 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 617 FBC_WRITE(sc, FFB_FBC_BY, 0); 618 FBC_WRITE(sc, FFB_FBC_BX, 0); 619 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 620 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 621 } else { 622 row *= ri->ri_font->fontheight; 623 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 624 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 625 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 626 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 627 } 628 creator_ras_wait(sc); 629 630 return 0; 631 } 632 633 int 634 creator_ras_erasecols(cookie, row, col, n, attr) 635 void *cookie; 636 int row, col, n; 637 uint32_t attr; 638 { 639 struct rasops_info *ri = cookie; 640 struct creator_softc *sc = ri->ri_hw; 641 int fg, bg; 642 643 if ((row < 0) || (row >= ri->ri_rows)) 644 return 0; 645 if (col < 0) { 646 n += col; 647 col = 0; 648 } 649 if (col + n > ri->ri_cols) 650 n = ri->ri_cols - col; 651 if (n <= 0) 652 return 0; 653 n *= ri->ri_font->fontwidth; 654 col *= ri->ri_font->fontwidth; 655 row *= ri->ri_font->fontheight; 656 657 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 658 creator_ras_fill(sc); 659 creator_ras_setfg(sc, ri->ri_devcmap[bg]); 660 creator_ras_fifo_wait(sc, 4); 661 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 662 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 663 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 664 FBC_WRITE(sc, FFB_FBC_BW, n - 1); 665 creator_ras_wait(sc); 666 667 return 0; 668 } 669 670 void 671 creator_ras_fill(sc) 672 struct creator_softc *sc; 673 { 674 creator_ras_fifo_wait(sc, 2); 675 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 676 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 677 creator_ras_wait(sc); 678 } 679 680 int 681 creator_ras_copyrows(cookie, src, dst, n) 682 void *cookie; 683 int src, dst, n; 684 { 685 struct rasops_info *ri = cookie; 686 struct creator_softc *sc = ri->ri_hw; 687 688 if (dst == src) 689 return 0; 690 if (src < 0) { 691 n += src; 692 src = 0; 693 } 694 if ((src + n) > ri->ri_rows) 695 n = ri->ri_rows - src; 696 if (dst < 0) { 697 n += dst; 698 dst = 0; 699 } 700 if ((dst + n) > ri->ri_rows) 701 n = ri->ri_rows - dst; 702 if (n <= 0) 703 return 0; 704 n *= ri->ri_font->fontheight; 705 src *= ri->ri_font->fontheight; 706 dst *= ri->ri_font->fontheight; 707 708 creator_ras_fifo_wait(sc, 8); 709 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 710 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 711 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 712 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 713 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 714 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 715 FBC_WRITE(sc, FFB_FBC_BH, n); 716 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 717 creator_ras_wait(sc); 718 719 return 0; 720 } 721 722 void 723 creator_ras_setfg(sc, fg) 724 struct creator_softc *sc; 725 int32_t fg; 726 { 727 creator_ras_fifo_wait(sc, 1); 728 if (fg == sc->sc_fg_cache) 729 return; 730 sc->sc_fg_cache = fg; 731 FBC_WRITE(sc, FFB_FBC_FG, fg); 732 creator_ras_wait(sc); 733 } 734 735 #ifndef SMALL_KERNEL 736 struct creator_firmware { 737 char fw_ident[8]; 738 u_int32_t fw_size; 739 u_int32_t fw_reserved[2]; 740 u_int32_t fw_ucode[0]; 741 }; 742 743 #define CREATOR_FIRMWARE_REV 0x101 744 745 void 746 creator_load_firmware(struct device *self) 747 { 748 struct creator_softc *sc = (struct creator_softc *)self; 749 struct creator_firmware *fw; 750 u_int32_t ascr; 751 size_t buflen; 752 u_char *buf; 753 int error; 754 755 error = loadfirmware("afb", &buf, &buflen); 756 if (error) { 757 printf("%s: error %d, could not read firmware %s\n", 758 sc->sc_sunfb.sf_dev.dv_xname, error, "afb"); 759 return; 760 } 761 762 fw = (struct creator_firmware *)buf; 763 if (sizeof(*fw) > buflen || 764 fw->fw_size * sizeof(u_int32_t) > (buflen - sizeof(*fw))) { 765 printf("%s: corrupt firmware\n", sc->sc_sunfb.sf_dev.dv_xname); 766 free(buf, M_DEVBUF, 0); 767 return; 768 } 769 770 printf("%s: firmware rev %d.%d.%d\n", sc->sc_sunfb.sf_dev.dv_xname, 771 (fw->fw_ucode[CREATOR_FIRMWARE_REV] >> 16) & 0xff, 772 (fw->fw_ucode[CREATOR_FIRMWARE_REV] >> 8) & 0xff, 773 fw->fw_ucode[CREATOR_FIRMWARE_REV] & 0xff); 774 775 ascr = FBC_READ(sc, FFB_FBC_ASCR); 776 777 /* Stop all floats. */ 778 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x3f); 779 FBC_WRITE(sc, FFB_FBC_ASCR, FBC_ASCR_STOP); 780 781 creator_ras_wait(sc); 782 783 /* Load firmware into all secondary floats. */ 784 if (ascr & 0x3e) { 785 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x3e); 786 creator_load_sram(sc, fw->fw_ucode, fw->fw_size); 787 } 788 789 /* Load firmware into primary float. */ 790 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x01); 791 creator_load_sram(sc, fw->fw_ucode, fw->fw_size); 792 793 /* Restart all floats. */ 794 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x3f); 795 FBC_WRITE(sc, FFB_FBC_ASCR, FBC_ASCR_RESTART); 796 797 creator_ras_wait(sc); 798 799 free(buf, M_DEVBUF, 0); 800 } 801 #endif /* SMALL_KERNEL */ 802 803 void 804 creator_load_sram(struct creator_softc *sc, u_int32_t *ucode, u_int32_t size) 805 { 806 uint64_t pstate, fprs; 807 caddr_t sram; 808 809 sram = bus_space_vaddr(sc->sc_bt, sc->sc_fbc_h) + FFB_FBC_SRAM36; 810 811 /* 812 * Apparently, loading the firmware into SRAM needs to be done 813 * using block copies. And block copies use the 814 * floating-point registers. Generally, using the FPU in the 815 * kernel is verboten. But since we load the firmware before 816 * userland processes are started, thrashing the 817 * floating-point registers is fine. We do need to enable the 818 * FPU before we access them though, otherwise we'll trap. 819 */ 820 pstate = sparc_rdpr(pstate); 821 sparc_wrpr(pstate, pstate | PSTATE_PEF, 0); 822 fprs = sparc_rd(fprs); 823 sparc_wr(fprs, FPRS_FEF, 0); 824 825 FBC_WRITE(sc, FFB_FBC_SRAMAR, 0); 826 827 while (size > 0) { 828 creator_ras_fifo_wait(sc, 16); 829 830 __asm__ volatile("ld [%0 + 0x00], %%f1\n\t" 831 "ld [%0 + 0x04], %%f0\n\t" 832 "ld [%0 + 0x08], %%f3\n\t" 833 "ld [%0 + 0x0c], %%f2\n\t" 834 "ld [%0 + 0x10], %%f5\n\t" 835 "ld [%0 + 0x14], %%f4\n\t" 836 "ld [%0 + 0x18], %%f7\n\t" 837 "ld [%0 + 0x1c], %%f6\n\t" 838 "ld [%0 + 0x20], %%f9\n\t" 839 "ld [%0 + 0x24], %%f8\n\t" 840 "ld [%0 + 0x28], %%f11\n\t" 841 "ld [%0 + 0x2c], %%f10\n\t" 842 "ld [%0 + 0x30], %%f13\n\t" 843 "ld [%0 + 0x34], %%f12\n\t" 844 "ld [%0 + 0x38], %%f15\n\t" 845 "ld [%0 + 0x3c], %%f14\n\t" 846 "membar #Sync\n\t" 847 "stda %%f0, [%1] 240\n\t" 848 "membar #Sync" 849 : : "r" (ucode), "r" (sram)); 850 851 ucode += 16; 852 size -= 16; 853 } 854 855 sparc_wr(fprs, fprs, 0); 856 sparc_wrpr(pstate, pstate, 0); 857 858 creator_ras_wait(sc); 859 } 860