1 /* $OpenBSD: creator.c,v 1.57 2022/10/21 18:55:42 miod Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/kernel.h> 32 #include <sys/device.h> 33 #include <sys/conf.h> 34 #include <sys/malloc.h> 35 36 #include <machine/autoconf.h> 37 #include <machine/bus.h> 38 #include <machine/fsr.h> 39 #include <machine/openfirm.h> 40 41 #include <dev/wscons/wsconsio.h> 42 #include <dev/wscons/wsdisplayvar.h> 43 #include <dev/rasops/rasops.h> 44 #include <machine/fbvar.h> 45 46 #include <sparc64/dev/creatorreg.h> 47 #include <sparc64/dev/creatorvar.h> 48 49 int creator_match(struct device *, void *, void *); 50 void creator_attach(struct device *, struct device *, void *); 51 int creator_ioctl(void *, u_long, caddr_t, int, struct proc *); 52 paddr_t creator_mmap(void *, off_t, int); 53 54 void creator_ras_fifo_wait(struct creator_softc *, int); 55 void creator_ras_wait(struct creator_softc *); 56 void creator_ras_init(struct creator_softc *); 57 int creator_ras_copyrows(void *, int, int, int); 58 int creator_ras_erasecols(void *, int, int, int, uint32_t); 59 int creator_ras_eraserows(void *, int, int, uint32_t); 60 void creator_ras_fill(struct creator_softc *); 61 void creator_ras_setfg(struct creator_softc *, int32_t); 62 63 int creator_setcursor(struct creator_softc *, struct wsdisplay_cursor *); 64 int creator_updatecursor(struct creator_softc *, u_int); 65 void creator_curs_enable(struct creator_softc *, u_int); 66 67 #ifndef SMALL_KERNEL 68 void creator_load_firmware(struct device *); 69 #endif /* SMALL_KERNEL */ 70 void creator_load_sram(struct creator_softc *, u_int32_t *, u_int32_t); 71 72 struct wsdisplay_accessops creator_accessops = { 73 .ioctl = creator_ioctl, 74 .mmap = creator_mmap 75 }; 76 77 struct cfdriver creator_cd = { 78 NULL, "creator", DV_DULL 79 }; 80 81 const struct cfattach creator_ca = { 82 sizeof(struct creator_softc), creator_match, creator_attach 83 }; 84 85 int 86 creator_match(struct device *parent, void *match, void *aux) 87 { 88 struct mainbus_attach_args *ma = aux; 89 90 if (strcmp(ma->ma_name, "SUNW,ffb") == 0 || 91 strcmp(ma->ma_name, "SUNW,afb") == 0) 92 return (1); 93 return (0); 94 } 95 96 void 97 creator_attach(struct device *parent, struct device *self, void *aux) 98 { 99 struct creator_softc *sc = (struct creator_softc *)self; 100 struct mainbus_attach_args *ma = aux; 101 extern int fbnode; 102 int i, nregs; 103 char *model; 104 int btype; 105 106 sc->sc_bt = ma->ma_bustag; 107 108 nregs = min(ma->ma_nreg, FFB_NREGS); 109 110 if (nregs <= FFB_REG_DFB24) { 111 printf(": no dfb24 regs found\n"); 112 return; 113 } 114 115 if (bus_space_map(sc->sc_bt, ma->ma_reg[FFB_REG_DFB24].ur_paddr, 116 ma->ma_reg[FFB_REG_DFB24].ur_len, BUS_SPACE_MAP_LINEAR, 117 &sc->sc_pixel_h)) { 118 printf(": failed to map dfb24\n"); 119 return; 120 } 121 122 if (bus_space_map(sc->sc_bt, ma->ma_reg[FFB_REG_FBC].ur_paddr, 123 ma->ma_reg[FFB_REG_FBC].ur_len, 0, &sc->sc_fbc_h)) { 124 printf(": failed to map fbc\n"); 125 goto unmap_dfb24; 126 } 127 128 if (bus_space_map(sc->sc_bt, ma->ma_reg[FFB_REG_DAC].ur_paddr, 129 ma->ma_reg[FFB_REG_DAC].ur_len, 0, &sc->sc_dac_h)) { 130 printf(": failed to map dac\n"); 131 goto unmap_fbc; 132 } 133 134 for (i = 0; i < nregs; i++) { 135 sc->sc_addrs[i] = ma->ma_reg[i].ur_paddr; 136 sc->sc_sizes[i] = ma->ma_reg[i].ur_len; 137 } 138 sc->sc_nreg = nregs; 139 140 sc->sc_console = (fbnode == ma->ma_node); 141 sc->sc_node = ma->ma_node; 142 143 if (strcmp(ma->ma_name, "SUNW,afb") == 0) 144 sc->sc_type = FFB_AFB; 145 146 /* 147 * Prom reports only the length of the fcode header, we need 148 * the whole thing. 149 */ 150 sc->sc_sizes[0] = 0x00400000; 151 152 if (sc->sc_type == FFB_CREATOR) { 153 btype = getpropint(sc->sc_node, "board_type", 0); 154 if ((btype & 7) == 3) 155 printf(": Creator3D"); 156 else 157 printf(": Creator"); 158 } else 159 printf(": Elite3D"); 160 161 model = getpropstring(sc->sc_node, "model"); 162 if (model == NULL || strlen(model) == 0) 163 model = "unknown"; 164 165 DAC_WRITE(sc, FFB_DAC_TYPE, DAC_TYPE_GETREV); 166 sc->sc_dacrev = DAC_READ(sc, FFB_DAC_VALUE) >> 28; 167 168 printf(", model %s, dac %u", model, sc->sc_dacrev); 169 170 if (sc->sc_type == FFB_AFB) 171 sc->sc_dacrev = 10; 172 173 fb_setsize(&sc->sc_sunfb, 32, 1152, 900, sc->sc_node, 0); 174 /* linesize has a fixed value, compensate */ 175 sc->sc_sunfb.sf_linebytes = 8192; 176 sc->sc_sunfb.sf_fbsize = sc->sc_sunfb.sf_height * 8192; 177 178 printf(", %dx%d\n", sc->sc_sunfb.sf_width, sc->sc_sunfb.sf_height); 179 180 sc->sc_sunfb.sf_ro.ri_bits = (void *)bus_space_vaddr(sc->sc_bt, 181 sc->sc_pixel_h); 182 sc->sc_sunfb.sf_ro.ri_hw = sc; 183 fbwscons_init(&sc->sc_sunfb, 0, sc->sc_console); 184 185 if ((sc->sc_sunfb.sf_dev.dv_cfdata->cf_flags & CREATOR_CFFLAG_NOACCEL) 186 == 0) { 187 sc->sc_sunfb.sf_ro.ri_ops.eraserows = creator_ras_eraserows; 188 sc->sc_sunfb.sf_ro.ri_ops.erasecols = creator_ras_erasecols; 189 sc->sc_sunfb.sf_ro.ri_ops.copyrows = creator_ras_copyrows; 190 creator_ras_init(sc); 191 192 #ifndef SMALL_KERNEL 193 /* 194 * Elite3D cards need a firmware for accelerated X to 195 * work. Console framebuffer acceleration will work 196 * without it though, so doing this late should be 197 * fine. 198 */ 199 if (sc->sc_type == FFB_AFB) 200 config_mountroot(self, creator_load_firmware); 201 #endif /* SMALL_KERNEL */ 202 } 203 204 if (sc->sc_console) 205 fbwscons_console_init(&sc->sc_sunfb, -1); 206 207 fbwscons_attach(&sc->sc_sunfb, &creator_accessops, sc->sc_console); 208 return; 209 210 unmap_fbc: 211 bus_space_unmap(sc->sc_bt, sc->sc_fbc_h, 212 ma->ma_reg[FFB_REG_FBC].ur_len); 213 unmap_dfb24: 214 bus_space_unmap(sc->sc_bt, sc->sc_pixel_h, 215 ma->ma_reg[FFB_REG_DFB24].ur_len); 216 } 217 218 int 219 creator_ioctl(void *v, u_long cmd, caddr_t data, int flags, struct proc *p) 220 { 221 struct creator_softc *sc = v; 222 struct wsdisplay_cursor *curs; 223 struct wsdisplay_fbinfo *wdf; 224 struct wsdisplay_curpos *pos; 225 u_char r[2], g[2], b[2]; 226 int error; 227 228 switch (cmd) { 229 case WSDISPLAYIO_GTYPE: 230 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 231 break; 232 case WSDISPLAYIO_SMODE: 233 sc->sc_mode = *(u_int *)data; 234 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 235 struct rasops_info *ri = &sc->sc_sunfb.sf_ro; 236 uint32_t attr; 237 238 if ((sc->sc_sunfb.sf_dev.dv_cfdata->cf_flags & 239 CREATOR_CFFLAG_NOACCEL) == 0) 240 creator_ras_init(sc); 241 242 /* Clear screen. */ 243 ri->ri_ops.pack_attr(ri, 244 WSCOL_BLACK, WSCOL_WHITE, WSATTR_WSCOLORS, &attr); 245 ri->ri_ops.eraserows(ri, 0, ri->ri_rows, attr); 246 } 247 break; 248 case WSDISPLAYIO_GINFO: 249 wdf = (void *)data; 250 wdf->height = sc->sc_sunfb.sf_height; 251 wdf->width = sc->sc_sunfb.sf_width; 252 wdf->depth = 32; 253 wdf->stride = sc->sc_sunfb.sf_linebytes; 254 wdf->offset = 0; 255 wdf->cmsize = 0; 256 break; 257 case WSDISPLAYIO_GETSUPPORTEDDEPTH: 258 *(u_int *)data = WSDISPLAYIO_DEPTH_24_32; 259 break; 260 case WSDISPLAYIO_LINEBYTES: 261 *(u_int *)data = sc->sc_sunfb.sf_linebytes; 262 break; 263 case WSDISPLAYIO_GCURSOR: 264 curs = (struct wsdisplay_cursor *)data; 265 if (curs->which & WSDISPLAY_CURSOR_DOCUR) 266 curs->enable = sc->sc_curs_enabled; 267 if (curs->which & WSDISPLAY_CURSOR_DOPOS) { 268 curs->pos.x = sc->sc_curs_pos.x; 269 curs->pos.y = sc->sc_curs_pos.y; 270 } 271 if (curs->which & WSDISPLAY_CURSOR_DOHOT) { 272 curs->hot.x = sc->sc_curs_hot.x; 273 curs->hot.y = sc->sc_curs_hot.y; 274 } 275 if (curs->which & WSDISPLAY_CURSOR_DOCMAP) { 276 curs->cmap.index = 0; 277 curs->cmap.count = 2; 278 r[0] = sc->sc_curs_fg >> 0; 279 g[0] = sc->sc_curs_fg >> 8; 280 b[0] = sc->sc_curs_fg >> 16; 281 r[1] = sc->sc_curs_bg >> 0; 282 g[1] = sc->sc_curs_bg >> 8; 283 b[1] = sc->sc_curs_bg >> 16; 284 error = copyout(r, curs->cmap.red, sizeof(r)); 285 if (error) 286 return (error); 287 error = copyout(g, curs->cmap.green, sizeof(g)); 288 if (error) 289 return (error); 290 error = copyout(b, curs->cmap.blue, sizeof(b)); 291 if (error) 292 return (error); 293 } 294 if (curs->which & WSDISPLAY_CURSOR_DOSHAPE) { 295 size_t l; 296 297 curs->size.x = sc->sc_curs_size.x; 298 curs->size.y = sc->sc_curs_size.y; 299 l = (sc->sc_curs_size.x * sc->sc_curs_size.y) / NBBY; 300 error = copyout(sc->sc_curs_image, curs->image, l); 301 if (error) 302 return (error); 303 error = copyout(sc->sc_curs_mask, curs->mask, l); 304 if (error) 305 return (error); 306 } 307 break; 308 case WSDISPLAYIO_SCURPOS: 309 pos = (struct wsdisplay_curpos *)data; 310 sc->sc_curs_pos.x = pos->x; 311 sc->sc_curs_pos.y = pos->y; 312 creator_updatecursor(sc, WSDISPLAY_CURSOR_DOPOS); 313 break; 314 case WSDISPLAYIO_GCURPOS: 315 pos = (struct wsdisplay_curpos *)data; 316 pos->x = sc->sc_curs_pos.x; 317 pos->y = sc->sc_curs_pos.y; 318 break; 319 case WSDISPLAYIO_SCURSOR: 320 curs = (struct wsdisplay_cursor *)data; 321 return (creator_setcursor(sc, curs)); 322 case WSDISPLAYIO_GCURMAX: 323 pos = (struct wsdisplay_curpos *)data; 324 pos->x = CREATOR_CURS_MAX; 325 pos->y = CREATOR_CURS_MAX; 326 break; 327 case WSDISPLAYIO_SVIDEO: 328 case WSDISPLAYIO_GVIDEO: 329 break; 330 331 case WSDISPLAYIO_GETCMAP: 332 case WSDISPLAYIO_PUTCMAP: 333 default: 334 return -1; /* not supported yet */ 335 } 336 337 return (0); 338 } 339 340 int 341 creator_setcursor(struct creator_softc *sc, struct wsdisplay_cursor *curs) 342 { 343 u_int8_t r[2], g[2], b[2], image[128], mask[128]; 344 int error; 345 size_t imcount; 346 347 /* 348 * Do stuff that can generate errors first, then we'll blast it 349 * all at once. 350 */ 351 if (curs->which & WSDISPLAY_CURSOR_DOCMAP) { 352 if (curs->cmap.count < 2) 353 return (EINVAL); 354 error = copyin(curs->cmap.red, r, sizeof(r)); 355 if (error) 356 return (error); 357 error = copyin(curs->cmap.green, g, sizeof(g)); 358 if (error) 359 return (error); 360 error = copyin(curs->cmap.blue, b, sizeof(b)); 361 if (error) 362 return (error); 363 } 364 365 if (curs->which & WSDISPLAY_CURSOR_DOSHAPE) { 366 if (curs->size.x > CREATOR_CURS_MAX || 367 curs->size.y > CREATOR_CURS_MAX) 368 return (EINVAL); 369 imcount = (curs->size.x * curs->size.y) / NBBY; 370 error = copyin(curs->image, image, imcount); 371 if (error) 372 return (error); 373 error = copyin(curs->mask, mask, imcount); 374 if (error) 375 return (error); 376 } 377 378 /* 379 * Ok, everything is in kernel space and sane, update state. 380 */ 381 382 if (curs->which & WSDISPLAY_CURSOR_DOCUR) 383 sc->sc_curs_enabled = curs->enable; 384 if (curs->which & WSDISPLAY_CURSOR_DOPOS) { 385 sc->sc_curs_pos.x = curs->pos.x; 386 sc->sc_curs_pos.y = curs->pos.y; 387 } 388 if (curs->which & WSDISPLAY_CURSOR_DOHOT) { 389 sc->sc_curs_hot.x = curs->hot.x; 390 sc->sc_curs_hot.y = curs->hot.y; 391 } 392 if (curs->which & WSDISPLAY_CURSOR_DOCMAP) { 393 sc->sc_curs_fg = ((r[0] << 0) | (g[0] << 8) | (b[0] << 16)); 394 sc->sc_curs_bg = ((r[1] << 0) | (g[1] << 8) | (b[1] << 16)); 395 } 396 if (curs->which & WSDISPLAY_CURSOR_DOSHAPE) { 397 sc->sc_curs_size.x = curs->size.x; 398 sc->sc_curs_size.y = curs->size.y; 399 bcopy(image, sc->sc_curs_image, imcount); 400 bcopy(mask, sc->sc_curs_mask, imcount); 401 } 402 403 creator_updatecursor(sc, curs->which); 404 405 return (0); 406 } 407 408 void 409 creator_curs_enable(struct creator_softc *sc, u_int ena) 410 { 411 u_int32_t v; 412 413 DAC_WRITE(sc, FFB_DAC_TYPE2, DAC_TYPE2_CURSENAB); 414 if (sc->sc_dacrev <= 2) 415 v = ena ? 3 : 0; 416 else 417 v = ena ? 0 : 3; 418 DAC_WRITE(sc, FFB_DAC_VALUE2, v); 419 } 420 421 int 422 creator_updatecursor(struct creator_softc *sc, u_int which) 423 { 424 creator_curs_enable(sc, 0); 425 426 if (which & WSDISPLAY_CURSOR_DOCMAP) { 427 DAC_WRITE(sc, FFB_DAC_TYPE2, DAC_TYPE2_CURSCMAP); 428 DAC_WRITE(sc, FFB_DAC_VALUE2, sc->sc_curs_fg); 429 DAC_WRITE(sc, FFB_DAC_VALUE2, sc->sc_curs_bg); 430 } 431 432 if (which & (WSDISPLAY_CURSOR_DOPOS | WSDISPLAY_CURSOR_DOHOT)) { 433 u_int32_t x, y; 434 435 x = sc->sc_curs_pos.x + CREATOR_CURS_MAX - sc->sc_curs_hot.x; 436 y = sc->sc_curs_pos.y + CREATOR_CURS_MAX - sc->sc_curs_hot.y; 437 DAC_WRITE(sc, FFB_DAC_TYPE2, DAC_TYPE2_CURSPOS); 438 DAC_WRITE(sc, FFB_DAC_VALUE2, 439 ((x & 0xffff) << 16) | (y & 0xffff)); 440 } 441 442 if (which & WSDISPLAY_CURSOR_DOCUR) 443 creator_curs_enable(sc, sc->sc_curs_enabled); 444 445 return (0); 446 } 447 448 const struct creator_mappings { 449 bus_addr_t uoff; 450 bus_addr_t poff; 451 bus_size_t ulen; 452 } creator_map[] = { 453 { FFB_VOFF_SFB8R, FFB_POFF_SFB8R, FFB_VLEN_SFB8R }, 454 { FFB_VOFF_SFB8G, FFB_POFF_SFB8G, FFB_VLEN_SFB8G }, 455 { FFB_VOFF_SFB8B, FFB_POFF_SFB8B, FFB_VLEN_SFB8B }, 456 { FFB_VOFF_SFB8X, FFB_POFF_SFB8X, FFB_VLEN_SFB8X }, 457 { FFB_VOFF_SFB32, FFB_POFF_SFB32, FFB_VLEN_SFB32 }, 458 { FFB_VOFF_SFB64, FFB_POFF_SFB64, FFB_VLEN_SFB64 }, 459 { FFB_VOFF_FBC_REGS, FFB_POFF_FBC_REGS, FFB_VLEN_FBC_REGS }, 460 { FFB_VOFF_BM_FBC_REGS, FFB_POFF_BM_FBC_REGS, FFB_VLEN_BM_FBC_REGS }, 461 { FFB_VOFF_DFB8R, FFB_POFF_DFB8R, FFB_VLEN_DFB8R }, 462 { FFB_VOFF_DFB8G, FFB_POFF_DFB8G, FFB_VLEN_DFB8G }, 463 { FFB_VOFF_DFB8B, FFB_POFF_DFB8B, FFB_VLEN_DFB8B }, 464 { FFB_VOFF_DFB8X, FFB_POFF_DFB8X, FFB_VLEN_DFB8X }, 465 { FFB_VOFF_DFB24, FFB_POFF_DFB24, FFB_VLEN_DFB24 }, 466 { FFB_VOFF_DFB32, FFB_POFF_DFB32, FFB_VLEN_DFB32 }, 467 { FFB_VOFF_DFB422A, FFB_POFF_DFB422A, FFB_VLEN_DFB422A }, 468 { FFB_VOFF_DFB422AD, FFB_POFF_DFB422AD, FFB_VLEN_DFB422AD }, 469 { FFB_VOFF_DFB24B, FFB_POFF_DFB24B, FFB_VLEN_DFB24B }, 470 { FFB_VOFF_DFB422B, FFB_POFF_DFB422B, FFB_VLEN_DFB422B }, 471 { FFB_VOFF_DFB422BD, FFB_POFF_DFB422BD, FFB_VLEN_DFB422BD }, 472 { FFB_VOFF_SFB16Z, FFB_POFF_SFB16Z, FFB_VLEN_SFB16Z }, 473 { FFB_VOFF_SFB8Z, FFB_POFF_SFB8Z, FFB_VLEN_SFB8Z }, 474 { FFB_VOFF_SFB422, FFB_POFF_SFB422, FFB_VLEN_SFB422 }, 475 { FFB_VOFF_SFB422D, FFB_POFF_SFB422D, FFB_VLEN_SFB422D }, 476 { FFB_VOFF_FBC_KREGS, FFB_POFF_FBC_KREGS, FFB_VLEN_FBC_KREGS }, 477 { FFB_VOFF_DAC, FFB_POFF_DAC, FFB_VLEN_DAC }, 478 { FFB_VOFF_PROM, FFB_POFF_PROM, FFB_VLEN_PROM }, 479 { FFB_VOFF_EXP, FFB_POFF_EXP, FFB_VLEN_EXP }, 480 }; 481 #define CREATOR_NMAPPINGS nitems(creator_map) 482 483 paddr_t 484 creator_mmap(void *vsc, off_t off, int prot) 485 { 486 paddr_t x; 487 struct creator_softc *sc = vsc; 488 int i; 489 490 switch (sc->sc_mode) { 491 case WSDISPLAYIO_MODE_MAPPED: 492 /* Turn virtual offset into physical offset */ 493 for (i = 0; i < CREATOR_NMAPPINGS; i++) { 494 if (off >= creator_map[i].uoff && 495 off < (creator_map[i].uoff + creator_map[i].ulen)) 496 break; 497 } 498 if (i == CREATOR_NMAPPINGS) 499 break; 500 501 off -= creator_map[i].uoff; 502 off += creator_map[i].poff; 503 off += sc->sc_addrs[0]; 504 505 /* Map based on physical offset */ 506 for (i = 0; i < sc->sc_nreg; i++) { 507 /* Before this set? */ 508 if (off < sc->sc_addrs[i]) 509 continue; 510 /* After this set? */ 511 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 512 continue; 513 514 x = bus_space_mmap(sc->sc_bt, 0, off, prot, 515 BUS_SPACE_MAP_LINEAR); 516 return (x); 517 } 518 break; 519 case WSDISPLAYIO_MODE_DUMBFB: 520 if (sc->sc_nreg <= FFB_REG_DFB24) 521 break; 522 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 523 return (bus_space_mmap(sc->sc_bt, 524 sc->sc_addrs[FFB_REG_DFB24], off, prot, 525 BUS_SPACE_MAP_LINEAR)); 526 break; 527 } 528 529 return (-1); 530 } 531 532 void 533 creator_ras_fifo_wait(struct creator_softc *sc, int n) 534 { 535 int32_t cache = sc->sc_fifo_cache; 536 537 if (cache < n) { 538 do { 539 cache = FBC_READ(sc, FFB_FBC_UCSR); 540 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 541 } while (cache < n); 542 } 543 sc->sc_fifo_cache = cache - n; 544 } 545 546 void 547 creator_ras_wait(struct creator_softc *sc) 548 { 549 u_int32_t ucsr, r; 550 551 while (1) { 552 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 553 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 554 break; 555 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 556 if (r != 0) 557 FBC_WRITE(sc, FFB_FBC_UCSR, r); 558 } 559 } 560 561 void 562 creator_ras_init(struct creator_softc *sc) 563 { 564 creator_ras_fifo_wait(sc, 7); 565 FBC_WRITE(sc, FFB_FBC_PPC, 566 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | 567 FBC_PPC_APE_DIS | FBC_PPC_CS_CONST); 568 FBC_WRITE(sc, FFB_FBC_FBC, 569 FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 570 FFB_FBC_XE_OFF | FFB_FBC_RGBE_MASK); 571 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 572 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 573 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 574 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 575 sc->sc_fg_cache = 0; 576 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 577 creator_ras_wait(sc); 578 } 579 580 int 581 creator_ras_eraserows(void *cookie, int row, int n, uint32_t attr) 582 { 583 struct rasops_info *ri = cookie; 584 struct creator_softc *sc = ri->ri_hw; 585 int bg, fg; 586 587 if (row < 0) { 588 n += row; 589 row = 0; 590 } 591 if (row + n > ri->ri_rows) 592 n = ri->ri_rows - row; 593 if (n <= 0) 594 return 0; 595 596 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 597 creator_ras_fill(sc); 598 creator_ras_setfg(sc, ri->ri_devcmap[bg]); 599 creator_ras_fifo_wait(sc, 4); 600 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 601 FBC_WRITE(sc, FFB_FBC_BY, 0); 602 FBC_WRITE(sc, FFB_FBC_BX, 0); 603 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 604 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 605 } else { 606 row *= ri->ri_font->fontheight; 607 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 608 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 609 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 610 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 611 } 612 creator_ras_wait(sc); 613 614 return 0; 615 } 616 617 int 618 creator_ras_erasecols(void *cookie, int row, int col, int n, uint32_t attr) 619 { 620 struct rasops_info *ri = cookie; 621 struct creator_softc *sc = ri->ri_hw; 622 int fg, bg; 623 624 if ((row < 0) || (row >= ri->ri_rows)) 625 return 0; 626 if (col < 0) { 627 n += col; 628 col = 0; 629 } 630 if (col + n > ri->ri_cols) 631 n = ri->ri_cols - col; 632 if (n <= 0) 633 return 0; 634 n *= ri->ri_font->fontwidth; 635 col *= ri->ri_font->fontwidth; 636 row *= ri->ri_font->fontheight; 637 638 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 639 creator_ras_fill(sc); 640 creator_ras_setfg(sc, ri->ri_devcmap[bg]); 641 creator_ras_fifo_wait(sc, 4); 642 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 643 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 644 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 645 FBC_WRITE(sc, FFB_FBC_BW, n - 1); 646 creator_ras_wait(sc); 647 648 return 0; 649 } 650 651 void 652 creator_ras_fill(struct creator_softc *sc) 653 { 654 creator_ras_fifo_wait(sc, 2); 655 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 656 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 657 creator_ras_wait(sc); 658 } 659 660 int 661 creator_ras_copyrows(void *cookie, int src, int dst, int n) 662 { 663 struct rasops_info *ri = cookie; 664 struct creator_softc *sc = ri->ri_hw; 665 666 if (dst == src) 667 return 0; 668 if (src < 0) { 669 n += src; 670 src = 0; 671 } 672 if ((src + n) > ri->ri_rows) 673 n = ri->ri_rows - src; 674 if (dst < 0) { 675 n += dst; 676 dst = 0; 677 } 678 if ((dst + n) > ri->ri_rows) 679 n = ri->ri_rows - dst; 680 if (n <= 0) 681 return 0; 682 n *= ri->ri_font->fontheight; 683 src *= ri->ri_font->fontheight; 684 dst *= ri->ri_font->fontheight; 685 686 creator_ras_fifo_wait(sc, 8); 687 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 688 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 689 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 690 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 691 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 692 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 693 FBC_WRITE(sc, FFB_FBC_BH, n); 694 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 695 creator_ras_wait(sc); 696 697 return 0; 698 } 699 700 void 701 creator_ras_setfg(struct creator_softc *sc, int32_t fg) 702 { 703 creator_ras_fifo_wait(sc, 1); 704 if (fg == sc->sc_fg_cache) 705 return; 706 sc->sc_fg_cache = fg; 707 FBC_WRITE(sc, FFB_FBC_FG, fg); 708 creator_ras_wait(sc); 709 } 710 711 #ifndef SMALL_KERNEL 712 struct creator_firmware { 713 char fw_ident[8]; 714 u_int32_t fw_size; 715 u_int32_t fw_reserved[2]; 716 u_int32_t fw_ucode[0]; 717 }; 718 719 #define CREATOR_FIRMWARE_REV 0x101 720 721 void 722 creator_load_firmware(struct device *self) 723 { 724 struct creator_softc *sc = (struct creator_softc *)self; 725 struct creator_firmware *fw; 726 u_int32_t ascr; 727 size_t buflen; 728 u_char *buf; 729 int error; 730 731 error = loadfirmware("afb", &buf, &buflen); 732 if (error) { 733 printf("%s: error %d, could not read firmware %s\n", 734 sc->sc_sunfb.sf_dev.dv_xname, error, "afb"); 735 return; 736 } 737 738 fw = (struct creator_firmware *)buf; 739 if (sizeof(*fw) > buflen || 740 fw->fw_size * sizeof(u_int32_t) > (buflen - sizeof(*fw))) { 741 printf("%s: corrupt firmware\n", sc->sc_sunfb.sf_dev.dv_xname); 742 free(buf, M_DEVBUF, 0); 743 return; 744 } 745 746 printf("%s: firmware rev %d.%d.%d\n", sc->sc_sunfb.sf_dev.dv_xname, 747 (fw->fw_ucode[CREATOR_FIRMWARE_REV] >> 16) & 0xff, 748 (fw->fw_ucode[CREATOR_FIRMWARE_REV] >> 8) & 0xff, 749 fw->fw_ucode[CREATOR_FIRMWARE_REV] & 0xff); 750 751 ascr = FBC_READ(sc, FFB_FBC_ASCR); 752 753 /* Stop all floats. */ 754 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x3f); 755 FBC_WRITE(sc, FFB_FBC_ASCR, FBC_ASCR_STOP); 756 757 creator_ras_wait(sc); 758 759 /* Load firmware into all secondary floats. */ 760 if (ascr & 0x3e) { 761 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x3e); 762 creator_load_sram(sc, fw->fw_ucode, fw->fw_size); 763 } 764 765 /* Load firmware into primary float. */ 766 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x01); 767 creator_load_sram(sc, fw->fw_ucode, fw->fw_size); 768 769 /* Restart all floats. */ 770 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x3f); 771 FBC_WRITE(sc, FFB_FBC_ASCR, FBC_ASCR_RESTART); 772 773 creator_ras_wait(sc); 774 775 free(buf, M_DEVBUF, 0); 776 } 777 #endif /* SMALL_KERNEL */ 778 779 void 780 creator_load_sram(struct creator_softc *sc, u_int32_t *ucode, u_int32_t size) 781 { 782 uint64_t pstate, fprs; 783 caddr_t sram; 784 785 sram = bus_space_vaddr(sc->sc_bt, sc->sc_fbc_h) + FFB_FBC_SRAM36; 786 787 /* 788 * Apparently, loading the firmware into SRAM needs to be done 789 * using block copies. And block copies use the 790 * floating-point registers. Generally, using the FPU in the 791 * kernel is verboten. But since we load the firmware before 792 * userland processes are started, thrashing the 793 * floating-point registers is fine. We do need to enable the 794 * FPU before we access them though, otherwise we'll trap. 795 */ 796 pstate = sparc_rdpr(pstate); 797 sparc_wrpr(pstate, pstate | PSTATE_PEF, 0); 798 fprs = sparc_rd(fprs); 799 sparc_wr(fprs, FPRS_FEF, 0); 800 801 FBC_WRITE(sc, FFB_FBC_SRAMAR, 0); 802 803 while (size > 0) { 804 creator_ras_fifo_wait(sc, 16); 805 806 __asm__ volatile("ld [%0 + 0x00], %%f1\n\t" 807 "ld [%0 + 0x04], %%f0\n\t" 808 "ld [%0 + 0x08], %%f3\n\t" 809 "ld [%0 + 0x0c], %%f2\n\t" 810 "ld [%0 + 0x10], %%f5\n\t" 811 "ld [%0 + 0x14], %%f4\n\t" 812 "ld [%0 + 0x18], %%f7\n\t" 813 "ld [%0 + 0x1c], %%f6\n\t" 814 "ld [%0 + 0x20], %%f9\n\t" 815 "ld [%0 + 0x24], %%f8\n\t" 816 "ld [%0 + 0x28], %%f11\n\t" 817 "ld [%0 + 0x2c], %%f10\n\t" 818 "ld [%0 + 0x30], %%f13\n\t" 819 "ld [%0 + 0x34], %%f12\n\t" 820 "ld [%0 + 0x38], %%f15\n\t" 821 "ld [%0 + 0x3c], %%f14\n\t" 822 "membar #Sync\n\t" 823 "stda %%f0, [%1] 240\n\t" 824 "membar #Sync" 825 : : "r" (ucode), "r" (sram)); 826 827 ucode += 16; 828 size -= 16; 829 } 830 831 sparc_wr(fprs, fprs, 0); 832 sparc_wrpr(pstate, pstate, 0); 833 834 creator_ras_wait(sc); 835 } 836