1 /* $OpenBSD: ifb.c,v 1.20 2013/07/15 18:28:46 miod Exp $ */ 2 3 /* 4 * Copyright (c) 2007, 2008, 2009 Miodrag Vallat. 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Least-effort driver for the Sun Expert3D cards (based on the 21 * ``Wildcat'' chips). 22 * 23 * There is no public documentation for these chips available. 24 * Since they are no longer supported by 3DLabs (which got bought by 25 * Creative), and Sun does not want to publish even minimal information 26 * or source code, the best we can do is experiment. 27 * 28 * Quoting Alan Coopersmith in 29 * http://mail.opensolaris.org/pipermail/opensolaris-discuss/2005-December/011885.html 30 * ``Unfortunately, the lawyers have asked we not give details about why 31 * specific components are not being released.'' 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/ioctl.h> 39 #include <sys/malloc.h> 40 #include <sys/pciio.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <machine/autoconf.h> 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 #include <machine/openfirm.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 52 #include <dev/wscons/wsconsio.h> 53 #include <dev/wscons/wsdisplayvar.h> 54 55 #include <dev/rasops/rasops.h> 56 57 #include <machine/fbvar.h> 58 59 #ifdef APERTURE 60 extern int allowaperture; 61 #endif 62 63 /* 64 * Parts of the following hardware knowledge come from David S. Miller's 65 * XVR-500 Linux driver (drivers/video/sunxvr500.c). 66 */ 67 68 /* 69 * The Expert3D and Expert3d-Lite cards are built around the Wildcat 70 * 5110, 6210 and 7210 chips. 71 * 72 * The card exposes the following resources: 73 * - a 32MB (ifb), 64MB (xvr600) or 128MB (jfb) aperture window in which 74 * views to the different frame buffer areas can be mapped, in the first BAR. 75 * - a 64KB or 128KB PROM and registers area, in the second BAR. 76 * - a 8MB ``direct burst'' memory mapping, in the third BAR. 77 * 78 * The location of this BAR range is pointed to by a board-specific PCI 79 * configuration register. 80 * 81 * In the state the PROM leaves us in, the 8MB frame buffer windows map 82 * the video memory as interleaved stripes, of which the non-visible parts 83 * can still be addressed (probably for fast screen switching). 84 * 85 * Unfortunately, since we do not know how to reconfigure the stripes 86 * to provide at least a linear frame buffer, we have to write to both 87 * windows and have them provide the complete image. 88 * 89 * Moreover, high pixel values in the overlay planes (such as 0xff or 0xfe) 90 * seem to enable other planes with random contents, so we'll limit ourselves 91 * to 7bpp operation. 92 */ 93 94 /* 95 * The Fcode driver sets up a communication structure, allowing third-party 96 * code to reprogram the video mode while still allowing the Fcode routines 97 * to access the overlay planes. 98 * 99 * We'll use this information as well, although so far it's unlikely 100 * any code will do so, as long as the only documentation for this 101 * hardware amounts to zilch. 102 */ 103 104 /* probably some form of signature */ 105 #define IFB_SHARED_SIGNATURE 0x00 106 #define SIG_IFB 0x09209911 107 #define SIG_JFB 0x05140213 108 #define IFB_SHARED_MONITOR_MODE 0x10 109 #define IFB_SHARED_WIDTH 0x14 110 #define IFB_SHARED_HEIGHT 0x18 111 #define IFB_SHARED_V_FREQ 0x1c 112 #define IFB_SHARED_TIMING_H_FP 0x20 113 #define IFB_SHARED_TIMING_H_SYNC 0x24 114 #define IFB_SHARED_TIMING_H_BP 0x28 115 #define IFB_SHARED_TIMING_V_FP 0x2c 116 #define IFB_SHARED_TIMING_V_SYNC 0x30 117 #define IFB_SHARED_TIMING_V_BP 0x34 118 #define IFB_SHARED_TIMING_FLAGS 0x38 119 #define IFB_SHARED_CMAP_DIRTY 0x3c 120 #define IFB_SHARED_TERM8_GSR 0x4c 121 #define IFB_SHARED_TERM8_SPR 0x50 122 #define IFB_SHARED_TERM8_SPLR 0x54 123 124 /* 125 * The Expert3D has an extra BAR that is not present on the -Lite 126 * version. This register contains bits that tell us how many BARs to 127 * skip before we get to the BARs that interest us. 128 */ 129 #define IFB_PCI_CFG 0x5c 130 #define IFB_PCI_CFG_BAR_OFFSET(x) ((x & 0x000000e0) >> 3) 131 132 /* 133 * 6000 (jfb) / 8000 (ifb) engine command 134 * This register is used to issue (some) commands sequences to the 135 * acceleration hardware. 136 */ 137 #define JFB_REG_ENGINE 0x6000 138 #define IFB_REG_ENGINE 0x8000 139 140 /* 141 * 8040 component configuration 142 * This register controls which parts of the board will be addressed by 143 * writes to other configuration registers. 144 * Apparently the low two bytes control the frame buffer windows for the 145 * given head (starting at 1). 146 * The high two bytes are texture related. 147 */ 148 #define IFB_REG_COMPONENT_SELECT 0x8040 149 150 /* 151 * 8044 status 152 * This register has a bit that signals completion of commands issued 153 * to the acceleration hardware. 154 */ 155 #define IFB_REG_STATUS 0x8044 156 #define IFB_REG_STATUS_DONE 0x00000004 157 158 /* 159 * 8058 magnifying configuration 160 * This register apparently controls magnifying. 161 * bits 5-6 select the window width divider (00: by 2, 01: by 4, 10: by 8, 162 * 11: by 16) 163 * bits 7-8 select the zoom factor (00: disabled, 01: x2, 10: x4, 11: x8) 164 */ 165 #define IFB_REG_MAGNIFY 0x8058 166 #define IFB_REG_MAGNIFY_DISABLE 0x00000000 167 #define IFB_REG_MAGNIFY_X2 0x00000040 168 #define IFB_REG_MAGNIFY_X4 0x00000080 169 #define IFB_REG_MAGNIFY_X8 0x000000c0 170 #define IFB_REG_MAGNIFY_WINDIV2 0x00000000 171 #define IFB_REG_MAGNIFY_WINDIV4 0x00000010 172 #define IFB_REG_MAGNIFY_WINDIV8 0x00000020 173 #define IFB_REG_MAGNIFY_WINDIV16 0x00000030 174 175 /* 176 * 8070 display resolution 177 * Contains the size of the display, as ((height - 1) << 16) | (width - 1) 178 */ 179 #define IFB_REG_RESOLUTION 0x8070 180 /* 181 * 8074 configuration register 182 * Contains 0x1a000088 | ((Log2 stride) << 16) 183 */ 184 #define IFB_REG_CONFIG 0x8074 185 /* 186 * 8078 32bit frame buffer window #0 (8 to 9 MB) 187 * Contains the offset (relative to BAR0) of the 32 bit frame buffer window. 188 */ 189 #define IFB_REG_FB32_0 0x8078 190 /* 191 * 807c 32bit frame buffer window #1 (8 to 9 MB) 192 * Contains the offset (relative to BAR0) of the 32 bit frame buffer window. 193 */ 194 #define IFB_REG_FB32_1 0x807c 195 /* 196 * 8080 8bit frame buffer window #0 (2 to 2.2 MB) 197 * Contains the offset (relative to BAR0) of the 8 bit frame buffer window. 198 */ 199 #define IFB_REG_FB8_0 0x8080 200 /* 201 * 8084 8bit frame buffer window #1 (2 to 2.2 MB) 202 * Contains the offset (relative to BAR0) of the 8 bit frame buffer window. 203 */ 204 #define IFB_REG_FB8_1 0x8084 205 /* 206 * 8088 unknown window (as large as a 32 bit frame buffer) 207 */ 208 #define IFB_REG_FB_UNK0 0x8088 209 /* 210 * 808c unknown window (as large as a 8 bit frame buffer) 211 */ 212 #define IFB_REG_FB_UNK1 0x808c 213 /* 214 * 8090 unknown window (as large as a 8 bit frame buffer) 215 */ 216 #define IFB_REG_FB_UNK2 0x8090 217 218 /* 219 * 80bc RAMDAC palette index register 220 */ 221 #define IFB_REG_CMAP_INDEX 0x80bc 222 /* 223 * 80c0 RAMDAC palette data register 224 */ 225 #define IFB_REG_CMAP_DATA 0x80c0 226 227 /* 228 * 80e4 DPMS state register 229 * States ``off'' and ``suspend'' need chip reprogramming before video can 230 * be enabled again. 231 */ 232 #define IFB_REG_DPMS_STATE 0x80e4 233 #define IFB_REG_DPMS_OFF 0x00000000 234 #define IFB_REG_DPMS_SUSPEND 0x00000001 235 #define IFB_REG_DPMS_STANDBY 0x00000002 236 #define IFB_REG_DPMS_ON 0x00000003 237 238 /* 239 * (some) ROP codes 240 */ 241 242 #define IFB_ROP_CLEAR 0x00000000 /* clear bits in rop mask */ 243 #define IFB_ROP_SRC 0x00330000 /* copy src bits matching rop mask */ 244 #define IFB_ROP_XOR 0x00cc0000 /* xor src bits with rop mask */ 245 #define IFB_ROP_SET 0x00ff0000 /* set bits in rop mask */ 246 247 #define IFB_COORDS(x, y) ((x) | (y) << 16) 248 249 /* blitter directions */ 250 #define IFB_BLT_DIR_BACKWARDS_Y (0x08 | 0x02) 251 #define IFB_BLT_DIR_BACKWARDS_X (0x04 | 0x01) 252 253 #define IFB_PIXELMASK 0x7f /* 7bpp */ 254 255 struct ifb_softc { 256 struct sunfb sc_sunfb; 257 258 bus_space_tag_t sc_mem_t; 259 pcitag_t sc_pcitag; 260 261 /* overlays mappings */ 262 bus_space_handle_t sc_mem_h; 263 bus_addr_t sc_membase, sc_fb8bank0_base, sc_fb8bank1_base; 264 bus_size_t sc_memlen; 265 vaddr_t sc_memvaddr, sc_fb8bank0_vaddr, sc_fb8bank1_vaddr; 266 267 /* registers mapping */ 268 bus_space_handle_t sc_reg_h; 269 bus_addr_t sc_regbase; 270 bus_size_t sc_reglen; 271 272 /* communication area */ 273 volatile uint32_t *sc_comm; 274 275 /* acceleration information */ 276 u_int sc_acceltype; 277 #define IFB_ACCEL_NONE 0 278 #define IFB_ACCEL_IFB 1 /* Expert3D style */ 279 #define IFB_ACCEL_JFB 2 /* XVR-500 style */ 280 void (*sc_rop)(void *, int, int, int, int, int, int, uint32_t, int32_t); 281 282 /* wsdisplay related goo */ 283 u_int sc_mode; 284 struct wsdisplay_emulops sc_old_ops; 285 u_int8_t sc_cmap_red[256]; 286 u_int8_t sc_cmap_green[256]; 287 u_int8_t sc_cmap_blue[256]; 288 }; 289 290 int ifb_ioctl(void *, u_long, caddr_t, int, struct proc *); 291 paddr_t ifb_mmap(void *, off_t, int); 292 void ifb_burner(void *, u_int, u_int); 293 294 struct wsdisplay_accessops ifb_accessops = { 295 ifb_ioctl, 296 ifb_mmap, 297 NULL, /* alloc_screen */ 298 NULL, /* free_screen */ 299 NULL, /* show_screen */ 300 NULL, /* load_font */ 301 NULL, /* scrollback */ 302 NULL, /* getchar */ 303 ifb_burner, 304 NULL /* pollc */ 305 }; 306 307 int ifbmatch(struct device *, void *, void *); 308 void ifbattach(struct device *, struct device *, void *); 309 310 struct cfattach ifb_ca = { 311 sizeof (struct ifb_softc), ifbmatch, ifbattach 312 }; 313 314 struct cfdriver ifb_cd = { 315 NULL, "ifb", DV_DULL 316 }; 317 318 int ifb_accel_identify(const char *); 319 static inline 320 u_int ifb_dac_value(u_int, u_int, u_int); 321 int ifb_getcmap(struct ifb_softc *, struct wsdisplay_cmap *); 322 static inline 323 int ifb_is_console(int); 324 int ifb_mapregs(struct ifb_softc *, struct pci_attach_args *); 325 int ifb_putcmap(struct ifb_softc *, struct wsdisplay_cmap *); 326 void ifb_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t); 327 void ifb_setcolormap(struct sunfb *, 328 void (*)(void *, u_int, u_int8_t, u_int8_t, u_int8_t)); 329 330 void ifb_copyrect(struct ifb_softc *, int, int, int, int, int, int); 331 void ifb_fillrect(struct ifb_softc *, int, int, int, int, int); 332 static inline 333 void ifb_rop(struct ifb_softc *, int, int, int, int, int, int, uint32_t, 334 int32_t); 335 void ifb_rop_common(struct ifb_softc *, bus_addr_t, int, int, int, int, 336 int, int, uint32_t, int32_t); 337 void ifb_rop_ifb(void *, int, int, int, int, int, int, uint32_t, int32_t); 338 void ifb_rop_jfb(void *, int, int, int, int, int, int, uint32_t, int32_t); 339 int ifb_rop_wait(struct ifb_softc *); 340 341 int ifb_putchar_dumb(void *, int, int, u_int, long); 342 int ifb_copycols_dumb(void *, int, int, int, int); 343 int ifb_erasecols_dumb(void *, int, int, int, long); 344 int ifb_copyrows_dumb(void *, int, int, int); 345 int ifb_eraserows_dumb(void *, int, int, long); 346 int ifb_do_cursor_dumb(struct rasops_info *); 347 348 int ifb_putchar(void *, int, int, u_int, long); 349 int ifb_copycols(void *, int, int, int, int); 350 int ifb_erasecols(void *, int, int, int, long); 351 int ifb_copyrows(void *, int, int, int); 352 int ifb_eraserows(void *, int, int, long); 353 int ifb_do_cursor(struct rasops_info *); 354 355 int 356 ifbmatch(struct device *parent, void *cf, void *aux) 357 { 358 return ifb_ident(aux); 359 } 360 361 void 362 ifbattach(struct device *parent, struct device *self, void *aux) 363 { 364 struct ifb_softc *sc = (struct ifb_softc *)self; 365 struct pci_attach_args *paa = aux; 366 struct rasops_info *ri; 367 uint32_t dev_comm; 368 int node, console; 369 char *name, *text; 370 char namebuf[32]; 371 372 sc->sc_mem_t = paa->pa_memt; 373 sc->sc_pcitag = paa->pa_tag; 374 375 node = PCITAG_NODE(paa->pa_tag); 376 console = ifb_is_console(node); 377 378 printf("\n"); 379 380 /* 381 * Multiple heads appear as PCI subfunctions. 382 * However, the ofw node for it lacks most properties, 383 * and its BAR only give access to registers, not 384 * frame buffer memory. 385 */ 386 if (!node_has_property(node, "device_type")) { 387 printf("%s: secondary output not supported yet\n", 388 self->dv_xname); 389 return; 390 } 391 392 /* 393 * Describe the beast. 394 */ 395 396 name = text = getpropstringA(node, "name", namebuf); 397 if (strncmp(text, "SUNW,", 5) == 0) 398 text += 5; 399 printf("%s: %s", self->dv_xname, text); 400 text = getpropstring(node, "model"); 401 if (*text != '\0') 402 printf(" (%s)", text); 403 404 if (ifb_mapregs(sc, paa)) 405 return; 406 407 sc->sc_fb8bank0_base = bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 408 IFB_REG_FB8_0); 409 sc->sc_fb8bank1_base = bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 410 IFB_REG_FB8_1); 411 412 sc->sc_memvaddr = (vaddr_t)bus_space_vaddr(sc->sc_mem_t, sc->sc_mem_h); 413 sc->sc_fb8bank0_vaddr = sc->sc_memvaddr + 414 sc->sc_fb8bank0_base - sc->sc_membase; 415 sc->sc_fb8bank1_vaddr = sc->sc_memvaddr + 416 sc->sc_fb8bank1_base - sc->sc_membase; 417 418 /* 419 * The values stored into the node properties might have been 420 * modified since the Fcode was last run. Pick the geometry 421 * information from the configuration registers instead. 422 * This replaces 423 fb_setsize(&sc->sc_sunfb, 8, 1152, 900, node, 0); 424 */ 425 426 sc->sc_sunfb.sf_width = (bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 427 IFB_REG_RESOLUTION) & 0xffff) + 1; 428 sc->sc_sunfb.sf_height = (bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 429 IFB_REG_RESOLUTION) >> 16) + 1; 430 sc->sc_sunfb.sf_depth = 8; 431 sc->sc_sunfb.sf_linebytes = 1 << (bus_space_read_4(sc->sc_mem_t, 432 sc->sc_reg_h, IFB_REG_CONFIG) >> 16); 433 sc->sc_sunfb.sf_fbsize = 434 sc->sc_sunfb.sf_height * sc->sc_sunfb.sf_linebytes; 435 436 printf(", %dx%d\n", sc->sc_sunfb.sf_width, sc->sc_sunfb.sf_height); 437 438 ri = &sc->sc_sunfb.sf_ro; 439 ri->ri_bits = NULL; 440 ri->ri_hw = sc; 441 442 fbwscons_init(&sc->sc_sunfb, RI_BSWAP, console); 443 444 /* 445 * Find out what flavour of ifb we are... 446 */ 447 448 sc->sc_acceltype = ifb_accel_identify(name); 449 450 switch (sc->sc_acceltype) { 451 case IFB_ACCEL_IFB: 452 sc->sc_rop = ifb_rop_ifb; 453 break; 454 case IFB_ACCEL_JFB: 455 /* 456 * Remember the address of the communication area 457 */ 458 if (OF_getprop(node, "dev-comm", &dev_comm, 459 sizeof dev_comm) != -1) { 460 sc->sc_comm = (volatile uint32_t *)(vaddr_t)dev_comm; 461 } 462 sc->sc_rop = ifb_rop_jfb; 463 break; 464 } 465 466 /* 467 * Clear the unwanted pixel planes: all if non console (thus 468 * white background), and all planes above 7bpp otherwise. 469 * This also allows to check whether the accelerated code works, 470 * or not. 471 */ 472 473 if (sc->sc_acceltype != IFB_ACCEL_NONE) { 474 ifb_rop(sc, 0, 0, 0, 0, sc->sc_sunfb.sf_width, 475 sc->sc_sunfb.sf_height, IFB_ROP_CLEAR, 476 console ? ~IFB_PIXELMASK : ~0); 477 if (ifb_rop_wait(sc) == 0) { 478 /* fall back to dumb software operation */ 479 sc->sc_acceltype = IFB_ACCEL_NONE; 480 } 481 } 482 483 if (sc->sc_acceltype == IFB_ACCEL_NONE) { 484 /* due to the way we will handle updates */ 485 ri->ri_flg &= ~RI_FULLCLEAR; 486 487 if (!console) { 488 bzero((void *)sc->sc_fb8bank0_vaddr, 489 sc->sc_sunfb.sf_fbsize); 490 bzero((void *)sc->sc_fb8bank1_vaddr, 491 sc->sc_sunfb.sf_fbsize); 492 } 493 } 494 495 /* pick centering delta */ 496 sc->sc_fb8bank0_vaddr += ri->ri_bits - ri->ri_origbits; 497 sc->sc_fb8bank1_vaddr += ri->ri_bits - ri->ri_origbits; 498 499 sc->sc_old_ops = ri->ri_ops; /* structure copy */ 500 501 if (sc->sc_acceltype != IFB_ACCEL_NONE) { 502 ri->ri_ops.copyrows = ifb_copyrows; 503 ri->ri_ops.copycols = ifb_copycols; 504 ri->ri_ops.eraserows = ifb_eraserows; 505 ri->ri_ops.erasecols = ifb_erasecols; 506 ri->ri_ops.putchar = ifb_putchar_dumb; 507 ri->ri_do_cursor = ifb_do_cursor; 508 } else { 509 ri->ri_ops.copyrows = ifb_copyrows_dumb; 510 ri->ri_ops.copycols = ifb_copycols_dumb; 511 ri->ri_ops.eraserows = ifb_eraserows_dumb; 512 ri->ri_ops.erasecols = ifb_erasecols_dumb; 513 ri->ri_ops.putchar = ifb_putchar_dumb; 514 ri->ri_do_cursor = ifb_do_cursor_dumb; 515 } 516 517 ifb_setcolormap(&sc->sc_sunfb, ifb_setcolor); 518 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 519 520 if (console) 521 fbwscons_console_init(&sc->sc_sunfb, -1); 522 fbwscons_attach(&sc->sc_sunfb, &ifb_accessops, console); 523 } 524 525 /* 526 * Attempt to identify what kind of ifb we are talking to, so as to setup 527 * proper acceleration information. 528 */ 529 int 530 ifb_accel_identify(const char *name) 531 { 532 if (strcmp(name, "SUNW,Expert3D") == 0 || 533 strcmp(name, "SUNW,Expert3D-Lite") == 0) 534 return IFB_ACCEL_IFB; /* ifblite */ 535 536 if (strcmp(name, "SUNW,XVR-1200") == 0) 537 return IFB_ACCEL_JFB; /* jfb */ 538 539 /* XVR-500 is bobcat, XVR-600 is xvr600 */ 540 541 return IFB_ACCEL_NONE; 542 } 543 544 int 545 ifb_ioctl(void *v, u_long cmd, caddr_t data, int flags, struct proc *p) 546 { 547 struct ifb_softc *sc = v; 548 struct wsdisplay_fbinfo *wdf; 549 struct pcisel *sel; 550 int mode; 551 552 switch (cmd) { 553 case WSDISPLAYIO_GTYPE: 554 *(u_int *)data = WSDISPLAY_TYPE_IFB; 555 break; 556 557 case WSDISPLAYIO_SMODE: 558 mode = *(u_int *)data; 559 if (mode == WSDISPLAYIO_MODE_EMUL) 560 ifb_setcolormap(&sc->sc_sunfb, ifb_setcolor); 561 sc->sc_mode = mode; 562 break; 563 case WSDISPLAYIO_GINFO: 564 wdf = (void *)data; 565 wdf->height = sc->sc_sunfb.sf_height; 566 wdf->width = sc->sc_sunfb.sf_width; 567 wdf->depth = sc->sc_sunfb.sf_depth; 568 wdf->cmsize = 256; 569 break; 570 case WSDISPLAYIO_LINEBYTES: 571 *(u_int *)data = sc->sc_sunfb.sf_linebytes; 572 break; 573 574 case WSDISPLAYIO_GETCMAP: 575 return ifb_getcmap(sc, (struct wsdisplay_cmap *)data); 576 case WSDISPLAYIO_PUTCMAP: 577 return ifb_putcmap(sc, (struct wsdisplay_cmap *)data); 578 579 case WSDISPLAYIO_GPCIID: 580 sel = (struct pcisel *)data; 581 sel->pc_bus = PCITAG_BUS(sc->sc_pcitag); 582 sel->pc_dev = PCITAG_DEV(sc->sc_pcitag); 583 sel->pc_func = PCITAG_FUN(sc->sc_pcitag); 584 break; 585 586 case WSDISPLAYIO_SVIDEO: 587 case WSDISPLAYIO_GVIDEO: 588 break; 589 590 case WSDISPLAYIO_GCURPOS: 591 case WSDISPLAYIO_SCURPOS: 592 case WSDISPLAYIO_GCURMAX: 593 case WSDISPLAYIO_GCURSOR: 594 case WSDISPLAYIO_SCURSOR: 595 default: 596 return -1; /* not supported yet */ 597 } 598 599 return 0; 600 } 601 602 static inline 603 u_int 604 ifb_dac_value(u_int r, u_int g, u_int b) 605 { 606 /* 607 * Convert 8 bit values to 10 bit scale, by shifting and inserting 608 * the former high bits in the low two bits. 609 * Simply shifting is sligthly too dull. 610 */ 611 r = (r << 2) | (r >> 6); 612 g = (g << 2) | (g >> 6); 613 b = (b << 2) | (b >> 6); 614 615 return (b << 20) | (g << 10) | r; 616 } 617 618 int 619 ifb_getcmap(struct ifb_softc *sc, struct wsdisplay_cmap *cm) 620 { 621 u_int index = cm->index; 622 u_int count = cm->count; 623 int error; 624 625 if (index >= 256 || count > 256 - index) 626 return EINVAL; 627 628 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 629 if (error) 630 return error; 631 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 632 if (error) 633 return error; 634 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 635 if (error) 636 return error; 637 return 0; 638 } 639 640 int 641 ifb_putcmap(struct ifb_softc *sc, struct wsdisplay_cmap *cm) 642 { 643 u_int index = cm->index; 644 u_int count = cm->count; 645 u_int i; 646 int error; 647 u_char *r, *g, *b; 648 649 if (index >= 256 || count > 256 - index) 650 return EINVAL; 651 652 if ((error = copyin(cm->red, &sc->sc_cmap_red[index], count)) != 0) 653 return error; 654 if ((error = copyin(cm->green, &sc->sc_cmap_green[index], count)) != 0) 655 return error; 656 if ((error = copyin(cm->blue, &sc->sc_cmap_blue[index], count)) != 0) 657 return error; 658 659 r = &sc->sc_cmap_red[index]; 660 g = &sc->sc_cmap_green[index]; 661 b = &sc->sc_cmap_blue[index]; 662 663 for (i = 0; i < count; i++) { 664 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 665 IFB_REG_CMAP_INDEX, index); 666 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, IFB_REG_CMAP_DATA, 667 ifb_dac_value(*r, *g, *b)); 668 r++, g++, b++, index++; 669 } 670 return 0; 671 } 672 673 void 674 ifb_setcolor(void *v, u_int index, u_int8_t r, u_int8_t g, u_int8_t b) 675 { 676 struct ifb_softc *sc = v; 677 678 sc->sc_cmap_red[index] = r; 679 sc->sc_cmap_green[index] = g; 680 sc->sc_cmap_blue[index] = b; 681 682 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, IFB_REG_CMAP_INDEX, 683 index); 684 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, IFB_REG_CMAP_DATA, 685 ifb_dac_value(r, g, b)); 686 } 687 688 /* similar in spirit to fbwscons_setcolormap() */ 689 void 690 ifb_setcolormap(struct sunfb *sf, 691 void (*setcolor)(void *, u_int, u_int8_t, u_int8_t, u_int8_t)) 692 { 693 struct rasops_info *ri = &sf->sf_ro; 694 int i; 695 const u_char *color; 696 697 /* 698 * Compensate for overlay plane limitations. Since we'll operate 699 * in 7bpp mode, our basic colors will use positions 00 to 0f, 700 * and the inverted colors will use positions 7f to 70. 701 */ 702 703 for (i = 0x00; i < 0x10; i++) { 704 color = &rasops_cmap[i * 3]; 705 setcolor(sf, i, color[0], color[1], color[2]); 706 } 707 for (i = 0x70; i < 0x80; i++) { 708 color = &rasops_cmap[(0xf0 | i) * 3]; 709 setcolor(sf, i, color[0], color[1], color[2]); 710 } 711 712 /* 713 * Proper operation apparently needs black to be 01, always. 714 * Replace black, red and white with white, black and red. 715 * Kind of ugly, but it works. 716 */ 717 ri->ri_devcmap[WSCOL_WHITE] = 0x00000000; 718 ri->ri_devcmap[WSCOL_BLACK] = 0x01010101; 719 ri->ri_devcmap[WSCOL_RED] = 0x07070707; 720 721 color = &rasops_cmap[(WSCOL_WHITE + 8) * 3]; /* real white */ 722 setcolor(sf, 0, color[0], color[1], color[2]); 723 setcolor(sf, IFB_PIXELMASK ^ 0, ~color[0], ~color[1], ~color[2]); 724 color = &rasops_cmap[WSCOL_BLACK * 3]; 725 setcolor(sf, 1, color[0], color[1], color[2]); 726 setcolor(sf, IFB_PIXELMASK ^ 1, ~color[0], ~color[1], ~color[2]); 727 color = &rasops_cmap[WSCOL_RED * 3]; 728 setcolor(sf, 7, color[0], color[1], color[2]); 729 setcolor(sf, IFB_PIXELMASK ^ 7, ~color[0], ~color[1], ~color[2]); 730 } 731 732 paddr_t 733 ifb_mmap(void *v, off_t off, int prot) 734 { 735 struct ifb_softc *sc = (struct ifb_softc *)v; 736 737 switch (sc->sc_mode) { 738 case WSDISPLAYIO_MODE_MAPPED: 739 /* 740 * In mapped mode, provide access to the two overlays, 741 * followed by the control registers, at the following 742 * addresses: 743 * 00000000 overlay 0, size up to 2MB (visible fb size) 744 * 01000000 overlay 1, size up to 2MB (visible fb size) 745 * 02000000 control registers 746 */ 747 off -= 0x00000000; 748 if (off >= 0 && off < round_page(sc->sc_sunfb.sf_fbsize)) { 749 return bus_space_mmap(sc->sc_mem_t, 750 sc->sc_fb8bank0_base, 751 off, prot, BUS_SPACE_MAP_LINEAR); 752 } 753 off -= 0x01000000; 754 if (off >= 0 && off < round_page(sc->sc_sunfb.sf_fbsize)) { 755 return bus_space_mmap(sc->sc_mem_t, 756 sc->sc_fb8bank1_base, 757 off, prot, BUS_SPACE_MAP_LINEAR); 758 } 759 #ifdef APERTURE 760 off -= 0x01000000; 761 if (allowaperture != 0 && sc->sc_acceltype != IFB_ACCEL_NONE) { 762 if (off >= 0 && off < round_page(sc->sc_reglen)) { 763 return bus_space_mmap(sc->sc_mem_t, 764 sc->sc_regbase, 765 off, prot, BUS_SPACE_MAP_LINEAR); 766 } 767 } 768 #endif 769 break; 770 } 771 772 return -1; 773 } 774 775 void 776 ifb_burner(void *v, u_int on, u_int flags) 777 { 778 struct ifb_softc *sc = (struct ifb_softc *)v; 779 int s; 780 uint32_t dpms; 781 782 s = splhigh(); 783 if (on) 784 dpms = IFB_REG_DPMS_ON; 785 else { 786 #ifdef notyet 787 if (flags & WSDISPLAY_BURN_VBLANK) 788 dpms = IFB_REG_DPMS_SUSPEND; 789 else 790 #endif 791 dpms = IFB_REG_DPMS_STANDBY; 792 } 793 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, IFB_REG_DPMS_STATE, dpms); 794 splx(s); 795 } 796 797 static inline int 798 ifb_is_console(int node) 799 { 800 extern int fbnode; 801 802 return fbnode == node; 803 } 804 805 int 806 ifb_mapregs(struct ifb_softc *sc, struct pci_attach_args *pa) 807 { 808 u_int32_t cf; 809 int bar, rc; 810 811 cf = pci_conf_read(pa->pa_pc, pa->pa_tag, IFB_PCI_CFG); 812 bar = PCI_MAPREG_START + IFB_PCI_CFG_BAR_OFFSET(cf); 813 814 cf = pci_conf_read(pa->pa_pc, pa->pa_tag, bar); 815 if (PCI_MAPREG_TYPE(cf) == PCI_MAPREG_TYPE_IO) 816 rc = EINVAL; 817 else { 818 rc = pci_mapreg_map(pa, bar, cf, 819 BUS_SPACE_MAP_LINEAR, NULL, &sc->sc_mem_h, 820 &sc->sc_membase, &sc->sc_memlen, 0); 821 } 822 if (rc != 0) { 823 printf("\n%s: can't map video memory\n", 824 sc->sc_sunfb.sf_dev.dv_xname); 825 return rc; 826 } 827 828 cf = pci_conf_read(pa->pa_pc, pa->pa_tag, bar + 4); 829 if (PCI_MAPREG_TYPE(cf) == PCI_MAPREG_TYPE_IO) 830 rc = EINVAL; 831 else { 832 rc = pci_mapreg_map(pa, bar + 4, cf, 833 0, NULL, &sc->sc_reg_h, 834 &sc->sc_regbase, &sc->sc_reglen, 0x9000); 835 } 836 if (rc != 0) { 837 printf("\n%s: can't map register space\n", 838 sc->sc_sunfb.sf_dev.dv_xname); 839 return rc; 840 } 841 842 return 0; 843 } 844 845 /* 846 * Non accelerated routines. 847 */ 848 849 int 850 ifb_putchar_dumb(void *cookie, int row, int col, u_int uc, long attr) 851 { 852 struct rasops_info *ri = cookie; 853 struct ifb_softc *sc = ri->ri_hw; 854 855 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 856 sc->sc_old_ops.putchar(cookie, row, col, uc, attr); 857 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 858 sc->sc_old_ops.putchar(cookie, row, col, uc, attr); 859 860 return 0; 861 } 862 863 int 864 ifb_copycols_dumb(void *cookie, int row, int src, int dst, int num) 865 { 866 struct rasops_info *ri = cookie; 867 struct ifb_softc *sc = ri->ri_hw; 868 869 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 870 sc->sc_old_ops.copycols(cookie, row, src, dst, num); 871 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 872 sc->sc_old_ops.copycols(cookie, row, src, dst, num); 873 874 return 0; 875 } 876 877 int 878 ifb_erasecols_dumb(void *cookie, int row, int col, int num, long attr) 879 { 880 struct rasops_info *ri = cookie; 881 struct ifb_softc *sc = ri->ri_hw; 882 883 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 884 sc->sc_old_ops.erasecols(cookie, row, col, num, attr); 885 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 886 sc->sc_old_ops.erasecols(cookie, row, col, num, attr); 887 888 return 0; 889 } 890 891 int 892 ifb_copyrows_dumb(void *cookie, int src, int dst, int num) 893 { 894 struct rasops_info *ri = cookie; 895 struct ifb_softc *sc = ri->ri_hw; 896 897 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 898 sc->sc_old_ops.copyrows(cookie, src, dst, num); 899 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 900 sc->sc_old_ops.copyrows(cookie, src, dst, num); 901 902 return 0; 903 } 904 905 int 906 ifb_eraserows_dumb(void *cookie, int row, int num, long attr) 907 { 908 struct rasops_info *ri = cookie; 909 struct ifb_softc *sc = ri->ri_hw; 910 911 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 912 sc->sc_old_ops.eraserows(cookie, row, num, attr); 913 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 914 sc->sc_old_ops.eraserows(cookie, row, num, attr); 915 916 return 0; 917 } 918 919 /* Similar to rasops_do_cursor(), but using a 7bit pixel mask. */ 920 921 #define CURSOR_MASK 0x7f7f7f7f 922 923 int 924 ifb_do_cursor_dumb(struct rasops_info *ri) 925 { 926 struct ifb_softc *sc = ri->ri_hw; 927 int full1, height, cnt, slop1, slop2, row, col; 928 int ovl_offset = sc->sc_fb8bank1_vaddr - sc->sc_fb8bank0_vaddr; 929 u_char *dp0, *dp1, *rp; 930 931 row = ri->ri_crow; 932 col = ri->ri_ccol; 933 934 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 935 rp = ri->ri_bits + row * ri->ri_yscale + col * ri->ri_xscale; 936 height = ri->ri_font->fontheight; 937 slop1 = (4 - ((long)rp & 3)) & 3; 938 939 if (slop1 > ri->ri_xscale) 940 slop1 = ri->ri_xscale; 941 942 slop2 = (ri->ri_xscale - slop1) & 3; 943 full1 = (ri->ri_xscale - slop1 - slop2) >> 2; 944 945 if ((slop1 | slop2) == 0) { 946 /* A common case */ 947 while (height--) { 948 dp0 = rp; 949 dp1 = dp0 + ovl_offset; 950 rp += ri->ri_stride; 951 952 for (cnt = full1; cnt; cnt--) { 953 *(int32_t *)dp0 ^= CURSOR_MASK; 954 *(int32_t *)dp1 ^= CURSOR_MASK; 955 dp0 += 4; 956 dp1 += 4; 957 } 958 } 959 } else { 960 /* XXX this is stupid.. use masks instead */ 961 while (height--) { 962 dp0 = rp; 963 dp1 = dp0 + ovl_offset; 964 rp += ri->ri_stride; 965 966 if (slop1 & 1) { 967 *dp0++ ^= (u_char)CURSOR_MASK; 968 *dp1++ ^= (u_char)CURSOR_MASK; 969 } 970 971 if (slop1 & 2) { 972 *(int16_t *)dp0 ^= (int16_t)CURSOR_MASK; 973 *(int16_t *)dp1 ^= (int16_t)CURSOR_MASK; 974 dp0 += 2; 975 dp1 += 2; 976 } 977 978 for (cnt = full1; cnt; cnt--) { 979 *(int32_t *)dp0 ^= CURSOR_MASK; 980 *(int32_t *)dp1 ^= CURSOR_MASK; 981 dp0 += 4; 982 dp1 += 4; 983 } 984 985 if (slop2 & 1) { 986 *dp0++ ^= (u_char)CURSOR_MASK; 987 *dp1++ ^= (u_char)CURSOR_MASK; 988 } 989 990 if (slop2 & 2) { 991 *(int16_t *)dp0 ^= (int16_t)CURSOR_MASK; 992 *(int16_t *)dp1 ^= (int16_t)CURSOR_MASK; 993 } 994 } 995 } 996 997 return 0; 998 } 999 1000 /* 1001 * Accelerated routines. 1002 */ 1003 1004 int 1005 ifb_copycols(void *cookie, int row, int src, int dst, int num) 1006 { 1007 struct rasops_info *ri = cookie; 1008 struct ifb_softc *sc = ri->ri_hw; 1009 1010 num *= ri->ri_font->fontwidth; 1011 src *= ri->ri_font->fontwidth; 1012 dst *= ri->ri_font->fontwidth; 1013 row *= ri->ri_font->fontheight; 1014 1015 ifb_copyrect(sc, ri->ri_xorigin + src, ri->ri_yorigin + row, 1016 ri->ri_xorigin + dst, ri->ri_yorigin + row, 1017 num, ri->ri_font->fontheight); 1018 1019 return 0; 1020 } 1021 1022 int 1023 ifb_erasecols(void *cookie, int row, int col, int num, long attr) 1024 { 1025 struct rasops_info *ri = cookie; 1026 struct ifb_softc *sc = ri->ri_hw; 1027 int bg, fg; 1028 1029 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 1030 1031 row *= ri->ri_font->fontheight; 1032 col *= ri->ri_font->fontwidth; 1033 num *= ri->ri_font->fontwidth; 1034 1035 ifb_fillrect(sc, ri->ri_xorigin + col, ri->ri_yorigin + row, 1036 num, ri->ri_font->fontheight, ri->ri_devcmap[bg]); 1037 1038 return 0; 1039 } 1040 1041 int 1042 ifb_copyrows(void *cookie, int src, int dst, int num) 1043 { 1044 struct rasops_info *ri = cookie; 1045 struct ifb_softc *sc = ri->ri_hw; 1046 1047 num *= ri->ri_font->fontheight; 1048 src *= ri->ri_font->fontheight; 1049 dst *= ri->ri_font->fontheight; 1050 1051 ifb_copyrect(sc, ri->ri_xorigin, ri->ri_yorigin + src, 1052 ri->ri_xorigin, ri->ri_yorigin + dst, ri->ri_emuwidth, num); 1053 1054 return 0; 1055 } 1056 1057 int 1058 ifb_eraserows(void *cookie, int row, int num, long attr) 1059 { 1060 struct rasops_info *ri = cookie; 1061 struct ifb_softc *sc = ri->ri_hw; 1062 int bg, fg; 1063 int x, y, w; 1064 1065 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 1066 1067 if ((num == ri->ri_rows) && ISSET(ri->ri_flg, RI_FULLCLEAR)) { 1068 num = ri->ri_height; 1069 x = y = 0; 1070 w = ri->ri_width; 1071 } else { 1072 num *= ri->ri_font->fontheight; 1073 x = ri->ri_xorigin; 1074 y = ri->ri_yorigin + row * ri->ri_font->fontheight; 1075 w = ri->ri_emuwidth; 1076 } 1077 ifb_fillrect(sc, x, y, w, num, ri->ri_devcmap[bg]); 1078 1079 return 0; 1080 } 1081 1082 void 1083 ifb_copyrect(struct ifb_softc *sc, int sx, int sy, int dx, int dy, int w, int h) 1084 { 1085 ifb_rop(sc, sx, sy, dx, dy, w, h, IFB_ROP_SRC, IFB_PIXELMASK); 1086 ifb_rop_wait(sc); 1087 } 1088 1089 void 1090 ifb_fillrect(struct ifb_softc *sc, int x, int y, int w, int h, int bg) 1091 { 1092 int32_t mask; 1093 1094 /* pixels to set... */ 1095 mask = IFB_PIXELMASK & bg; 1096 if (mask != 0) { 1097 ifb_rop(sc, x, y, x, y, w, h, IFB_ROP_SET, mask); 1098 ifb_rop_wait(sc); 1099 } 1100 1101 /* pixels to clear... */ 1102 mask = IFB_PIXELMASK & ~bg; 1103 if (mask != 0) { 1104 ifb_rop(sc, x, y, x, y, w, h, IFB_ROP_CLEAR, mask); 1105 ifb_rop_wait(sc); 1106 } 1107 } 1108 1109 /* 1110 * Perform a raster operation on both overlay planes. 1111 * Puzzled by all the magic numbers in there? So are we. Isn't a dire 1112 * lack of documentation wonderful? 1113 */ 1114 1115 static inline void 1116 ifb_rop(struct ifb_softc *sc, int sx, int sy, int dx, int dy, int w, int h, 1117 uint32_t rop, int32_t planemask) 1118 { 1119 (*sc->sc_rop)(sc, sx, sy, dx, dy, w, h, rop, planemask); 1120 } 1121 1122 void 1123 ifb_rop_common(struct ifb_softc *sc, bus_addr_t reg, int sx, int sy, 1124 int dx, int dy, int w, int h, uint32_t rop, int32_t planemask) 1125 { 1126 int dir = 0; 1127 1128 /* 1129 * Compute rop direction. This only really matters for 1130 * screen-to-screen copies. 1131 */ 1132 if (sy < dy /* && sy + h > dy */) { 1133 sy += h - 1; 1134 dy += h; 1135 dir |= IFB_BLT_DIR_BACKWARDS_Y; 1136 } 1137 if (sx < dx /* && sx + w > dx */) { 1138 sx += w - 1; 1139 dx += w; 1140 dir |= IFB_BLT_DIR_BACKWARDS_X; 1141 } 1142 1143 /* Which one of those below is your magic number for today? */ 1144 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x61000001); 1145 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0); 1146 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x6301c080); 1147 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x80000000); 1148 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, rop); 1149 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, planemask); 1150 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0); 1151 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x64000303); 1152 /* 1153 * This value is a pixel offset within the destination area. It is 1154 * probably used to define complex polygon shapes, with the 1155 * last pixel in the list being back to (0,0). 1156 */ 1157 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(0, 0)); 1158 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0); 1159 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x00030000); 1160 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x2200010d); 1161 1162 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x33f01000 | dir); 1163 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(dx, dy)); 1164 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(w, h)); 1165 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(sx, sy)); 1166 } 1167 1168 void 1169 ifb_rop_ifb(void *v, int sx, int sy, int dx, int dy, int w, int h, 1170 uint32_t rop, int32_t planemask) 1171 { 1172 struct ifb_softc *sc = (struct ifb_softc *)v; 1173 bus_addr_t reg = IFB_REG_ENGINE; 1174 1175 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 2); 1176 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 1); 1177 /* the ``0101'' part is probably a component selection */ 1178 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x540101ff); 1179 1180 ifb_rop_common(sc, reg, sx, sy, dx, dy, w, h, rop, planemask); 1181 } 1182 1183 void 1184 ifb_rop_jfb(void *v, int sx, int sy, int dx, int dy, int w, int h, 1185 uint32_t rop, int32_t planemask) 1186 { 1187 struct ifb_softc *sc = (struct ifb_softc *)v; 1188 bus_addr_t reg = JFB_REG_ENGINE; 1189 uint32_t spr, splr; 1190 1191 /* 1192 * Pick the current spr and splr values from the communication 1193 * area if possible. 1194 */ 1195 if (sc->sc_comm != NULL) { 1196 spr = sc->sc_comm[IFB_SHARED_TERM8_SPR >> 2]; 1197 splr = sc->sc_comm[IFB_SHARED_TERM8_SPLR >> 2]; 1198 } else { 1199 /* supposedly sane defaults */ 1200 spr = 0x54ff0303; 1201 splr = 0x5c0000ff; 1202 } 1203 1204 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x00400016); 1205 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5b000002); 1206 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5a000000); 1207 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, spr); 1208 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, splr); 1209 1210 ifb_rop_common(sc, reg, sx, sy, dx, dy, w, h, rop, planemask); 1211 1212 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5a000001); 1213 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5b000001); 1214 } 1215 1216 int 1217 ifb_rop_wait(struct ifb_softc *sc) 1218 { 1219 int i; 1220 1221 for (i = 1000000; i != 0; i--) { 1222 if (bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 1223 IFB_REG_STATUS) & IFB_REG_STATUS_DONE) 1224 break; 1225 DELAY(1); 1226 } 1227 1228 return i; 1229 } 1230 1231 int 1232 ifb_do_cursor(struct rasops_info *ri) 1233 { 1234 struct ifb_softc *sc = ri->ri_hw; 1235 int y, x; 1236 1237 y = ri->ri_yorigin + ri->ri_crow * ri->ri_font->fontheight; 1238 x = ri->ri_xorigin + ri->ri_ccol * ri->ri_font->fontwidth; 1239 1240 ifb_rop(sc, x, y, x, y, ri->ri_font->fontwidth, ri->ri_font->fontheight, 1241 IFB_ROP_XOR, IFB_PIXELMASK); 1242 ifb_rop_wait(sc); 1243 1244 return 0; 1245 } 1246