1 /* $OpenBSD: ifb.c,v 1.7 2008/12/28 14:25:57 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2007, 2008 Miodrag Vallat. 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Least-effort driver for the Sun Expert3D cards (based on the 21 * ``Wildcat'' chips. 22 * 23 * There is no public documentation for these chips available. 24 * Since they are no longer supported by 3DLabs (which got bought by 25 * Creative), and Sun does not want to publish even minimal information 26 * or source code, the best we can do is experiment. 27 * 28 * Quoting Alan Coopersmith in 29 * http://mail.opensolaris.org/pipermail/opensolaris-discuss/2005-December/011885.html 30 * ``Unfortunately, the lawyers have asked we not give details about why 31 * specific components are not being released.'' 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/ioctl.h> 39 #include <sys/malloc.h> 40 #include <sys/pciio.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <machine/autoconf.h> 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 #include <machine/openfirm.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcidevs.h> 52 53 #include <dev/wscons/wsconsio.h> 54 #include <dev/wscons/wsdisplayvar.h> 55 56 #include <dev/rasops/rasops.h> 57 58 #include <machine/fbvar.h> 59 60 /* 61 * Parts of the following hardware knowledge come from David S. Miller's 62 * XVR-500 Linux driver (drivers/video/sunxvr500.c). 63 */ 64 65 /* 66 * The Expert3D and Expert3d-Lite cards are built around the Wildcat 67 * 5110, 6210 and 7210 chips. 68 * 69 * The card exposes the following resources: 70 * - a 32MB aperture window in which views to the different frame buffer 71 * areas can be mapped, in the first BAR. 72 * - a 64KB PROM and registers area, in the second BAR, with the registers 73 * starting 32KB within this area. 74 * - a 8MB memory mapping, which purpose is unknown, in the third BAR. 75 * 76 * In the state the PROM leaves us in, the 8MB frame buffer windows map 77 * the video memory as interleaved stripes: 78 * - frame buffer #0 will map horizontal pixels 00-1f, 60-9f, e0-11f, etc. 79 * - frame buffer #1 will map horizontal pixels 20-5f, a0-df, 120-15f, etc. 80 * However the non-visible parts of each stripe can still be addressed 81 * (probably for fast screen switching). 82 * 83 * Unfortunately, since we do not know how to reconfigure the stripes 84 * to provide at least a linear frame buffer, we have to write to both 85 * windows and have them provide the complete image. 86 * 87 * Moreover, high pixel values in the overlay planes (such as 0xff or 0xfe) 88 * seem to enable other planes with random contents, so we'll limit ourselves 89 * to 7bpp opration. 90 */ 91 92 /* 93 * The Expert3D has an extra BAR that is not present on the -Lite 94 * version. This register contains bits that tell us how many BARs to 95 * skip before we get to the BARs that interest us. 96 */ 97 #define IFB_PCI_CFG 0x5c 98 #define IFB_PCI_CFG_BAR_OFFSET(x) ((x & 0x000000e0) >> 3) 99 100 #define IFB_REG_OFFSET 0x8000 101 102 /* 103 * 0000 magic 104 * This register seems to be used to issue commands to the 105 * acceleration hardware. 106 * 107 */ 108 #define IFB_REG_MAGIC 0x0000 109 #define IFB_REG_MAGIC_DIR_FORWARDS 0x00 110 #define IFB_REG_MAGIC_DIR_BACKWARDS 0x0a 111 112 /* 113 * 0040 component configuration 114 * This register controls which parts of the board will be addressed by 115 * writes to other configuration registers. 116 * Apparently the low two bytes control the frame buffer windows for the 117 * given head (starting at 1). 118 * The high two bytes are texture related. 119 */ 120 #define IFB_REG_COMPONENT_SELECT 0x0040 121 122 /* 123 * 0044 status 124 * This register has a bit that signals completion of commands issued 125 * to the acceleration hardware. 126 */ 127 #define IFB_REG_STATUS 0x0044 128 #define IFB_REG_STATUS_DONE 0x00000004 129 130 /* 131 * 0058 magnifying configuration 132 * This register apparently controls magnifying. 133 * bits 5-6 select the window width divider (00: by 2, 01: by 4, 10: by 8, 134 * 11: by 16) 135 * bits 7-8 select the zoom factor (00: disabled, 01: x2, 10: x4, 11: x8) 136 */ 137 #define IFB_REG_MAGNIFY 0x0058 138 #define IFB_REG_MAGNIFY_DISABLE 0x00000000 139 #define IFB_REG_MAGNIFY_X2 0x00000040 140 #define IFB_REG_MAGNIFY_X4 0x00000080 141 #define IFB_REG_MAGNIFY_X8 0x000000c0 142 #define IFB_REG_MAGNIFY_WINDIV2 0x00000000 143 #define IFB_REG_MAGNIFY_WINDIV4 0x00000010 144 #define IFB_REG_MAGNIFY_WINDIV8 0x00000020 145 #define IFB_REG_MAGNIFY_WINDIV16 0x00000030 146 147 /* 148 * 0070 display resolution 149 * Contains the size of the display, as ((height - 1) << 16) | (width - 1) 150 */ 151 #define IFB_REG_RESOLUTION 0x0070 152 /* 153 * 0074 configuration register 154 * Contains 0x1a000088 | ((Log2 stride) << 16) 155 */ 156 #define IFB_REG_CONFIG 0x0074 157 /* 158 * 0078 32bit frame buffer window #0 (8 to 9 MB) 159 * Contains the offset (relative to BAR0) of the 32 bit frame buffer window. 160 */ 161 #define IFB_REG_FB32_0 0x0078 162 /* 163 * 007c 32bit frame buffer window #1 (8 to 9 MB) 164 * Contains the offset (relative to BAR0) of the 32 bit frame buffer window. 165 */ 166 #define IFB_REG_FB32_1 0x007c 167 /* 168 * 0080 8bit frame buffer window #0 (2 to 2.2 MB) 169 * Contains the offset (relative to BAR0) of the 8 bit frame buffer window. 170 */ 171 #define IFB_REG_FB8_0 0x0080 172 /* 173 * 0084 8bit frame buffer window #1 (2 to 2.2 MB) 174 * Contains the offset (relative to BAR0) of the 8 bit frame buffer window. 175 */ 176 #define IFB_REG_FB8_1 0x0084 177 /* 178 * 0088 unknown window (as large as a 32 bit frame buffer) 179 */ 180 #define IFB_REG_FB_UNK0 0x0088 181 /* 182 * 008c unknown window (as large as a 8 bit frame buffer) 183 */ 184 #define IFB_REG_FB_UNK1 0x008c 185 /* 186 * 0090 unknown window (as large as a 8 bit frame buffer) 187 */ 188 #define IFB_REG_FB_UNK2 0x0090 189 190 /* 191 * 00bc RAMDAC palette index register 192 */ 193 #define IFB_REG_CMAP_INDEX 0x00bc 194 /* 195 * 00c0 RAMDAC palette data register 196 */ 197 #define IFB_REG_CMAP_DATA 0x00c0 198 199 /* 200 * 00e4 DPMS state register 201 * States ``off'' and ``suspend'' need chip reprogramming before video can 202 * be enabled again. 203 */ 204 #define IFB_REG_DPMS_STATE 0x00e4 205 #define IFB_REG_DPMS_OFF 0x00000000 206 #define IFB_REG_DPMS_SUSPEND 0x00000001 207 #define IFB_REG_DPMS_STANDBY 0x00000002 208 #define IFB_REG_DPMS_ON 0x00000003 209 210 #define IFB_COORDS(x, y) ((x) | (y) << 16) 211 212 struct ifb_softc { 213 struct sunfb sc_sunfb; 214 int sc_nscreens; 215 216 bus_space_tag_t sc_mem_t; 217 pcitag_t sc_pcitag; 218 219 bus_space_handle_t sc_mem_h; 220 bus_addr_t sc_membase; 221 bus_size_t sc_memlen; 222 vaddr_t sc_memvaddr, sc_fb8bank0_vaddr, sc_fb8bank1_vaddr; 223 bus_space_handle_t sc_reg_h; 224 225 struct wsdisplay_emulops sc_old_ops; 226 void (*sc_old_cursor)(struct rasops_info *); 227 228 int sc_console; 229 u_int8_t sc_cmap_red[256]; 230 u_int8_t sc_cmap_green[256]; 231 u_int8_t sc_cmap_blue[256]; 232 }; 233 234 int ifb_ioctl(void *, u_long, caddr_t, int, struct proc *); 235 paddr_t ifb_mmap(void *, off_t, int); 236 void ifb_burner(void *, u_int, u_int); 237 238 struct wsdisplay_accessops ifb_accessops = { 239 ifb_ioctl, 240 ifb_mmap, 241 NULL, /* alloc_screen */ 242 NULL, /* free_screen */ 243 NULL, /* show_screen */ 244 NULL, /* load_font */ 245 NULL, /* scrollback */ 246 NULL, /* getchar */ 247 ifb_burner, 248 NULL /* pollc */ 249 }; 250 251 int ifbmatch(struct device *, void *, void *); 252 void ifbattach(struct device *, struct device *, void *); 253 254 struct cfattach ifb_ca = { 255 sizeof (struct ifb_softc), ifbmatch, ifbattach 256 }; 257 258 struct cfdriver ifb_cd = { 259 NULL, "ifb", DV_DULL 260 }; 261 262 int ifb_getcmap(struct ifb_softc *, struct wsdisplay_cmap *); 263 int ifb_is_console(int); 264 int ifb_mapregs(struct ifb_softc *, struct pci_attach_args *); 265 int ifb_putcmap(struct ifb_softc *, struct wsdisplay_cmap *); 266 void ifb_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t); 267 void ifb_setcolormap(struct sunfb *, 268 void (*)(void *, u_int, u_int8_t, u_int8_t, u_int8_t)); 269 270 void ifb_putchar(void *, int, int, u_int, long); 271 void ifb_copycols(void *, int, int, int, int); 272 void ifb_erasecols(void *, int, int, int, long); 273 void ifb_copyrows(void *, int, int, int); 274 void ifb_eraserows(void *, int, int, long); 275 void ifb_do_cursor(struct rasops_info *); 276 277 const struct pci_matchid ifb_devices[] = { 278 { PCI_VENDOR_INTERGRAPH, PCI_PRODUCT_INTERGRAPH_EXPERT3D }, 279 { PCI_VENDOR_3DLABS, PCI_PRODUCT_3DLABS_WILDCAT_6210 }, 280 { PCI_VENDOR_3DLABS, PCI_PRODUCT_3DLABS_WILDCAT_5110 },/* Sun XVR-500 */ 281 { PCI_VENDOR_3DLABS, PCI_PRODUCT_3DLABS_WILDCAT_7210 }, 282 }; 283 284 int 285 ifbmatch(struct device *parent, void *cf, void *aux) 286 { 287 struct pci_attach_args *paa = aux; 288 int node; 289 char *name; 290 291 if (pci_matchbyid(paa, ifb_devices, 292 sizeof(ifb_devices) / sizeof(ifb_devices[0])) != 0) 293 return 1; 294 295 node = PCITAG_NODE(paa->pa_tag); 296 name = getpropstring(node, "name"); 297 if (strcmp(name, "SUNW,Expert3D") == 0 || 298 strcmp(name, "SUNW,Expert3D-Lite") == 0) 299 return 1; 300 301 return 0; 302 } 303 304 void 305 ifbattach(struct device *parent, struct device *self, void *aux) 306 { 307 struct ifb_softc *sc = (struct ifb_softc *)self; 308 struct pci_attach_args *paa = aux; 309 struct rasops_info *ri; 310 int node; 311 312 sc->sc_mem_t = paa->pa_memt; 313 sc->sc_pcitag = paa->pa_tag; 314 315 printf("\n"); 316 317 if (ifb_mapregs(sc, paa)) 318 return; 319 320 sc->sc_memvaddr = (vaddr_t)bus_space_vaddr(sc->sc_mem_t, sc->sc_mem_h); 321 sc->sc_fb8bank0_vaddr = sc->sc_memvaddr + 322 bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 323 IFB_REG_OFFSET + IFB_REG_FB8_0) - sc->sc_membase; 324 sc->sc_fb8bank1_vaddr = sc->sc_memvaddr + 325 bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 326 IFB_REG_OFFSET + IFB_REG_FB8_1) - sc->sc_membase; 327 328 node = PCITAG_NODE(paa->pa_tag); 329 sc->sc_console = ifb_is_console(node); 330 331 fb_setsize(&sc->sc_sunfb, 8, 1152, 900, node, 0); 332 333 printf("%s: %dx%d\n", 334 self->dv_xname, sc->sc_sunfb.sf_width, sc->sc_sunfb.sf_height); 335 336 #if 0 337 /* 338 * Make sure the frame buffer is configured to sane values. 339 * So much more is needed there... documentation permitting. 340 */ 341 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 342 IFB_REG_OFFSET + IFB_REG_COMPONENT_SELECT, 0x00000101); 343 delay(1000); 344 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 345 IFB_REG_OFFSET + IFB_REG_MAGNIFY, IFB_REG_MAGNIFY_DISABLE); 346 #endif 347 348 ri = &sc->sc_sunfb.sf_ro; 349 ri->ri_bits = NULL; 350 ri->ri_hw = sc; 351 352 fbwscons_init(&sc->sc_sunfb, RI_BSWAP, sc->sc_console); 353 ri->ri_flg &= ~RI_FULLCLEAR; /* due to the way we handle updates */ 354 355 if (!sc->sc_console) { 356 bzero((void *)sc->sc_fb8bank0_vaddr, sc->sc_sunfb.sf_fbsize); 357 bzero((void *)sc->sc_fb8bank1_vaddr, sc->sc_sunfb.sf_fbsize); 358 } 359 360 /* pick centering delta */ 361 sc->sc_fb8bank0_vaddr += ri->ri_bits - ri->ri_origbits; 362 sc->sc_fb8bank1_vaddr += ri->ri_bits - ri->ri_origbits; 363 364 sc->sc_old_ops = ri->ri_ops; /* structure copy */ 365 sc->sc_old_cursor = ri->ri_do_cursor; 366 ri->ri_ops.copyrows = ifb_copyrows; 367 ri->ri_ops.copycols = ifb_copycols; 368 ri->ri_ops.eraserows = ifb_eraserows; 369 ri->ri_ops.erasecols = ifb_erasecols; 370 ri->ri_ops.putchar = ifb_putchar; 371 ri->ri_do_cursor = ifb_do_cursor; 372 373 ifb_setcolormap(&sc->sc_sunfb, ifb_setcolor); 374 375 if (sc->sc_console) 376 fbwscons_console_init(&sc->sc_sunfb, -1); 377 fbwscons_attach(&sc->sc_sunfb, &ifb_accessops, sc->sc_console); 378 } 379 380 int 381 ifb_ioctl(void *v, u_long cmd, caddr_t data, int flags, struct proc *p) 382 { 383 struct ifb_softc *sc = v; 384 struct wsdisplay_fbinfo *wdf; 385 struct pcisel *sel; 386 387 switch (cmd) { 388 case WSDISPLAYIO_GTYPE: 389 *(u_int *)data = WSDISPLAY_TYPE_UNKNOWN; 390 break; 391 392 case WSDISPLAYIO_SMODE: 393 if (*(u_int *)data == WSDISPLAYIO_MODE_EMUL) 394 ifb_setcolormap(&sc->sc_sunfb, ifb_setcolor); 395 break; 396 case WSDISPLAYIO_GINFO: 397 wdf = (void *)data; 398 wdf->height = sc->sc_sunfb.sf_height; 399 wdf->width = sc->sc_sunfb.sf_width; 400 wdf->depth = sc->sc_sunfb.sf_depth; 401 wdf->cmsize = 256; 402 break; 403 case WSDISPLAYIO_LINEBYTES: 404 *(u_int *)data = sc->sc_sunfb.sf_linebytes; 405 break; 406 407 case WSDISPLAYIO_GETCMAP: 408 return ifb_getcmap(sc, (struct wsdisplay_cmap *)data); 409 case WSDISPLAYIO_PUTCMAP: 410 return ifb_putcmap(sc, (struct wsdisplay_cmap *)data); 411 412 case WSDISPLAYIO_GPCIID: 413 sel = (struct pcisel *)data; 414 sel->pc_bus = PCITAG_BUS(sc->sc_pcitag); 415 sel->pc_dev = PCITAG_DEV(sc->sc_pcitag); 416 sel->pc_func = PCITAG_FUN(sc->sc_pcitag); 417 break; 418 419 case WSDISPLAYIO_SVIDEO: 420 case WSDISPLAYIO_GVIDEO: 421 break; 422 423 case WSDISPLAYIO_GCURPOS: 424 case WSDISPLAYIO_SCURPOS: 425 case WSDISPLAYIO_GCURMAX: 426 case WSDISPLAYIO_GCURSOR: 427 case WSDISPLAYIO_SCURSOR: 428 default: 429 return -1; /* not supported yet */ 430 } 431 432 return 0; 433 } 434 435 int 436 ifb_getcmap(struct ifb_softc *sc, struct wsdisplay_cmap *cm) 437 { 438 u_int index = cm->index; 439 u_int count = cm->count; 440 int error; 441 442 if (index >= 256 || count > 256 - index) 443 return EINVAL; 444 445 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 446 if (error) 447 return error; 448 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 449 if (error) 450 return error; 451 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 452 if (error) 453 return error; 454 return 0; 455 } 456 457 int 458 ifb_putcmap(struct ifb_softc *sc, struct wsdisplay_cmap *cm) 459 { 460 u_int index = cm->index; 461 u_int count = cm->count; 462 u_int i; 463 int error; 464 u_char *r, *g, *b; 465 466 if (index >= 256 || count > 256 - index) 467 return EINVAL; 468 469 if ((error = copyin(cm->red, &sc->sc_cmap_red[index], count)) != 0) 470 return error; 471 if ((error = copyin(cm->green, &sc->sc_cmap_green[index], count)) != 0) 472 return error; 473 if ((error = copyin(cm->blue, &sc->sc_cmap_blue[index], count)) != 0) 474 return error; 475 476 r = &sc->sc_cmap_red[index]; 477 g = &sc->sc_cmap_green[index]; 478 b = &sc->sc_cmap_blue[index]; 479 480 for (i = 0; i < count; i++) { 481 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 482 IFB_REG_OFFSET + IFB_REG_CMAP_INDEX, index); 483 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 484 IFB_REG_OFFSET + IFB_REG_CMAP_DATA, 485 (((u_int)*b) << 22) | (((u_int)*g) << 12) | (((u_int)*r) << 2)); 486 r++, g++, b++, index++; 487 } 488 return 0; 489 } 490 491 void 492 ifb_setcolor(void *v, u_int index, u_int8_t r, u_int8_t g, u_int8_t b) 493 { 494 struct ifb_softc *sc = v; 495 496 sc->sc_cmap_red[index] = r; 497 sc->sc_cmap_green[index] = g; 498 sc->sc_cmap_blue[index] = b; 499 500 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 501 IFB_REG_OFFSET + IFB_REG_CMAP_INDEX, index); 502 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 503 IFB_REG_OFFSET + IFB_REG_CMAP_DATA, 504 (((u_int)b) << 22) | (((u_int)g) << 12) | (((u_int)r) << 2)); 505 } 506 507 /* similar in spirit to fbwscons_setcolormap() */ 508 void 509 ifb_setcolormap(struct sunfb *sf, 510 void (*setcolor)(void *, u_int, u_int8_t, u_int8_t, u_int8_t)) 511 { 512 struct rasops_info *ri = &sf->sf_ro; 513 int i; 514 const u_char *color; 515 516 /* 517 * Compensate for overlay plane limitations. Since we'll operate 518 * in 7bpp mode, our basic colors will use positions 00 to 0f, 519 * and the inverted colors will use positions 7f to 70. 520 */ 521 522 for (i = 0x00; i < 0x10; i++) { 523 color = &rasops_cmap[i * 3]; 524 setcolor(sf, i, color[0], color[1], color[2]); 525 } 526 for (i = 0x70; i < 0x80; i++) { 527 color = &rasops_cmap[(0xf0 | i) * 3]; 528 setcolor(sf, i, color[0], color[1], color[2]); 529 } 530 531 /* 532 * Proper operation apparently needs black to be 01, always. 533 * Replace black, red and white with white, black and red. 534 * Kind of ugly, but it works. 535 */ 536 ri->ri_devcmap[WSCOL_WHITE] = 0x00000000; 537 ri->ri_devcmap[WSCOL_BLACK] = 0x01010101; 538 ri->ri_devcmap[WSCOL_RED] = 0x07070707; 539 540 color = &rasops_cmap[(WSCOL_WHITE + 8) * 3]; /* real white */ 541 setcolor(sf, 0, color[0], color[1], color[2]); 542 setcolor(sf, 0x7f ^ 0, ~color[0], ~color[1], ~color[2]); 543 color = &rasops_cmap[WSCOL_BLACK * 3]; 544 setcolor(sf, 1, color[0], color[1], color[2]); 545 setcolor(sf, 0x7f ^ 1, ~color[0], ~color[1], ~color[2]); 546 color = &rasops_cmap[WSCOL_RED * 3]; 547 setcolor(sf, 7, color[0], color[1], color[2]); 548 setcolor(sf, 0x7f ^ 7, ~color[0], ~color[1], ~color[2]); 549 } 550 551 paddr_t 552 ifb_mmap(void *v, off_t off, int prot) 553 { 554 return -1; 555 } 556 557 void 558 ifb_burner(void *v, u_int on, u_int flags) 559 { 560 struct ifb_softc *sc = (struct ifb_softc *)v; 561 int s; 562 uint32_t dpms; 563 564 s = splhigh(); 565 if (on) 566 dpms = IFB_REG_DPMS_ON; 567 else { 568 #ifdef notyet 569 if (flags & WSDISPLAY_BURN_VBLANK) 570 dpms = IFB_REG_DPMS_SUSPEND; 571 else 572 #endif 573 dpms = IFB_REG_DPMS_STANDBY; 574 } 575 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 576 IFB_REG_OFFSET + IFB_REG_DPMS_STATE, dpms); 577 splx(s); 578 } 579 580 int 581 ifb_is_console(int node) 582 { 583 extern int fbnode; 584 585 return fbnode == node; 586 } 587 588 int 589 ifb_mapregs(struct ifb_softc *sc, struct pci_attach_args *pa) 590 { 591 u_int32_t cf; 592 int bar, rc; 593 594 cf = pci_conf_read(pa->pa_pc, pa->pa_tag, IFB_PCI_CFG); 595 bar = PCI_MAPREG_START + IFB_PCI_CFG_BAR_OFFSET(cf); 596 597 cf = pci_conf_read(pa->pa_pc, pa->pa_tag, bar); 598 if (PCI_MAPREG_TYPE(cf) == PCI_MAPREG_TYPE_IO) 599 rc = EINVAL; 600 else { 601 rc = pci_mapreg_map(pa, bar, cf, 602 BUS_SPACE_MAP_LINEAR, NULL, &sc->sc_mem_h, 603 &sc->sc_membase, &sc->sc_memlen, 0); 604 } 605 if (rc != 0) { 606 printf("%s: can't map video memory\n", 607 sc->sc_sunfb.sf_dev.dv_xname); 608 return rc; 609 } 610 611 cf = pci_conf_read(pa->pa_pc, pa->pa_tag, bar + 4); 612 if (PCI_MAPREG_TYPE(cf) == PCI_MAPREG_TYPE_IO) 613 rc = EINVAL; 614 else { 615 rc = pci_mapreg_map(pa, bar + 4, cf, 616 0, NULL, &sc->sc_reg_h, NULL, NULL, 0x9000); 617 } 618 if (rc != 0) { 619 printf("%s: can't map register space\n", 620 sc->sc_sunfb.sf_dev.dv_xname); 621 return rc; 622 } 623 624 return 0; 625 } 626 627 void 628 ifb_putchar(void *cookie, int row, int col, u_int uc, long attr) 629 { 630 struct rasops_info *ri = cookie; 631 struct ifb_softc *sc = ri->ri_hw; 632 633 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 634 sc->sc_old_ops.putchar(cookie, row, col, uc, attr); 635 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 636 sc->sc_old_ops.putchar(cookie, row, col, uc, attr); 637 } 638 639 void 640 ifb_copycols(void *cookie, int row, int src, int dst, int num) 641 { 642 struct rasops_info *ri = cookie; 643 struct ifb_softc *sc = ri->ri_hw; 644 645 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 646 sc->sc_old_ops.copycols(cookie, row, src, dst, num); 647 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 648 sc->sc_old_ops.copycols(cookie, row, src, dst, num); 649 } 650 651 void 652 ifb_erasecols(void *cookie, int row, int col, int num, long attr) 653 { 654 struct rasops_info *ri = cookie; 655 struct ifb_softc *sc = ri->ri_hw; 656 657 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 658 sc->sc_old_ops.erasecols(cookie, row, col, num, attr); 659 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 660 sc->sc_old_ops.erasecols(cookie, row, col, num, attr); 661 } 662 663 void 664 ifb_copyrows(void *cookie, int src, int dst, int num) 665 { 666 struct rasops_info *ri = cookie; 667 struct ifb_softc *sc = ri->ri_hw; 668 int i, dir; 669 670 num *= ri->ri_font->fontheight; 671 src *= ri->ri_font->fontheight; 672 dst *= ri->ri_font->fontheight; 673 674 if (src < dst) { 675 src += (num -1); 676 dst += num; 677 dir = IFB_REG_MAGIC_DIR_BACKWARDS; 678 } else 679 dir = IFB_REG_MAGIC_DIR_FORWARDS; 680 681 /* Lots of magic numbers. */ 682 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 683 IFB_REG_OFFSET + IFB_REG_MAGIC, 2); 684 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 685 IFB_REG_OFFSET + IFB_REG_MAGIC, 1); 686 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 687 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x540101ff); 688 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 689 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x61000001); 690 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 691 IFB_REG_OFFSET + IFB_REG_MAGIC, 0); 692 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 693 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x6301c080); 694 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 695 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x80000000); 696 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 697 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x00330000); 698 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 699 IFB_REG_OFFSET + IFB_REG_MAGIC, 0xff); 700 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 701 IFB_REG_OFFSET + IFB_REG_MAGIC, 0); 702 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 703 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x64000303); 704 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 705 IFB_REG_OFFSET + IFB_REG_MAGIC, 0); 706 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 707 IFB_REG_OFFSET + IFB_REG_MAGIC, 0); 708 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 709 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x00030000); 710 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 711 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x2200010d); 712 713 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 714 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x33f01000 | dir); 715 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 716 IFB_REG_OFFSET + IFB_REG_MAGIC, 717 IFB_COORDS(ri->ri_xorigin, ri->ri_yorigin + dst)); 718 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 719 IFB_REG_OFFSET + IFB_REG_MAGIC, 720 IFB_COORDS(ri->ri_emuwidth, num)); 721 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 722 IFB_REG_OFFSET + IFB_REG_MAGIC, 723 IFB_COORDS(ri->ri_xorigin, ri->ri_yorigin + src)); 724 725 for (i = 1000000; i > 0; i--) { 726 if (bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 727 IFB_REG_OFFSET + IFB_REG_STATUS) & IFB_REG_STATUS_DONE) 728 break; 729 DELAY(1); 730 } 731 } 732 733 void 734 ifb_eraserows(void *cookie, int row, int num, long attr) 735 { 736 struct rasops_info *ri = cookie; 737 struct ifb_softc *sc = ri->ri_hw; 738 739 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 740 sc->sc_old_ops.eraserows(cookie, row, num, attr); 741 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 742 sc->sc_old_ops.eraserows(cookie, row, num, attr); 743 } 744 745 /* 746 * Similar to rasops_do_cursor(), but using a 7bit pixel mask. 747 */ 748 void 749 ifb_do_cursor(struct rasops_info *ri) 750 { 751 struct ifb_softc *sc = ri->ri_hw; 752 int full1, height, cnt, slop1, slop2, row, col; 753 int ovl_offset = sc->sc_fb8bank1_vaddr - sc->sc_fb8bank0_vaddr; 754 u_char *dp0, *dp1, *rp; 755 756 row = ri->ri_crow; 757 col = ri->ri_ccol; 758 759 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 760 rp = ri->ri_bits + row * ri->ri_yscale + col * ri->ri_xscale; 761 height = ri->ri_font->fontheight; 762 slop1 = (4 - ((long)rp & 3)) & 3; 763 764 if (slop1 > ri->ri_xscale) 765 slop1 = ri->ri_xscale; 766 767 slop2 = (ri->ri_xscale - slop1) & 3; 768 full1 = (ri->ri_xscale - slop1 - slop2) >> 2; 769 770 if ((slop1 | slop2) == 0) { 771 /* A common case */ 772 while (height--) { 773 dp0 = rp; 774 dp1 = dp0 + ovl_offset; 775 rp += ri->ri_stride; 776 777 for (cnt = full1; cnt; cnt--) { 778 *(int32_t *)dp0 ^= 0x7f7f7f7f; 779 *(int32_t *)dp1 ^= 0x7f7f7f7f; 780 dp0 += 4; 781 dp1 += 4; 782 } 783 } 784 } else { 785 /* XXX this is stupid.. use masks instead */ 786 while (height--) { 787 dp0 = rp; 788 dp1 = dp0 + ovl_offset; 789 rp += ri->ri_stride; 790 791 if (slop1 & 1) { 792 *dp0++ ^= 0x7f; 793 *dp1++ ^= 0x7f; 794 } 795 796 if (slop1 & 2) { 797 *(int16_t *)dp0 ^= 0x7f7f; 798 *(int16_t *)dp1 ^= 0x7f7f; 799 dp0 += 2; 800 dp1 += 2; 801 } 802 803 for (cnt = full1; cnt; cnt--) { 804 *(int32_t *)dp0 ^= 0x7f7f7f7f; 805 *(int32_t *)dp1 ^= 0x7f7f7f7f; 806 dp0 += 4; 807 dp1 += 4; 808 } 809 810 if (slop2 & 1) { 811 *dp0++ ^= 0x7f; 812 *dp1++ ^= 0x7f; 813 } 814 815 if (slop2 & 2) { 816 *(int16_t *)dp0 ^= 0x7f7f; 817 *(int16_t *)dp1 ^= 0x7f7f; 818 } 819 } 820 } 821 } 822