1 /* $OpenBSD: ifb.c,v 1.9 2008/12/29 21:54:52 miod Exp $ */ 2 3 /* 4 * Copyright (c) 2007, 2008 Miodrag Vallat. 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Least-effort driver for the Sun Expert3D cards (based on the 21 * ``Wildcat'' chips). 22 * 23 * There is no public documentation for these chips available. 24 * Since they are no longer supported by 3DLabs (which got bought by 25 * Creative), and Sun does not want to publish even minimal information 26 * or source code, the best we can do is experiment. 27 * 28 * Quoting Alan Coopersmith in 29 * http://mail.opensolaris.org/pipermail/opensolaris-discuss/2005-December/011885.html 30 * ``Unfortunately, the lawyers have asked we not give details about why 31 * specific components are not being released.'' 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/ioctl.h> 39 #include <sys/malloc.h> 40 #include <sys/pciio.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <machine/autoconf.h> 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 #include <machine/openfirm.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcidevs.h> 52 53 #include <dev/wscons/wsconsio.h> 54 #include <dev/wscons/wsdisplayvar.h> 55 56 #include <dev/rasops/rasops.h> 57 58 #include <machine/fbvar.h> 59 60 /* 61 * Parts of the following hardware knowledge come from David S. Miller's 62 * XVR-500 Linux driver (drivers/video/sunxvr500.c). 63 */ 64 65 /* 66 * The Expert3D and Expert3d-Lite cards are built around the Wildcat 67 * 5110, 6210 and 7210 chips. 68 * 69 * The card exposes the following resources: 70 * - a 32MB aperture window in which views to the different frame buffer 71 * areas can be mapped, in the first BAR. 72 * - a 64KB PROM and registers area, in the second BAR, with the registers 73 * starting 32KB within this area. 74 * - a 8MB memory mapping, which purpose is unknown, in the third BAR. 75 * 76 * In the state the PROM leaves us in, the 8MB frame buffer windows map 77 * the video memory as interleaved stripes, of which the non-visible parts 78 * can still be addressed (probably for fast screen switching). 79 * 80 * Unfortunately, since we do not know how to reconfigure the stripes 81 * to provide at least a linear frame buffer, we have to write to both 82 * windows and have them provide the complete image. 83 * 84 * Moreover, high pixel values in the overlay planes (such as 0xff or 0xfe) 85 * seem to enable other planes with random contents, so we'll limit ourselves 86 * to 7bpp opration. 87 */ 88 89 /* 90 * The Expert3D has an extra BAR that is not present on the -Lite 91 * version. This register contains bits that tell us how many BARs to 92 * skip before we get to the BARs that interest us. 93 */ 94 #define IFB_PCI_CFG 0x5c 95 #define IFB_PCI_CFG_BAR_OFFSET(x) ((x & 0x000000e0) >> 3) 96 97 #define IFB_REG_OFFSET 0x8000 98 99 /* 100 * 0000 magic 101 * This register seems to be used to issue commands to the 102 * acceleration hardware. 103 * 104 */ 105 #define IFB_REG_MAGIC 0x0000 106 #define IFB_REG_MAGIC_DIR_BACKWARDS_Y (0x08 | 0x02) 107 #define IFB_REG_MAGIC_DIR_BACKWARDS_X (0x04 | 0x01) 108 109 /* 110 * 0040 component configuration 111 * This register controls which parts of the board will be addressed by 112 * writes to other configuration registers. 113 * Apparently the low two bytes control the frame buffer windows for the 114 * given head (starting at 1). 115 * The high two bytes are texture related. 116 */ 117 #define IFB_REG_COMPONENT_SELECT 0x0040 118 119 /* 120 * 0044 status 121 * This register has a bit that signals completion of commands issued 122 * to the acceleration hardware. 123 */ 124 #define IFB_REG_STATUS 0x0044 125 #define IFB_REG_STATUS_DONE 0x00000004 126 127 /* 128 * 0058 magnifying configuration 129 * This register apparently controls magnifying. 130 * bits 5-6 select the window width divider (00: by 2, 01: by 4, 10: by 8, 131 * 11: by 16) 132 * bits 7-8 select the zoom factor (00: disabled, 01: x2, 10: x4, 11: x8) 133 */ 134 #define IFB_REG_MAGNIFY 0x0058 135 #define IFB_REG_MAGNIFY_DISABLE 0x00000000 136 #define IFB_REG_MAGNIFY_X2 0x00000040 137 #define IFB_REG_MAGNIFY_X4 0x00000080 138 #define IFB_REG_MAGNIFY_X8 0x000000c0 139 #define IFB_REG_MAGNIFY_WINDIV2 0x00000000 140 #define IFB_REG_MAGNIFY_WINDIV4 0x00000010 141 #define IFB_REG_MAGNIFY_WINDIV8 0x00000020 142 #define IFB_REG_MAGNIFY_WINDIV16 0x00000030 143 144 /* 145 * 0070 display resolution 146 * Contains the size of the display, as ((height - 1) << 16) | (width - 1) 147 */ 148 #define IFB_REG_RESOLUTION 0x0070 149 /* 150 * 0074 configuration register 151 * Contains 0x1a000088 | ((Log2 stride) << 16) 152 */ 153 #define IFB_REG_CONFIG 0x0074 154 /* 155 * 0078 32bit frame buffer window #0 (8 to 9 MB) 156 * Contains the offset (relative to BAR0) of the 32 bit frame buffer window. 157 */ 158 #define IFB_REG_FB32_0 0x0078 159 /* 160 * 007c 32bit frame buffer window #1 (8 to 9 MB) 161 * Contains the offset (relative to BAR0) of the 32 bit frame buffer window. 162 */ 163 #define IFB_REG_FB32_1 0x007c 164 /* 165 * 0080 8bit frame buffer window #0 (2 to 2.2 MB) 166 * Contains the offset (relative to BAR0) of the 8 bit frame buffer window. 167 */ 168 #define IFB_REG_FB8_0 0x0080 169 /* 170 * 0084 8bit frame buffer window #1 (2 to 2.2 MB) 171 * Contains the offset (relative to BAR0) of the 8 bit frame buffer window. 172 */ 173 #define IFB_REG_FB8_1 0x0084 174 /* 175 * 0088 unknown window (as large as a 32 bit frame buffer) 176 */ 177 #define IFB_REG_FB_UNK0 0x0088 178 /* 179 * 008c unknown window (as large as a 8 bit frame buffer) 180 */ 181 #define IFB_REG_FB_UNK1 0x008c 182 /* 183 * 0090 unknown window (as large as a 8 bit frame buffer) 184 */ 185 #define IFB_REG_FB_UNK2 0x0090 186 187 /* 188 * 00bc RAMDAC palette index register 189 */ 190 #define IFB_REG_CMAP_INDEX 0x00bc 191 /* 192 * 00c0 RAMDAC palette data register 193 */ 194 #define IFB_REG_CMAP_DATA 0x00c0 195 196 /* 197 * 00e4 DPMS state register 198 * States ``off'' and ``suspend'' need chip reprogramming before video can 199 * be enabled again. 200 */ 201 #define IFB_REG_DPMS_STATE 0x00e4 202 #define IFB_REG_DPMS_OFF 0x00000000 203 #define IFB_REG_DPMS_SUSPEND 0x00000001 204 #define IFB_REG_DPMS_STANDBY 0x00000002 205 #define IFB_REG_DPMS_ON 0x00000003 206 207 #define IFB_COORDS(x, y) ((x) | (y) << 16) 208 209 struct ifb_softc { 210 struct sunfb sc_sunfb; 211 int sc_nscreens; 212 213 bus_space_tag_t sc_mem_t; 214 pcitag_t sc_pcitag; 215 216 bus_space_handle_t sc_mem_h; 217 bus_addr_t sc_membase; 218 bus_size_t sc_memlen; 219 vaddr_t sc_memvaddr, sc_fb8bank0_vaddr, sc_fb8bank1_vaddr; 220 bus_space_handle_t sc_reg_h; 221 222 struct wsdisplay_emulops sc_old_ops; 223 void (*sc_old_cursor)(struct rasops_info *); 224 225 int sc_console; 226 u_int8_t sc_cmap_red[256]; 227 u_int8_t sc_cmap_green[256]; 228 u_int8_t sc_cmap_blue[256]; 229 }; 230 231 int ifb_ioctl(void *, u_long, caddr_t, int, struct proc *); 232 paddr_t ifb_mmap(void *, off_t, int); 233 void ifb_burner(void *, u_int, u_int); 234 235 struct wsdisplay_accessops ifb_accessops = { 236 ifb_ioctl, 237 ifb_mmap, 238 NULL, /* alloc_screen */ 239 NULL, /* free_screen */ 240 NULL, /* show_screen */ 241 NULL, /* load_font */ 242 NULL, /* scrollback */ 243 NULL, /* getchar */ 244 ifb_burner, 245 NULL /* pollc */ 246 }; 247 248 int ifbmatch(struct device *, void *, void *); 249 void ifbattach(struct device *, struct device *, void *); 250 251 struct cfattach ifb_ca = { 252 sizeof (struct ifb_softc), ifbmatch, ifbattach 253 }; 254 255 struct cfdriver ifb_cd = { 256 NULL, "ifb", DV_DULL 257 }; 258 259 int ifb_getcmap(struct ifb_softc *, struct wsdisplay_cmap *); 260 int ifb_is_console(int); 261 int ifb_mapregs(struct ifb_softc *, struct pci_attach_args *); 262 int ifb_putcmap(struct ifb_softc *, struct wsdisplay_cmap *); 263 void ifb_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t); 264 void ifb_setcolormap(struct sunfb *, 265 void (*)(void *, u_int, u_int8_t, u_int8_t, u_int8_t)); 266 267 void ifb_copyrect(struct ifb_softc *, int, int, int, int, int, int); 268 void ifb_putchar(void *, int, int, u_int, long); 269 void ifb_copycols(void *, int, int, int, int); 270 void ifb_erasecols(void *, int, int, int, long); 271 void ifb_copyrows(void *, int, int, int); 272 void ifb_eraserows(void *, int, int, long); 273 void ifb_do_cursor(struct rasops_info *); 274 275 const struct pci_matchid ifb_devices[] = { 276 { PCI_VENDOR_INTERGRAPH, PCI_PRODUCT_INTERGRAPH_EXPERT3D }, 277 { PCI_VENDOR_3DLABS, PCI_PRODUCT_3DLABS_WILDCAT_6210 }, 278 { PCI_VENDOR_3DLABS, PCI_PRODUCT_3DLABS_WILDCAT_5110 },/* Sun XVR-500 */ 279 { PCI_VENDOR_3DLABS, PCI_PRODUCT_3DLABS_WILDCAT_7210 }, 280 }; 281 282 int 283 ifbmatch(struct device *parent, void *cf, void *aux) 284 { 285 struct pci_attach_args *paa = aux; 286 int node; 287 char *name; 288 289 if (pci_matchbyid(paa, ifb_devices, 290 sizeof(ifb_devices) / sizeof(ifb_devices[0])) != 0) 291 return 1; 292 293 node = PCITAG_NODE(paa->pa_tag); 294 name = getpropstring(node, "name"); 295 if (strcmp(name, "SUNW,Expert3D") == 0 || 296 strcmp(name, "SUNW,Expert3D-Lite") == 0) 297 return 1; 298 299 return 0; 300 } 301 302 void 303 ifbattach(struct device *parent, struct device *self, void *aux) 304 { 305 struct ifb_softc *sc = (struct ifb_softc *)self; 306 struct pci_attach_args *paa = aux; 307 struct rasops_info *ri; 308 int node; 309 310 sc->sc_mem_t = paa->pa_memt; 311 sc->sc_pcitag = paa->pa_tag; 312 313 printf("\n"); 314 315 if (ifb_mapregs(sc, paa)) 316 return; 317 318 sc->sc_memvaddr = (vaddr_t)bus_space_vaddr(sc->sc_mem_t, sc->sc_mem_h); 319 sc->sc_fb8bank0_vaddr = sc->sc_memvaddr + 320 bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 321 IFB_REG_OFFSET + IFB_REG_FB8_0) - sc->sc_membase; 322 sc->sc_fb8bank1_vaddr = sc->sc_memvaddr + 323 bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 324 IFB_REG_OFFSET + IFB_REG_FB8_1) - sc->sc_membase; 325 326 node = PCITAG_NODE(paa->pa_tag); 327 sc->sc_console = ifb_is_console(node); 328 329 fb_setsize(&sc->sc_sunfb, 8, 1152, 900, node, 0); 330 331 printf("%s: %dx%d\n", 332 self->dv_xname, sc->sc_sunfb.sf_width, sc->sc_sunfb.sf_height); 333 334 #if 0 335 /* 336 * Make sure the frame buffer is configured to sane values. 337 * So much more is needed there... documentation permitting. 338 */ 339 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 340 IFB_REG_OFFSET + IFB_REG_COMPONENT_SELECT, 0x00000101); 341 delay(1000); 342 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 343 IFB_REG_OFFSET + IFB_REG_MAGNIFY, IFB_REG_MAGNIFY_DISABLE); 344 #endif 345 346 ri = &sc->sc_sunfb.sf_ro; 347 ri->ri_bits = NULL; 348 ri->ri_hw = sc; 349 350 fbwscons_init(&sc->sc_sunfb, RI_BSWAP, sc->sc_console); 351 ri->ri_flg &= ~RI_FULLCLEAR; /* due to the way we handle updates */ 352 353 if (!sc->sc_console) { 354 bzero((void *)sc->sc_fb8bank0_vaddr, sc->sc_sunfb.sf_fbsize); 355 bzero((void *)sc->sc_fb8bank1_vaddr, sc->sc_sunfb.sf_fbsize); 356 } 357 358 /* pick centering delta */ 359 sc->sc_fb8bank0_vaddr += ri->ri_bits - ri->ri_origbits; 360 sc->sc_fb8bank1_vaddr += ri->ri_bits - ri->ri_origbits; 361 362 sc->sc_old_ops = ri->ri_ops; /* structure copy */ 363 sc->sc_old_cursor = ri->ri_do_cursor; 364 ri->ri_ops.copyrows = ifb_copyrows; 365 ri->ri_ops.copycols = ifb_copycols; 366 ri->ri_ops.eraserows = ifb_eraserows; 367 ri->ri_ops.erasecols = ifb_erasecols; 368 ri->ri_ops.putchar = ifb_putchar; 369 ri->ri_do_cursor = ifb_do_cursor; 370 371 ifb_setcolormap(&sc->sc_sunfb, ifb_setcolor); 372 373 if (sc->sc_console) 374 fbwscons_console_init(&sc->sc_sunfb, -1); 375 fbwscons_attach(&sc->sc_sunfb, &ifb_accessops, sc->sc_console); 376 } 377 378 int 379 ifb_ioctl(void *v, u_long cmd, caddr_t data, int flags, struct proc *p) 380 { 381 struct ifb_softc *sc = v; 382 struct wsdisplay_fbinfo *wdf; 383 struct pcisel *sel; 384 385 switch (cmd) { 386 case WSDISPLAYIO_GTYPE: 387 *(u_int *)data = WSDISPLAY_TYPE_UNKNOWN; 388 break; 389 390 case WSDISPLAYIO_SMODE: 391 if (*(u_int *)data == WSDISPLAYIO_MODE_EMUL) 392 ifb_setcolormap(&sc->sc_sunfb, ifb_setcolor); 393 break; 394 case WSDISPLAYIO_GINFO: 395 wdf = (void *)data; 396 wdf->height = sc->sc_sunfb.sf_height; 397 wdf->width = sc->sc_sunfb.sf_width; 398 wdf->depth = sc->sc_sunfb.sf_depth; 399 wdf->cmsize = 256; 400 break; 401 case WSDISPLAYIO_LINEBYTES: 402 *(u_int *)data = sc->sc_sunfb.sf_linebytes; 403 break; 404 405 case WSDISPLAYIO_GETCMAP: 406 return ifb_getcmap(sc, (struct wsdisplay_cmap *)data); 407 case WSDISPLAYIO_PUTCMAP: 408 return ifb_putcmap(sc, (struct wsdisplay_cmap *)data); 409 410 case WSDISPLAYIO_GPCIID: 411 sel = (struct pcisel *)data; 412 sel->pc_bus = PCITAG_BUS(sc->sc_pcitag); 413 sel->pc_dev = PCITAG_DEV(sc->sc_pcitag); 414 sel->pc_func = PCITAG_FUN(sc->sc_pcitag); 415 break; 416 417 case WSDISPLAYIO_SVIDEO: 418 case WSDISPLAYIO_GVIDEO: 419 break; 420 421 case WSDISPLAYIO_GCURPOS: 422 case WSDISPLAYIO_SCURPOS: 423 case WSDISPLAYIO_GCURMAX: 424 case WSDISPLAYIO_GCURSOR: 425 case WSDISPLAYIO_SCURSOR: 426 default: 427 return -1; /* not supported yet */ 428 } 429 430 return 0; 431 } 432 433 int 434 ifb_getcmap(struct ifb_softc *sc, struct wsdisplay_cmap *cm) 435 { 436 u_int index = cm->index; 437 u_int count = cm->count; 438 int error; 439 440 if (index >= 256 || count > 256 - index) 441 return EINVAL; 442 443 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 444 if (error) 445 return error; 446 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 447 if (error) 448 return error; 449 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 450 if (error) 451 return error; 452 return 0; 453 } 454 455 int 456 ifb_putcmap(struct ifb_softc *sc, struct wsdisplay_cmap *cm) 457 { 458 u_int index = cm->index; 459 u_int count = cm->count; 460 u_int i; 461 int error; 462 u_char *r, *g, *b; 463 464 if (index >= 256 || count > 256 - index) 465 return EINVAL; 466 467 if ((error = copyin(cm->red, &sc->sc_cmap_red[index], count)) != 0) 468 return error; 469 if ((error = copyin(cm->green, &sc->sc_cmap_green[index], count)) != 0) 470 return error; 471 if ((error = copyin(cm->blue, &sc->sc_cmap_blue[index], count)) != 0) 472 return error; 473 474 r = &sc->sc_cmap_red[index]; 475 g = &sc->sc_cmap_green[index]; 476 b = &sc->sc_cmap_blue[index]; 477 478 for (i = 0; i < count; i++) { 479 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 480 IFB_REG_OFFSET + IFB_REG_CMAP_INDEX, index); 481 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 482 IFB_REG_OFFSET + IFB_REG_CMAP_DATA, 483 (((u_int)*b) << 22) | (((u_int)*g) << 12) | (((u_int)*r) << 2)); 484 r++, g++, b++, index++; 485 } 486 return 0; 487 } 488 489 void 490 ifb_setcolor(void *v, u_int index, u_int8_t r, u_int8_t g, u_int8_t b) 491 { 492 struct ifb_softc *sc = v; 493 494 sc->sc_cmap_red[index] = r; 495 sc->sc_cmap_green[index] = g; 496 sc->sc_cmap_blue[index] = b; 497 498 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 499 IFB_REG_OFFSET + IFB_REG_CMAP_INDEX, index); 500 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 501 IFB_REG_OFFSET + IFB_REG_CMAP_DATA, 502 (((u_int)b) << 22) | (((u_int)g) << 12) | (((u_int)r) << 2)); 503 } 504 505 /* similar in spirit to fbwscons_setcolormap() */ 506 void 507 ifb_setcolormap(struct sunfb *sf, 508 void (*setcolor)(void *, u_int, u_int8_t, u_int8_t, u_int8_t)) 509 { 510 struct rasops_info *ri = &sf->sf_ro; 511 int i; 512 const u_char *color; 513 514 /* 515 * Compensate for overlay plane limitations. Since we'll operate 516 * in 7bpp mode, our basic colors will use positions 00 to 0f, 517 * and the inverted colors will use positions 7f to 70. 518 */ 519 520 for (i = 0x00; i < 0x10; i++) { 521 color = &rasops_cmap[i * 3]; 522 setcolor(sf, i, color[0], color[1], color[2]); 523 } 524 for (i = 0x70; i < 0x80; i++) { 525 color = &rasops_cmap[(0xf0 | i) * 3]; 526 setcolor(sf, i, color[0], color[1], color[2]); 527 } 528 529 /* 530 * Proper operation apparently needs black to be 01, always. 531 * Replace black, red and white with white, black and red. 532 * Kind of ugly, but it works. 533 */ 534 ri->ri_devcmap[WSCOL_WHITE] = 0x00000000; 535 ri->ri_devcmap[WSCOL_BLACK] = 0x01010101; 536 ri->ri_devcmap[WSCOL_RED] = 0x07070707; 537 538 color = &rasops_cmap[(WSCOL_WHITE + 8) * 3]; /* real white */ 539 setcolor(sf, 0, color[0], color[1], color[2]); 540 setcolor(sf, 0x7f ^ 0, ~color[0], ~color[1], ~color[2]); 541 color = &rasops_cmap[WSCOL_BLACK * 3]; 542 setcolor(sf, 1, color[0], color[1], color[2]); 543 setcolor(sf, 0x7f ^ 1, ~color[0], ~color[1], ~color[2]); 544 color = &rasops_cmap[WSCOL_RED * 3]; 545 setcolor(sf, 7, color[0], color[1], color[2]); 546 setcolor(sf, 0x7f ^ 7, ~color[0], ~color[1], ~color[2]); 547 } 548 549 paddr_t 550 ifb_mmap(void *v, off_t off, int prot) 551 { 552 return -1; 553 } 554 555 void 556 ifb_burner(void *v, u_int on, u_int flags) 557 { 558 struct ifb_softc *sc = (struct ifb_softc *)v; 559 int s; 560 uint32_t dpms; 561 562 s = splhigh(); 563 if (on) 564 dpms = IFB_REG_DPMS_ON; 565 else { 566 #ifdef notyet 567 if (flags & WSDISPLAY_BURN_VBLANK) 568 dpms = IFB_REG_DPMS_SUSPEND; 569 else 570 #endif 571 dpms = IFB_REG_DPMS_STANDBY; 572 } 573 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 574 IFB_REG_OFFSET + IFB_REG_DPMS_STATE, dpms); 575 splx(s); 576 } 577 578 int 579 ifb_is_console(int node) 580 { 581 extern int fbnode; 582 583 return fbnode == node; 584 } 585 586 int 587 ifb_mapregs(struct ifb_softc *sc, struct pci_attach_args *pa) 588 { 589 u_int32_t cf; 590 int bar, rc; 591 592 cf = pci_conf_read(pa->pa_pc, pa->pa_tag, IFB_PCI_CFG); 593 bar = PCI_MAPREG_START + IFB_PCI_CFG_BAR_OFFSET(cf); 594 595 cf = pci_conf_read(pa->pa_pc, pa->pa_tag, bar); 596 if (PCI_MAPREG_TYPE(cf) == PCI_MAPREG_TYPE_IO) 597 rc = EINVAL; 598 else { 599 rc = pci_mapreg_map(pa, bar, cf, 600 BUS_SPACE_MAP_LINEAR, NULL, &sc->sc_mem_h, 601 &sc->sc_membase, &sc->sc_memlen, 0); 602 } 603 if (rc != 0) { 604 printf("%s: can't map video memory\n", 605 sc->sc_sunfb.sf_dev.dv_xname); 606 return rc; 607 } 608 609 cf = pci_conf_read(pa->pa_pc, pa->pa_tag, bar + 4); 610 if (PCI_MAPREG_TYPE(cf) == PCI_MAPREG_TYPE_IO) 611 rc = EINVAL; 612 else { 613 rc = pci_mapreg_map(pa, bar + 4, cf, 614 0, NULL, &sc->sc_reg_h, NULL, NULL, 0x9000); 615 } 616 if (rc != 0) { 617 printf("%s: can't map register space\n", 618 sc->sc_sunfb.sf_dev.dv_xname); 619 return rc; 620 } 621 622 return 0; 623 } 624 625 void 626 ifb_putchar(void *cookie, int row, int col, u_int uc, long attr) 627 { 628 struct rasops_info *ri = cookie; 629 struct ifb_softc *sc = ri->ri_hw; 630 631 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 632 sc->sc_old_ops.putchar(cookie, row, col, uc, attr); 633 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 634 sc->sc_old_ops.putchar(cookie, row, col, uc, attr); 635 } 636 637 void 638 ifb_copycols(void *cookie, int row, int src, int dst, int num) 639 { 640 struct rasops_info *ri = cookie; 641 struct ifb_softc *sc = ri->ri_hw; 642 643 num *= ri->ri_font->fontwidth; 644 src *= ri->ri_font->fontwidth; 645 dst *= ri->ri_font->fontwidth; 646 row *= ri->ri_font->fontheight; 647 648 ifb_copyrect(sc, ri->ri_xorigin + src, ri->ri_yorigin + row, 649 ri->ri_xorigin + dst, ri->ri_yorigin + row, 650 num, ri->ri_font->fontheight); 651 } 652 653 void 654 ifb_erasecols(void *cookie, int row, int col, int num, long attr) 655 { 656 struct rasops_info *ri = cookie; 657 struct ifb_softc *sc = ri->ri_hw; 658 659 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 660 sc->sc_old_ops.erasecols(cookie, row, col, num, attr); 661 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 662 sc->sc_old_ops.erasecols(cookie, row, col, num, attr); 663 } 664 665 void 666 ifb_copyrows(void *cookie, int src, int dst, int num) 667 { 668 struct rasops_info *ri = cookie; 669 struct ifb_softc *sc = ri->ri_hw; 670 671 num *= ri->ri_font->fontheight; 672 src *= ri->ri_font->fontheight; 673 dst *= ri->ri_font->fontheight; 674 675 ifb_copyrect(sc, ri->ri_xorigin, ri->ri_yorigin + src, 676 ri->ri_xorigin, ri->ri_yorigin + dst, ri->ri_emuwidth, num); 677 } 678 679 void 680 ifb_eraserows(void *cookie, int row, int num, long attr) 681 { 682 struct rasops_info *ri = cookie; 683 struct ifb_softc *sc = ri->ri_hw; 684 int bg, fg, done, cnt; 685 686 /* 687 * Perform the first line with plain rasops code (adapted below)... 688 */ 689 690 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 691 692 memset((void *)(sc->sc_fb8bank0_vaddr + row * ri->ri_yscale), 693 ri->ri_devcmap[bg], ri->ri_emustride); 694 memset((void *)(sc->sc_fb8bank1_vaddr + row * ri->ri_yscale), 695 ri->ri_devcmap[bg], ri->ri_emustride); 696 697 /* 698 * ...then copy it over and over until the whole area is done. 699 */ 700 701 row *= ri->ri_font->fontheight; 702 num *= ri->ri_font->fontheight; 703 row += ri->ri_yorigin; 704 705 for (done = 1, num -= done; num != 0;) { 706 cnt = min(done, num); 707 708 ifb_copyrect(sc, ri->ri_xorigin, row, 709 ri->ri_xorigin, row + done, ri->ri_emuwidth, cnt); 710 711 done += cnt; 712 num -= cnt; 713 } 714 } 715 716 void 717 ifb_copyrect(struct ifb_softc *sc, int sx, int sy, int dx, int dy, int w, int h) 718 { 719 int i, dir = 0; 720 721 if (sy < dy /* && sy + h > dy */) { 722 sy += h - 1; 723 dy += h; 724 dir |= IFB_REG_MAGIC_DIR_BACKWARDS_Y; 725 } 726 if (sx < dx /* && sx + w > dx */) { 727 sx += w - 1; 728 dx += w; 729 dir |= IFB_REG_MAGIC_DIR_BACKWARDS_X; 730 } 731 732 /* Lots of magic numbers. */ 733 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 734 IFB_REG_OFFSET + IFB_REG_MAGIC, 2); 735 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 736 IFB_REG_OFFSET + IFB_REG_MAGIC, 1); 737 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 738 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x540101ff); 739 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 740 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x61000001); 741 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 742 IFB_REG_OFFSET + IFB_REG_MAGIC, 0); 743 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 744 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x6301c080); 745 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 746 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x80000000); 747 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 748 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x00330000); 749 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 750 IFB_REG_OFFSET + IFB_REG_MAGIC, 0xff); 751 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 752 IFB_REG_OFFSET + IFB_REG_MAGIC, 0); 753 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 754 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x64000303); 755 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 756 IFB_REG_OFFSET + IFB_REG_MAGIC, 0); 757 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 758 IFB_REG_OFFSET + IFB_REG_MAGIC, 0); 759 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 760 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x00030000); 761 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 762 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x2200010d); 763 764 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 765 IFB_REG_OFFSET + IFB_REG_MAGIC, 0x33f01000 | dir); 766 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 767 IFB_REG_OFFSET + IFB_REG_MAGIC, IFB_COORDS(dx, dy)); 768 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 769 IFB_REG_OFFSET + IFB_REG_MAGIC, IFB_COORDS(w, h)); 770 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 771 IFB_REG_OFFSET + IFB_REG_MAGIC, IFB_COORDS(sx, sy)); 772 773 for (i = 1000000; i > 0; i--) { 774 if (bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 775 IFB_REG_OFFSET + IFB_REG_STATUS) & IFB_REG_STATUS_DONE) 776 break; 777 DELAY(1); 778 } 779 } 780 781 /* 782 * Similar to rasops_do_cursor(), but using a 7bit pixel mask. 783 */ 784 785 #define CURSOR_MASK 0x7f7f7f7f 786 787 void 788 ifb_do_cursor(struct rasops_info *ri) 789 { 790 struct ifb_softc *sc = ri->ri_hw; 791 int full1, height, cnt, slop1, slop2, row, col; 792 int ovl_offset = sc->sc_fb8bank1_vaddr - sc->sc_fb8bank0_vaddr; 793 u_char *dp0, *dp1, *rp; 794 795 row = ri->ri_crow; 796 col = ri->ri_ccol; 797 798 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 799 rp = ri->ri_bits + row * ri->ri_yscale + col * ri->ri_xscale; 800 height = ri->ri_font->fontheight; 801 slop1 = (4 - ((long)rp & 3)) & 3; 802 803 if (slop1 > ri->ri_xscale) 804 slop1 = ri->ri_xscale; 805 806 slop2 = (ri->ri_xscale - slop1) & 3; 807 full1 = (ri->ri_xscale - slop1 - slop2) >> 2; 808 809 if ((slop1 | slop2) == 0) { 810 /* A common case */ 811 while (height--) { 812 dp0 = rp; 813 dp1 = dp0 + ovl_offset; 814 rp += ri->ri_stride; 815 816 for (cnt = full1; cnt; cnt--) { 817 *(int32_t *)dp0 ^= CURSOR_MASK; 818 *(int32_t *)dp1 ^= CURSOR_MASK; 819 dp0 += 4; 820 dp1 += 4; 821 } 822 } 823 } else { 824 /* XXX this is stupid.. use masks instead */ 825 while (height--) { 826 dp0 = rp; 827 dp1 = dp0 + ovl_offset; 828 rp += ri->ri_stride; 829 830 if (slop1 & 1) { 831 *dp0++ ^= (u_char)CURSOR_MASK; 832 *dp1++ ^= (u_char)CURSOR_MASK; 833 } 834 835 if (slop1 & 2) { 836 *(int16_t *)dp0 ^= (int16_t)CURSOR_MASK; 837 *(int16_t *)dp1 ^= (int16_t)CURSOR_MASK; 838 dp0 += 2; 839 dp1 += 2; 840 } 841 842 for (cnt = full1; cnt; cnt--) { 843 *(int32_t *)dp0 ^= CURSOR_MASK; 844 *(int32_t *)dp1 ^= CURSOR_MASK; 845 dp0 += 4; 846 dp1 += 4; 847 } 848 849 if (slop2 & 1) { 850 *dp0++ ^= (u_char)CURSOR_MASK; 851 *dp1++ ^= (u_char)CURSOR_MASK; 852 } 853 854 if (slop2 & 2) { 855 *(int16_t *)dp0 ^= (int16_t)CURSOR_MASK; 856 *(int16_t *)dp1 ^= (int16_t)CURSOR_MASK; 857 } 858 } 859 } 860 } 861