1 /* $OpenBSD: ifb.c,v 1.19 2010/07/20 20:47:17 miod Exp $ */ 2 3 /* 4 * Copyright (c) 2007, 2008, 2009 Miodrag Vallat. 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Least-effort driver for the Sun Expert3D cards (based on the 21 * ``Wildcat'' chips). 22 * 23 * There is no public documentation for these chips available. 24 * Since they are no longer supported by 3DLabs (which got bought by 25 * Creative), and Sun does not want to publish even minimal information 26 * or source code, the best we can do is experiment. 27 * 28 * Quoting Alan Coopersmith in 29 * http://mail.opensolaris.org/pipermail/opensolaris-discuss/2005-December/011885.html 30 * ``Unfortunately, the lawyers have asked we not give details about why 31 * specific components are not being released.'' 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/ioctl.h> 39 #include <sys/malloc.h> 40 #include <sys/pciio.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <machine/autoconf.h> 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 #include <machine/openfirm.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 52 #include <dev/wscons/wsconsio.h> 53 #include <dev/wscons/wsdisplayvar.h> 54 55 #include <dev/rasops/rasops.h> 56 57 #include <machine/fbvar.h> 58 59 #ifdef APERTURE 60 extern int allowaperture; 61 #endif 62 63 /* 64 * Parts of the following hardware knowledge come from David S. Miller's 65 * XVR-500 Linux driver (drivers/video/sunxvr500.c). 66 */ 67 68 /* 69 * The Expert3D and Expert3d-Lite cards are built around the Wildcat 70 * 5110, 6210 and 7210 chips. 71 * 72 * The card exposes the following resources: 73 * - a 32MB aperture window in which views to the different frame buffer 74 * areas can be mapped, in the first BAR. 75 * - a 64KB or 128KB PROM and registers area, in the second BAR. 76 * - a 8MB ``direct burst'' memory mapping, in the third BAR. 77 * 78 * The location of this BAR range is pointed to by a board-specific PCI 79 * configuration register. 80 * 81 * In the state the PROM leaves us in, the 8MB frame buffer windows map 82 * the video memory as interleaved stripes, of which the non-visible parts 83 * can still be addressed (probably for fast screen switching). 84 * 85 * Unfortunately, since we do not know how to reconfigure the stripes 86 * to provide at least a linear frame buffer, we have to write to both 87 * windows and have them provide the complete image. 88 * 89 * Moreover, high pixel values in the overlay planes (such as 0xff or 0xfe) 90 * seem to enable other planes with random contents, so we'll limit ourselves 91 * to 7bpp operation. 92 */ 93 94 /* 95 * The Fcode driver sets up a communication structure, allowing third-party 96 * code to reprogram the video mode while still allowing the Fcode routines 97 * to access the overlay planes. 98 * 99 * We'll use this information as well, although so far it's unlikely 100 * any code will do so, as long as the only documentation for this 101 * hardware amounts to zilch. 102 */ 103 104 /* probably some form of signature */ 105 #define IFB_SHARED_SIGNATURE 0x00 106 #define SIG_IFB 0x09209911 107 #define SIG_JFB 0x05140213 108 #define IFB_SHARED_MONITOR_MODE 0x10 109 #define IFB_SHARED_WIDTH 0x14 110 #define IFB_SHARED_HEIGHT 0x18 111 #define IFB_SHARED_V_FREQ 0x1c 112 #define IFB_SHARED_TIMING_H_FP 0x20 113 #define IFB_SHARED_TIMING_H_SYNC 0x24 114 #define IFB_SHARED_TIMING_H_BP 0x28 115 #define IFB_SHARED_TIMING_V_FP 0x2c 116 #define IFB_SHARED_TIMING_V_SYNC 0x30 117 #define IFB_SHARED_TIMING_V_BP 0x34 118 #define IFB_SHARED_TIMING_FLAGS 0x38 119 #define IFB_SHARED_CMAP_DIRTY 0x3c 120 #define IFB_SHARED_TERM8_GSR 0x4c 121 #define IFB_SHARED_TERM8_SPR 0x50 122 #define IFB_SHARED_TERM8_SPLR 0x54 123 124 /* 125 * The Expert3D has an extra BAR that is not present on the -Lite 126 * version. This register contains bits that tell us how many BARs to 127 * skip before we get to the BARs that interest us. 128 */ 129 #define IFB_PCI_CFG 0x5c 130 #define IFB_PCI_CFG_BAR_OFFSET(x) ((x & 0x000000e0) >> 3) 131 132 /* 133 * 6000 (jfb) / 8000 (ifb) engine command 134 * This register is used to issue (some) commands sequences to the 135 * acceleration hardware. 136 */ 137 #define JFB_REG_ENGINE 0x6000 138 #define IFB_REG_ENGINE 0x8000 139 140 /* 141 * 8040 component configuration 142 * This register controls which parts of the board will be addressed by 143 * writes to other configuration registers. 144 * Apparently the low two bytes control the frame buffer windows for the 145 * given head (starting at 1). 146 * The high two bytes are texture related. 147 */ 148 #define IFB_REG_COMPONENT_SELECT 0x8040 149 150 /* 151 * 8044 status 152 * This register has a bit that signals completion of commands issued 153 * to the acceleration hardware. 154 */ 155 #define IFB_REG_STATUS 0x8044 156 #define IFB_REG_STATUS_DONE 0x00000004 157 158 /* 159 * 8058 magnifying configuration 160 * This register apparently controls magnifying. 161 * bits 5-6 select the window width divider (00: by 2, 01: by 4, 10: by 8, 162 * 11: by 16) 163 * bits 7-8 select the zoom factor (00: disabled, 01: x2, 10: x4, 11: x8) 164 */ 165 #define IFB_REG_MAGNIFY 0x8058 166 #define IFB_REG_MAGNIFY_DISABLE 0x00000000 167 #define IFB_REG_MAGNIFY_X2 0x00000040 168 #define IFB_REG_MAGNIFY_X4 0x00000080 169 #define IFB_REG_MAGNIFY_X8 0x000000c0 170 #define IFB_REG_MAGNIFY_WINDIV2 0x00000000 171 #define IFB_REG_MAGNIFY_WINDIV4 0x00000010 172 #define IFB_REG_MAGNIFY_WINDIV8 0x00000020 173 #define IFB_REG_MAGNIFY_WINDIV16 0x00000030 174 175 /* 176 * 8070 display resolution 177 * Contains the size of the display, as ((height - 1) << 16) | (width - 1) 178 */ 179 #define IFB_REG_RESOLUTION 0x8070 180 /* 181 * 8074 configuration register 182 * Contains 0x1a000088 | ((Log2 stride) << 16) 183 */ 184 #define IFB_REG_CONFIG 0x8074 185 /* 186 * 8078 32bit frame buffer window #0 (8 to 9 MB) 187 * Contains the offset (relative to BAR0) of the 32 bit frame buffer window. 188 */ 189 #define IFB_REG_FB32_0 0x8078 190 /* 191 * 807c 32bit frame buffer window #1 (8 to 9 MB) 192 * Contains the offset (relative to BAR0) of the 32 bit frame buffer window. 193 */ 194 #define IFB_REG_FB32_1 0x807c 195 /* 196 * 8080 8bit frame buffer window #0 (2 to 2.2 MB) 197 * Contains the offset (relative to BAR0) of the 8 bit frame buffer window. 198 */ 199 #define IFB_REG_FB8_0 0x8080 200 /* 201 * 8084 8bit frame buffer window #1 (2 to 2.2 MB) 202 * Contains the offset (relative to BAR0) of the 8 bit frame buffer window. 203 */ 204 #define IFB_REG_FB8_1 0x8084 205 /* 206 * 8088 unknown window (as large as a 32 bit frame buffer) 207 */ 208 #define IFB_REG_FB_UNK0 0x8088 209 /* 210 * 808c unknown window (as large as a 8 bit frame buffer) 211 */ 212 #define IFB_REG_FB_UNK1 0x808c 213 /* 214 * 8090 unknown window (as large as a 8 bit frame buffer) 215 */ 216 #define IFB_REG_FB_UNK2 0x8090 217 218 /* 219 * 80bc RAMDAC palette index register 220 */ 221 #define IFB_REG_CMAP_INDEX 0x80bc 222 /* 223 * 80c0 RAMDAC palette data register 224 */ 225 #define IFB_REG_CMAP_DATA 0x80c0 226 227 /* 228 * 80e4 DPMS state register 229 * States ``off'' and ``suspend'' need chip reprogramming before video can 230 * be enabled again. 231 */ 232 #define IFB_REG_DPMS_STATE 0x80e4 233 #define IFB_REG_DPMS_OFF 0x00000000 234 #define IFB_REG_DPMS_SUSPEND 0x00000001 235 #define IFB_REG_DPMS_STANDBY 0x00000002 236 #define IFB_REG_DPMS_ON 0x00000003 237 238 /* 239 * (some) ROP codes 240 */ 241 242 #define IFB_ROP_CLEAR 0x00000000 /* clear bits in rop mask */ 243 #define IFB_ROP_SRC 0x00330000 /* copy src bits matching rop mask */ 244 #define IFB_ROP_XOR 0x00cc0000 /* xor src bits with rop mask */ 245 #define IFB_ROP_SET 0x00ff0000 /* set bits in rop mask */ 246 247 #define IFB_COORDS(x, y) ((x) | (y) << 16) 248 249 /* blitter directions */ 250 #define IFB_BLT_DIR_BACKWARDS_Y (0x08 | 0x02) 251 #define IFB_BLT_DIR_BACKWARDS_X (0x04 | 0x01) 252 253 #define IFB_PIXELMASK 0x7f /* 7bpp */ 254 255 struct ifb_softc { 256 struct sunfb sc_sunfb; 257 258 bus_space_tag_t sc_mem_t; 259 pcitag_t sc_pcitag; 260 261 /* overlays mappings */ 262 bus_space_handle_t sc_mem_h; 263 bus_addr_t sc_membase, sc_fb8bank0_base, sc_fb8bank1_base; 264 bus_size_t sc_memlen; 265 vaddr_t sc_memvaddr, sc_fb8bank0_vaddr, sc_fb8bank1_vaddr; 266 267 /* registers mapping */ 268 bus_space_handle_t sc_reg_h; 269 bus_addr_t sc_regbase; 270 bus_size_t sc_reglen; 271 272 /* communication area */ 273 volatile uint32_t *sc_comm; 274 275 /* acceleration information */ 276 u_int sc_acceltype; 277 #define IFB_ACCEL_NONE 0 278 #define IFB_ACCEL_IFB 1 /* Expert3D style */ 279 #define IFB_ACCEL_JFB 2 /* XVR-500 style */ 280 void (*sc_rop)(void *, int, int, int, int, int, int, uint32_t, int32_t); 281 282 /* wsdisplay related goo */ 283 u_int sc_mode; 284 struct wsdisplay_emulops sc_old_ops; 285 u_int8_t sc_cmap_red[256]; 286 u_int8_t sc_cmap_green[256]; 287 u_int8_t sc_cmap_blue[256]; 288 }; 289 290 int ifb_ioctl(void *, u_long, caddr_t, int, struct proc *); 291 paddr_t ifb_mmap(void *, off_t, int); 292 void ifb_burner(void *, u_int, u_int); 293 294 struct wsdisplay_accessops ifb_accessops = { 295 ifb_ioctl, 296 ifb_mmap, 297 NULL, /* alloc_screen */ 298 NULL, /* free_screen */ 299 NULL, /* show_screen */ 300 NULL, /* load_font */ 301 NULL, /* scrollback */ 302 NULL, /* getchar */ 303 ifb_burner, 304 NULL /* pollc */ 305 }; 306 307 int ifbmatch(struct device *, void *, void *); 308 void ifbattach(struct device *, struct device *, void *); 309 310 struct cfattach ifb_ca = { 311 sizeof (struct ifb_softc), ifbmatch, ifbattach 312 }; 313 314 struct cfdriver ifb_cd = { 315 NULL, "ifb", DV_DULL 316 }; 317 318 int ifb_accel_identify(const char *); 319 static inline 320 u_int ifb_dac_value(u_int, u_int, u_int); 321 int ifb_getcmap(struct ifb_softc *, struct wsdisplay_cmap *); 322 static inline 323 int ifb_is_console(int); 324 int ifb_mapregs(struct ifb_softc *, struct pci_attach_args *); 325 int ifb_putcmap(struct ifb_softc *, struct wsdisplay_cmap *); 326 void ifb_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t); 327 void ifb_setcolormap(struct sunfb *, 328 void (*)(void *, u_int, u_int8_t, u_int8_t, u_int8_t)); 329 330 void ifb_copyrect(struct ifb_softc *, int, int, int, int, int, int); 331 void ifb_fillrect(struct ifb_softc *, int, int, int, int, int); 332 static inline 333 void ifb_rop(struct ifb_softc *, int, int, int, int, int, int, uint32_t, 334 int32_t); 335 void ifb_rop_common(struct ifb_softc *, bus_addr_t, int, int, int, int, 336 int, int, uint32_t, int32_t); 337 void ifb_rop_ifb(void *, int, int, int, int, int, int, uint32_t, int32_t); 338 void ifb_rop_jfb(void *, int, int, int, int, int, int, uint32_t, int32_t); 339 int ifb_rop_wait(struct ifb_softc *); 340 341 int ifb_putchar_dumb(void *, int, int, u_int, long); 342 int ifb_copycols_dumb(void *, int, int, int, int); 343 int ifb_erasecols_dumb(void *, int, int, int, long); 344 int ifb_copyrows_dumb(void *, int, int, int); 345 int ifb_eraserows_dumb(void *, int, int, long); 346 int ifb_do_cursor_dumb(struct rasops_info *); 347 348 int ifb_putchar(void *, int, int, u_int, long); 349 int ifb_copycols(void *, int, int, int, int); 350 int ifb_erasecols(void *, int, int, int, long); 351 int ifb_copyrows(void *, int, int, int); 352 int ifb_eraserows(void *, int, int, long); 353 int ifb_do_cursor(struct rasops_info *); 354 355 int 356 ifbmatch(struct device *parent, void *cf, void *aux) 357 { 358 return ifb_ident(aux); 359 } 360 361 void 362 ifbattach(struct device *parent, struct device *self, void *aux) 363 { 364 struct ifb_softc *sc = (struct ifb_softc *)self; 365 struct pci_attach_args *paa = aux; 366 struct rasops_info *ri; 367 uint32_t dev_comm; 368 int node, console; 369 char *name, *text; 370 371 sc->sc_mem_t = paa->pa_memt; 372 sc->sc_pcitag = paa->pa_tag; 373 374 node = PCITAG_NODE(paa->pa_tag); 375 console = ifb_is_console(node); 376 377 printf("\n"); 378 379 /* 380 * Multiple heads appear as PCI subfunctions. 381 * However, the ofw node for it lacks most properties, 382 * and its BAR only give access to registers, not 383 * frame buffer memory. 384 */ 385 if (!node_has_property(node, "device_type")) { 386 printf("%s: secondary output not supported yet\n", 387 self->dv_xname); 388 return; 389 } 390 391 /* 392 * Describe the beast. 393 */ 394 395 name = text = getpropstring(node, "name"); 396 if (strncmp(text, "SUNW,", 5) == 0) 397 text += 5; 398 printf("%s: %s", self->dv_xname, text); 399 text = getpropstring(node, "model"); 400 if (*text != '\0') 401 printf(" (%s)", text); 402 403 if (ifb_mapregs(sc, paa)) 404 return; 405 406 sc->sc_fb8bank0_base = bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 407 IFB_REG_FB8_0); 408 sc->sc_fb8bank1_base = bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 409 IFB_REG_FB8_1); 410 411 sc->sc_memvaddr = (vaddr_t)bus_space_vaddr(sc->sc_mem_t, sc->sc_mem_h); 412 sc->sc_fb8bank0_vaddr = sc->sc_memvaddr + 413 sc->sc_fb8bank0_base - sc->sc_membase; 414 sc->sc_fb8bank1_vaddr = sc->sc_memvaddr + 415 sc->sc_fb8bank1_base - sc->sc_membase; 416 417 /* 418 * The values stored into the node properties might have been 419 * modified since the Fcode was last run. Pick the geometry 420 * information from the configuration registers instead. 421 * This replaces 422 fb_setsize(&sc->sc_sunfb, 8, 1152, 900, node, 0); 423 */ 424 425 sc->sc_sunfb.sf_width = (bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 426 IFB_REG_RESOLUTION) & 0xffff) + 1; 427 sc->sc_sunfb.sf_height = (bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 428 IFB_REG_RESOLUTION) >> 16) + 1; 429 sc->sc_sunfb.sf_depth = 8; 430 sc->sc_sunfb.sf_linebytes = 1 << (bus_space_read_4(sc->sc_mem_t, 431 sc->sc_reg_h, IFB_REG_CONFIG) >> 16); 432 sc->sc_sunfb.sf_fbsize = 433 sc->sc_sunfb.sf_height * sc->sc_sunfb.sf_linebytes; 434 435 printf(", %dx%d\n", sc->sc_sunfb.sf_width, sc->sc_sunfb.sf_height); 436 437 ri = &sc->sc_sunfb.sf_ro; 438 ri->ri_bits = NULL; 439 ri->ri_hw = sc; 440 441 fbwscons_init(&sc->sc_sunfb, RI_BSWAP, console); 442 443 /* 444 * Find out what flavour of ifb we are... 445 */ 446 447 sc->sc_acceltype = ifb_accel_identify(name); 448 449 switch (sc->sc_acceltype) { 450 case IFB_ACCEL_IFB: 451 sc->sc_rop = ifb_rop_ifb; 452 break; 453 case IFB_ACCEL_JFB: 454 /* 455 * Remember the address of the communication area 456 */ 457 if (OF_getprop(node, "dev-comm", &dev_comm, 458 sizeof dev_comm) != -1) { 459 sc->sc_comm = (volatile uint32_t *)(vaddr_t)dev_comm; 460 } 461 sc->sc_rop = ifb_rop_jfb; 462 break; 463 } 464 465 /* 466 * Clear the unwanted pixel planes: all if non console (thus 467 * white background), and all planes above 7bpp otherwise. 468 * This also allows to check whether the accelerated code works, 469 * or not. 470 */ 471 472 if (sc->sc_acceltype != IFB_ACCEL_NONE) { 473 ifb_rop(sc, 0, 0, 0, 0, sc->sc_sunfb.sf_width, 474 sc->sc_sunfb.sf_height, IFB_ROP_CLEAR, 475 console ? ~IFB_PIXELMASK : ~0); 476 if (ifb_rop_wait(sc) == 0) { 477 /* fall back to dumb software operation */ 478 sc->sc_acceltype = IFB_ACCEL_NONE; 479 } 480 } 481 482 if (sc->sc_acceltype == IFB_ACCEL_NONE) { 483 /* due to the way we will handle updates */ 484 ri->ri_flg &= ~RI_FULLCLEAR; 485 486 if (!console) { 487 bzero((void *)sc->sc_fb8bank0_vaddr, 488 sc->sc_sunfb.sf_fbsize); 489 bzero((void *)sc->sc_fb8bank1_vaddr, 490 sc->sc_sunfb.sf_fbsize); 491 } 492 } 493 494 /* pick centering delta */ 495 sc->sc_fb8bank0_vaddr += ri->ri_bits - ri->ri_origbits; 496 sc->sc_fb8bank1_vaddr += ri->ri_bits - ri->ri_origbits; 497 498 sc->sc_old_ops = ri->ri_ops; /* structure copy */ 499 500 if (sc->sc_acceltype != IFB_ACCEL_NONE) { 501 ri->ri_ops.copyrows = ifb_copyrows; 502 ri->ri_ops.copycols = ifb_copycols; 503 ri->ri_ops.eraserows = ifb_eraserows; 504 ri->ri_ops.erasecols = ifb_erasecols; 505 ri->ri_ops.putchar = ifb_putchar_dumb; 506 ri->ri_do_cursor = ifb_do_cursor; 507 } else { 508 ri->ri_ops.copyrows = ifb_copyrows_dumb; 509 ri->ri_ops.copycols = ifb_copycols_dumb; 510 ri->ri_ops.eraserows = ifb_eraserows_dumb; 511 ri->ri_ops.erasecols = ifb_erasecols_dumb; 512 ri->ri_ops.putchar = ifb_putchar_dumb; 513 ri->ri_do_cursor = ifb_do_cursor_dumb; 514 } 515 516 ifb_setcolormap(&sc->sc_sunfb, ifb_setcolor); 517 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 518 519 if (console) 520 fbwscons_console_init(&sc->sc_sunfb, -1); 521 fbwscons_attach(&sc->sc_sunfb, &ifb_accessops, console); 522 } 523 524 /* 525 * Attempt to identify what kind of ifb we are talking to, so as to setup 526 * proper acceleration information. 527 */ 528 int 529 ifb_accel_identify(const char *name) 530 { 531 if (strcmp(name, "SUNW,Expert3D") == 0 || 532 strcmp(name, "SUNW,Expert3D-Lite") == 0) 533 return IFB_ACCEL_IFB; 534 535 if (strcmp(name, "SUNW,XVR-1200") == 0) 536 return IFB_ACCEL_JFB; 537 538 /* XVR-500 is bobcat, XVR-600 is xvr600 */ 539 540 return IFB_ACCEL_NONE; 541 } 542 543 int 544 ifb_ioctl(void *v, u_long cmd, caddr_t data, int flags, struct proc *p) 545 { 546 struct ifb_softc *sc = v; 547 struct wsdisplay_fbinfo *wdf; 548 struct pcisel *sel; 549 int mode; 550 551 switch (cmd) { 552 case WSDISPLAYIO_GTYPE: 553 *(u_int *)data = WSDISPLAY_TYPE_IFB; 554 break; 555 556 case WSDISPLAYIO_SMODE: 557 mode = *(u_int *)data; 558 if (mode == WSDISPLAYIO_MODE_EMUL) 559 ifb_setcolormap(&sc->sc_sunfb, ifb_setcolor); 560 sc->sc_mode = mode; 561 break; 562 case WSDISPLAYIO_GINFO: 563 wdf = (void *)data; 564 wdf->height = sc->sc_sunfb.sf_height; 565 wdf->width = sc->sc_sunfb.sf_width; 566 wdf->depth = sc->sc_sunfb.sf_depth; 567 wdf->cmsize = 256; 568 break; 569 case WSDISPLAYIO_LINEBYTES: 570 *(u_int *)data = sc->sc_sunfb.sf_linebytes; 571 break; 572 573 case WSDISPLAYIO_GETCMAP: 574 return ifb_getcmap(sc, (struct wsdisplay_cmap *)data); 575 case WSDISPLAYIO_PUTCMAP: 576 return ifb_putcmap(sc, (struct wsdisplay_cmap *)data); 577 578 case WSDISPLAYIO_GPCIID: 579 sel = (struct pcisel *)data; 580 sel->pc_bus = PCITAG_BUS(sc->sc_pcitag); 581 sel->pc_dev = PCITAG_DEV(sc->sc_pcitag); 582 sel->pc_func = PCITAG_FUN(sc->sc_pcitag); 583 break; 584 585 case WSDISPLAYIO_SVIDEO: 586 case WSDISPLAYIO_GVIDEO: 587 break; 588 589 case WSDISPLAYIO_GCURPOS: 590 case WSDISPLAYIO_SCURPOS: 591 case WSDISPLAYIO_GCURMAX: 592 case WSDISPLAYIO_GCURSOR: 593 case WSDISPLAYIO_SCURSOR: 594 default: 595 return -1; /* not supported yet */ 596 } 597 598 return 0; 599 } 600 601 static inline 602 u_int 603 ifb_dac_value(u_int r, u_int g, u_int b) 604 { 605 /* 606 * Convert 8 bit values to 10 bit scale, by shifting and inserting 607 * the former high bits in the low two bits. 608 * Simply shifting is sligthly too dull. 609 */ 610 r = (r << 2) | (r >> 6); 611 g = (g << 2) | (g >> 6); 612 b = (b << 2) | (b >> 6); 613 614 return (b << 20) | (g << 10) | r; 615 } 616 617 int 618 ifb_getcmap(struct ifb_softc *sc, struct wsdisplay_cmap *cm) 619 { 620 u_int index = cm->index; 621 u_int count = cm->count; 622 int error; 623 624 if (index >= 256 || count > 256 - index) 625 return EINVAL; 626 627 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 628 if (error) 629 return error; 630 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 631 if (error) 632 return error; 633 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 634 if (error) 635 return error; 636 return 0; 637 } 638 639 int 640 ifb_putcmap(struct ifb_softc *sc, struct wsdisplay_cmap *cm) 641 { 642 u_int index = cm->index; 643 u_int count = cm->count; 644 u_int i; 645 int error; 646 u_char *r, *g, *b; 647 648 if (index >= 256 || count > 256 - index) 649 return EINVAL; 650 651 if ((error = copyin(cm->red, &sc->sc_cmap_red[index], count)) != 0) 652 return error; 653 if ((error = copyin(cm->green, &sc->sc_cmap_green[index], count)) != 0) 654 return error; 655 if ((error = copyin(cm->blue, &sc->sc_cmap_blue[index], count)) != 0) 656 return error; 657 658 r = &sc->sc_cmap_red[index]; 659 g = &sc->sc_cmap_green[index]; 660 b = &sc->sc_cmap_blue[index]; 661 662 for (i = 0; i < count; i++) { 663 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 664 IFB_REG_CMAP_INDEX, index); 665 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, IFB_REG_CMAP_DATA, 666 ifb_dac_value(*r, *g, *b)); 667 r++, g++, b++, index++; 668 } 669 return 0; 670 } 671 672 void 673 ifb_setcolor(void *v, u_int index, u_int8_t r, u_int8_t g, u_int8_t b) 674 { 675 struct ifb_softc *sc = v; 676 677 sc->sc_cmap_red[index] = r; 678 sc->sc_cmap_green[index] = g; 679 sc->sc_cmap_blue[index] = b; 680 681 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, IFB_REG_CMAP_INDEX, 682 index); 683 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, IFB_REG_CMAP_DATA, 684 ifb_dac_value(r, g, b)); 685 } 686 687 /* similar in spirit to fbwscons_setcolormap() */ 688 void 689 ifb_setcolormap(struct sunfb *sf, 690 void (*setcolor)(void *, u_int, u_int8_t, u_int8_t, u_int8_t)) 691 { 692 struct rasops_info *ri = &sf->sf_ro; 693 int i; 694 const u_char *color; 695 696 /* 697 * Compensate for overlay plane limitations. Since we'll operate 698 * in 7bpp mode, our basic colors will use positions 00 to 0f, 699 * and the inverted colors will use positions 7f to 70. 700 */ 701 702 for (i = 0x00; i < 0x10; i++) { 703 color = &rasops_cmap[i * 3]; 704 setcolor(sf, i, color[0], color[1], color[2]); 705 } 706 for (i = 0x70; i < 0x80; i++) { 707 color = &rasops_cmap[(0xf0 | i) * 3]; 708 setcolor(sf, i, color[0], color[1], color[2]); 709 } 710 711 /* 712 * Proper operation apparently needs black to be 01, always. 713 * Replace black, red and white with white, black and red. 714 * Kind of ugly, but it works. 715 */ 716 ri->ri_devcmap[WSCOL_WHITE] = 0x00000000; 717 ri->ri_devcmap[WSCOL_BLACK] = 0x01010101; 718 ri->ri_devcmap[WSCOL_RED] = 0x07070707; 719 720 color = &rasops_cmap[(WSCOL_WHITE + 8) * 3]; /* real white */ 721 setcolor(sf, 0, color[0], color[1], color[2]); 722 setcolor(sf, IFB_PIXELMASK ^ 0, ~color[0], ~color[1], ~color[2]); 723 color = &rasops_cmap[WSCOL_BLACK * 3]; 724 setcolor(sf, 1, color[0], color[1], color[2]); 725 setcolor(sf, IFB_PIXELMASK ^ 1, ~color[0], ~color[1], ~color[2]); 726 color = &rasops_cmap[WSCOL_RED * 3]; 727 setcolor(sf, 7, color[0], color[1], color[2]); 728 setcolor(sf, IFB_PIXELMASK ^ 7, ~color[0], ~color[1], ~color[2]); 729 } 730 731 paddr_t 732 ifb_mmap(void *v, off_t off, int prot) 733 { 734 struct ifb_softc *sc = (struct ifb_softc *)v; 735 736 switch (sc->sc_mode) { 737 case WSDISPLAYIO_MODE_MAPPED: 738 /* 739 * In mapped mode, provide access to the two overlays, 740 * followed by the control registers, at the following 741 * addresses: 742 * 00000000 overlay 0, size up to 2MB (visible fb size) 743 * 01000000 overlay 1, size up to 2MB (visible fb size) 744 * 02000000 control registers 745 */ 746 off -= 0x00000000; 747 if (off >= 0 && off < round_page(sc->sc_sunfb.sf_fbsize)) { 748 return bus_space_mmap(sc->sc_mem_t, 749 sc->sc_fb8bank0_base, 750 off, prot, BUS_SPACE_MAP_LINEAR); 751 } 752 off -= 0x01000000; 753 if (off >= 0 && off < round_page(sc->sc_sunfb.sf_fbsize)) { 754 return bus_space_mmap(sc->sc_mem_t, 755 sc->sc_fb8bank1_base, 756 off, prot, BUS_SPACE_MAP_LINEAR); 757 } 758 #ifdef APERTURE 759 off -= 0x01000000; 760 if (allowaperture != 0 && sc->sc_acceltype != IFB_ACCEL_NONE) { 761 if (off >= 0 && off < round_page(sc->sc_reglen)) { 762 return bus_space_mmap(sc->sc_mem_t, 763 sc->sc_regbase, 764 off, prot, BUS_SPACE_MAP_LINEAR); 765 } 766 } 767 #endif 768 break; 769 } 770 771 return -1; 772 } 773 774 void 775 ifb_burner(void *v, u_int on, u_int flags) 776 { 777 struct ifb_softc *sc = (struct ifb_softc *)v; 778 int s; 779 uint32_t dpms; 780 781 s = splhigh(); 782 if (on) 783 dpms = IFB_REG_DPMS_ON; 784 else { 785 #ifdef notyet 786 if (flags & WSDISPLAY_BURN_VBLANK) 787 dpms = IFB_REG_DPMS_SUSPEND; 788 else 789 #endif 790 dpms = IFB_REG_DPMS_STANDBY; 791 } 792 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, IFB_REG_DPMS_STATE, dpms); 793 splx(s); 794 } 795 796 static inline int 797 ifb_is_console(int node) 798 { 799 extern int fbnode; 800 801 return fbnode == node; 802 } 803 804 int 805 ifb_mapregs(struct ifb_softc *sc, struct pci_attach_args *pa) 806 { 807 u_int32_t cf; 808 int bar, rc; 809 810 cf = pci_conf_read(pa->pa_pc, pa->pa_tag, IFB_PCI_CFG); 811 bar = PCI_MAPREG_START + IFB_PCI_CFG_BAR_OFFSET(cf); 812 813 cf = pci_conf_read(pa->pa_pc, pa->pa_tag, bar); 814 if (PCI_MAPREG_TYPE(cf) == PCI_MAPREG_TYPE_IO) 815 rc = EINVAL; 816 else { 817 rc = pci_mapreg_map(pa, bar, cf, 818 BUS_SPACE_MAP_LINEAR, NULL, &sc->sc_mem_h, 819 &sc->sc_membase, &sc->sc_memlen, 0); 820 } 821 if (rc != 0) { 822 printf("\n%s: can't map video memory\n", 823 sc->sc_sunfb.sf_dev.dv_xname); 824 return rc; 825 } 826 827 cf = pci_conf_read(pa->pa_pc, pa->pa_tag, bar + 4); 828 if (PCI_MAPREG_TYPE(cf) == PCI_MAPREG_TYPE_IO) 829 rc = EINVAL; 830 else { 831 rc = pci_mapreg_map(pa, bar + 4, cf, 832 0, NULL, &sc->sc_reg_h, 833 &sc->sc_regbase, &sc->sc_reglen, 0x9000); 834 } 835 if (rc != 0) { 836 printf("\n%s: can't map register space\n", 837 sc->sc_sunfb.sf_dev.dv_xname); 838 return rc; 839 } 840 841 return 0; 842 } 843 844 /* 845 * Non accelerated routines. 846 */ 847 848 int 849 ifb_putchar_dumb(void *cookie, int row, int col, u_int uc, long attr) 850 { 851 struct rasops_info *ri = cookie; 852 struct ifb_softc *sc = ri->ri_hw; 853 854 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 855 sc->sc_old_ops.putchar(cookie, row, col, uc, attr); 856 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 857 sc->sc_old_ops.putchar(cookie, row, col, uc, attr); 858 859 return 0; 860 } 861 862 int 863 ifb_copycols_dumb(void *cookie, int row, int src, int dst, int num) 864 { 865 struct rasops_info *ri = cookie; 866 struct ifb_softc *sc = ri->ri_hw; 867 868 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 869 sc->sc_old_ops.copycols(cookie, row, src, dst, num); 870 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 871 sc->sc_old_ops.copycols(cookie, row, src, dst, num); 872 873 return 0; 874 } 875 876 int 877 ifb_erasecols_dumb(void *cookie, int row, int col, int num, long attr) 878 { 879 struct rasops_info *ri = cookie; 880 struct ifb_softc *sc = ri->ri_hw; 881 882 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 883 sc->sc_old_ops.erasecols(cookie, row, col, num, attr); 884 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 885 sc->sc_old_ops.erasecols(cookie, row, col, num, attr); 886 887 return 0; 888 } 889 890 int 891 ifb_copyrows_dumb(void *cookie, int src, int dst, int num) 892 { 893 struct rasops_info *ri = cookie; 894 struct ifb_softc *sc = ri->ri_hw; 895 896 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 897 sc->sc_old_ops.copyrows(cookie, src, dst, num); 898 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 899 sc->sc_old_ops.copyrows(cookie, src, dst, num); 900 901 return 0; 902 } 903 904 int 905 ifb_eraserows_dumb(void *cookie, int row, int num, long attr) 906 { 907 struct rasops_info *ri = cookie; 908 struct ifb_softc *sc = ri->ri_hw; 909 910 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 911 sc->sc_old_ops.eraserows(cookie, row, num, attr); 912 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 913 sc->sc_old_ops.eraserows(cookie, row, num, attr); 914 915 return 0; 916 } 917 918 /* Similar to rasops_do_cursor(), but using a 7bit pixel mask. */ 919 920 #define CURSOR_MASK 0x7f7f7f7f 921 922 int 923 ifb_do_cursor_dumb(struct rasops_info *ri) 924 { 925 struct ifb_softc *sc = ri->ri_hw; 926 int full1, height, cnt, slop1, slop2, row, col; 927 int ovl_offset = sc->sc_fb8bank1_vaddr - sc->sc_fb8bank0_vaddr; 928 u_char *dp0, *dp1, *rp; 929 930 row = ri->ri_crow; 931 col = ri->ri_ccol; 932 933 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 934 rp = ri->ri_bits + row * ri->ri_yscale + col * ri->ri_xscale; 935 height = ri->ri_font->fontheight; 936 slop1 = (4 - ((long)rp & 3)) & 3; 937 938 if (slop1 > ri->ri_xscale) 939 slop1 = ri->ri_xscale; 940 941 slop2 = (ri->ri_xscale - slop1) & 3; 942 full1 = (ri->ri_xscale - slop1 - slop2) >> 2; 943 944 if ((slop1 | slop2) == 0) { 945 /* A common case */ 946 while (height--) { 947 dp0 = rp; 948 dp1 = dp0 + ovl_offset; 949 rp += ri->ri_stride; 950 951 for (cnt = full1; cnt; cnt--) { 952 *(int32_t *)dp0 ^= CURSOR_MASK; 953 *(int32_t *)dp1 ^= CURSOR_MASK; 954 dp0 += 4; 955 dp1 += 4; 956 } 957 } 958 } else { 959 /* XXX this is stupid.. use masks instead */ 960 while (height--) { 961 dp0 = rp; 962 dp1 = dp0 + ovl_offset; 963 rp += ri->ri_stride; 964 965 if (slop1 & 1) { 966 *dp0++ ^= (u_char)CURSOR_MASK; 967 *dp1++ ^= (u_char)CURSOR_MASK; 968 } 969 970 if (slop1 & 2) { 971 *(int16_t *)dp0 ^= (int16_t)CURSOR_MASK; 972 *(int16_t *)dp1 ^= (int16_t)CURSOR_MASK; 973 dp0 += 2; 974 dp1 += 2; 975 } 976 977 for (cnt = full1; cnt; cnt--) { 978 *(int32_t *)dp0 ^= CURSOR_MASK; 979 *(int32_t *)dp1 ^= CURSOR_MASK; 980 dp0 += 4; 981 dp1 += 4; 982 } 983 984 if (slop2 & 1) { 985 *dp0++ ^= (u_char)CURSOR_MASK; 986 *dp1++ ^= (u_char)CURSOR_MASK; 987 } 988 989 if (slop2 & 2) { 990 *(int16_t *)dp0 ^= (int16_t)CURSOR_MASK; 991 *(int16_t *)dp1 ^= (int16_t)CURSOR_MASK; 992 } 993 } 994 } 995 996 return 0; 997 } 998 999 /* 1000 * Accelerated routines. 1001 */ 1002 1003 int 1004 ifb_copycols(void *cookie, int row, int src, int dst, int num) 1005 { 1006 struct rasops_info *ri = cookie; 1007 struct ifb_softc *sc = ri->ri_hw; 1008 1009 num *= ri->ri_font->fontwidth; 1010 src *= ri->ri_font->fontwidth; 1011 dst *= ri->ri_font->fontwidth; 1012 row *= ri->ri_font->fontheight; 1013 1014 ifb_copyrect(sc, ri->ri_xorigin + src, ri->ri_yorigin + row, 1015 ri->ri_xorigin + dst, ri->ri_yorigin + row, 1016 num, ri->ri_font->fontheight); 1017 1018 return 0; 1019 } 1020 1021 int 1022 ifb_erasecols(void *cookie, int row, int col, int num, long attr) 1023 { 1024 struct rasops_info *ri = cookie; 1025 struct ifb_softc *sc = ri->ri_hw; 1026 int bg, fg; 1027 1028 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 1029 1030 row *= ri->ri_font->fontheight; 1031 col *= ri->ri_font->fontwidth; 1032 num *= ri->ri_font->fontwidth; 1033 1034 ifb_fillrect(sc, ri->ri_xorigin + col, ri->ri_yorigin + row, 1035 num, ri->ri_font->fontheight, ri->ri_devcmap[bg]); 1036 1037 return 0; 1038 } 1039 1040 int 1041 ifb_copyrows(void *cookie, int src, int dst, int num) 1042 { 1043 struct rasops_info *ri = cookie; 1044 struct ifb_softc *sc = ri->ri_hw; 1045 1046 num *= ri->ri_font->fontheight; 1047 src *= ri->ri_font->fontheight; 1048 dst *= ri->ri_font->fontheight; 1049 1050 ifb_copyrect(sc, ri->ri_xorigin, ri->ri_yorigin + src, 1051 ri->ri_xorigin, ri->ri_yorigin + dst, ri->ri_emuwidth, num); 1052 1053 return 0; 1054 } 1055 1056 int 1057 ifb_eraserows(void *cookie, int row, int num, long attr) 1058 { 1059 struct rasops_info *ri = cookie; 1060 struct ifb_softc *sc = ri->ri_hw; 1061 int bg, fg; 1062 int x, y, w; 1063 1064 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 1065 1066 if ((num == ri->ri_rows) && ISSET(ri->ri_flg, RI_FULLCLEAR)) { 1067 num = ri->ri_height; 1068 x = y = 0; 1069 w = ri->ri_width; 1070 } else { 1071 num *= ri->ri_font->fontheight; 1072 x = ri->ri_xorigin; 1073 y = ri->ri_yorigin + row * ri->ri_font->fontheight; 1074 w = ri->ri_emuwidth; 1075 } 1076 ifb_fillrect(sc, x, y, w, num, ri->ri_devcmap[bg]); 1077 1078 return 0; 1079 } 1080 1081 void 1082 ifb_copyrect(struct ifb_softc *sc, int sx, int sy, int dx, int dy, int w, int h) 1083 { 1084 ifb_rop(sc, sx, sy, dx, dy, w, h, IFB_ROP_SRC, IFB_PIXELMASK); 1085 ifb_rop_wait(sc); 1086 } 1087 1088 void 1089 ifb_fillrect(struct ifb_softc *sc, int x, int y, int w, int h, int bg) 1090 { 1091 int32_t mask; 1092 1093 /* pixels to set... */ 1094 mask = IFB_PIXELMASK & bg; 1095 if (mask != 0) { 1096 ifb_rop(sc, x, y, x, y, w, h, IFB_ROP_SET, mask); 1097 ifb_rop_wait(sc); 1098 } 1099 1100 /* pixels to clear... */ 1101 mask = IFB_PIXELMASK & ~bg; 1102 if (mask != 0) { 1103 ifb_rop(sc, x, y, x, y, w, h, IFB_ROP_CLEAR, mask); 1104 ifb_rop_wait(sc); 1105 } 1106 } 1107 1108 /* 1109 * Perform a raster operation on both overlay planes. 1110 * Puzzled by all the magic numbers in there? So are we. Isn't a dire 1111 * lack of documentation wonderful? 1112 */ 1113 1114 static inline void 1115 ifb_rop(struct ifb_softc *sc, int sx, int sy, int dx, int dy, int w, int h, 1116 uint32_t rop, int32_t planemask) 1117 { 1118 (*sc->sc_rop)(sc, sx, sy, dx, dy, w, h, rop, planemask); 1119 } 1120 1121 void 1122 ifb_rop_common(struct ifb_softc *sc, bus_addr_t reg, int sx, int sy, 1123 int dx, int dy, int w, int h, uint32_t rop, int32_t planemask) 1124 { 1125 int dir = 0; 1126 1127 /* 1128 * Compute rop direction. This only really matters for 1129 * screen-to-screen copies. 1130 */ 1131 if (sy < dy /* && sy + h > dy */) { 1132 sy += h - 1; 1133 dy += h; 1134 dir |= IFB_BLT_DIR_BACKWARDS_Y; 1135 } 1136 if (sx < dx /* && sx + w > dx */) { 1137 sx += w - 1; 1138 dx += w; 1139 dir |= IFB_BLT_DIR_BACKWARDS_X; 1140 } 1141 1142 /* Which one of those below is your magic number for today? */ 1143 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x61000001); 1144 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0); 1145 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x6301c080); 1146 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x80000000); 1147 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, rop); 1148 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, planemask); 1149 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0); 1150 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x64000303); 1151 /* 1152 * This value is a pixel offset within the destination area. It is 1153 * probably used to define complex polygon shapes, with the 1154 * last pixel in the list being back to (0,0). 1155 */ 1156 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(0, 0)); 1157 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0); 1158 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x00030000); 1159 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x2200010d); 1160 1161 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x33f01000 | dir); 1162 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(dx, dy)); 1163 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(w, h)); 1164 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(sx, sy)); 1165 } 1166 1167 void 1168 ifb_rop_ifb(void *v, int sx, int sy, int dx, int dy, int w, int h, 1169 uint32_t rop, int32_t planemask) 1170 { 1171 struct ifb_softc *sc = (struct ifb_softc *)v; 1172 bus_addr_t reg = IFB_REG_ENGINE; 1173 1174 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 2); 1175 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 1); 1176 /* the ``0101'' part is probably a component selection */ 1177 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x540101ff); 1178 1179 ifb_rop_common(sc, reg, sx, sy, dx, dy, w, h, rop, planemask); 1180 } 1181 1182 void 1183 ifb_rop_jfb(void *v, int sx, int sy, int dx, int dy, int w, int h, 1184 uint32_t rop, int32_t planemask) 1185 { 1186 struct ifb_softc *sc = (struct ifb_softc *)v; 1187 bus_addr_t reg = JFB_REG_ENGINE; 1188 uint32_t spr, splr; 1189 1190 /* 1191 * Pick the current spr and splr values from the communication 1192 * area if possible. 1193 */ 1194 if (sc->sc_comm != NULL) { 1195 spr = sc->sc_comm[IFB_SHARED_TERM8_SPR >> 2]; 1196 splr = sc->sc_comm[IFB_SHARED_TERM8_SPLR >> 2]; 1197 } else { 1198 /* supposedly sane defaults */ 1199 spr = 0x54ff0303; 1200 splr = 0x5c0000ff; 1201 } 1202 1203 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x00400016); 1204 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5b000002); 1205 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5a000000); 1206 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, spr); 1207 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, splr); 1208 1209 ifb_rop_common(sc, reg, sx, sy, dx, dy, w, h, rop, planemask); 1210 1211 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5a000001); 1212 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5b000001); 1213 } 1214 1215 int 1216 ifb_rop_wait(struct ifb_softc *sc) 1217 { 1218 int i; 1219 1220 for (i = 1000000; i != 0; i--) { 1221 if (bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 1222 IFB_REG_STATUS) & IFB_REG_STATUS_DONE) 1223 break; 1224 DELAY(1); 1225 } 1226 1227 return i; 1228 } 1229 1230 int 1231 ifb_do_cursor(struct rasops_info *ri) 1232 { 1233 struct ifb_softc *sc = ri->ri_hw; 1234 int y, x; 1235 1236 y = ri->ri_yorigin + ri->ri_crow * ri->ri_font->fontheight; 1237 x = ri->ri_xorigin + ri->ri_ccol * ri->ri_font->fontwidth; 1238 1239 ifb_rop(sc, x, y, x, y, ri->ri_font->fontwidth, ri->ri_font->fontheight, 1240 IFB_ROP_XOR, IFB_PIXELMASK); 1241 ifb_rop_wait(sc); 1242 1243 return 0; 1244 } 1245