1 /* $OpenBSD: ifb.c,v 1.21 2013/07/16 22:31:15 miod Exp $ */ 2 3 /* 4 * Copyright (c) 2007, 2008, 2009 Miodrag Vallat. 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Least-effort driver for the Sun Expert3D cards (based on the 21 * ``Wildcat'' chips). 22 * 23 * There is no public documentation for these chips available. 24 * Since they are no longer supported by 3DLabs (which got bought by 25 * Creative), and Sun does not want to publish even minimal information 26 * or source code, the best we can do is experiment. 27 * 28 * Quoting Alan Coopersmith in 29 * http://mail.opensolaris.org/pipermail/opensolaris-discuss/2005-December/011885.html 30 * ``Unfortunately, the lawyers have asked we not give details about why 31 * specific components are not being released.'' 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/ioctl.h> 39 #include <sys/malloc.h> 40 #include <sys/pciio.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <machine/autoconf.h> 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 #include <machine/openfirm.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 52 #include <dev/wscons/wsconsio.h> 53 #include <dev/wscons/wsdisplayvar.h> 54 55 #include <dev/rasops/rasops.h> 56 57 #include <machine/fbvar.h> 58 59 #ifdef APERTURE 60 extern int allowaperture; 61 #endif 62 63 /* 64 * Parts of the following hardware knowledge come from David S. Miller's 65 * XVR-500 Linux driver (drivers/video/sunxvr500.c). 66 */ 67 68 /* 69 * The Expert3D and Expert3d-Lite cards are built around the Wildcat 70 * 5110, 6210 and 7210 chips. 71 * 72 * The card exposes the following resources: 73 * - a 32MB (ifb), 64MB (xvr600) or 128MB (jfb) aperture window in which 74 * views to the different frame buffer areas can be mapped, in the first BAR. 75 * - a 64KB or 128KB PROM and registers area, in the second BAR. 76 * - a 8MB ``direct burst'' memory mapping, in the third BAR. 77 * 78 * The location of this BAR range is pointed to by a board-specific PCI 79 * configuration register. 80 * 81 * In the state the PROM leaves us in, the 8MB frame buffer windows map 82 * the video memory as interleaved stripes, of which the non-visible parts 83 * can still be addressed (probably for fast screen switching). 84 * 85 * Unfortunately, since we do not know how to reconfigure the stripes 86 * to provide at least a linear frame buffer, we have to write to both 87 * windows and have them provide the complete image. 88 * 89 * Moreover, high pixel values in the overlay planes (such as 0xff or 0xfe) 90 * seem to enable other planes with random contents, so we'll limit ourselves 91 * to 7bpp operation. 92 */ 93 94 /* 95 * The Fcode driver sets up a communication structure, allowing third-party 96 * code to reprogram the video mode while still allowing the Fcode routines 97 * to access the overlay planes. 98 * 99 * We'll use this information as well, although so far it's unlikely 100 * any code will do so, as long as the only documentation for this 101 * hardware amounts to zilch. 102 */ 103 104 /* probably some form of signature */ 105 #define IFB_SHARED_SIGNATURE 0x00 106 #define SIG_IFB 0x09209911 107 #define SIG_JFB 0x05140213 108 #define IFB_SHARED_MONITOR_MODE 0x10 109 #define IFB_SHARED_WIDTH 0x14 110 #define IFB_SHARED_HEIGHT 0x18 111 #define IFB_SHARED_V_FREQ 0x1c 112 #define IFB_SHARED_TIMING_H_FP 0x20 113 #define IFB_SHARED_TIMING_H_SYNC 0x24 114 #define IFB_SHARED_TIMING_H_BP 0x28 115 #define IFB_SHARED_TIMING_V_FP 0x2c 116 #define IFB_SHARED_TIMING_V_SYNC 0x30 117 #define IFB_SHARED_TIMING_V_BP 0x34 118 #define IFB_SHARED_TIMING_FLAGS 0x38 119 #define IFB_SHARED_CMAP_DIRTY 0x3c 120 #define IFB_SHARED_TERM8_GSR 0x4c 121 #define IFB_SHARED_TERM8_SPR 0x50 122 #define IFB_SHARED_TERM8_SPLR 0x54 123 124 /* 125 * The Expert3D has an extra BAR that is not present on the -Lite 126 * version. This register contains bits that tell us how many BARs to 127 * skip before we get to the BARs that interest us. 128 */ 129 #define IFB_PCI_CFG 0x5c 130 #define IFB_PCI_CFG_BAR_OFFSET(x) ((x & 0x000000e0) >> 3) 131 132 /* 133 * 6000 (jfb) / 8000 (ifb) engine command 134 * This register is used to issue (some) commands sequences to the 135 * acceleration hardware. 136 */ 137 #define JFB_REG_ENGINE 0x6000 138 #define IFB_REG_ENGINE 0x8000 139 140 /* 141 * 8040 component configuration 142 * This register controls which parts of the board will be addressed by 143 * writes to other configuration registers. 144 * Apparently the low two bytes control the frame buffer windows for the 145 * given head (starting at 1). 146 * The high two bytes are texture related. 147 */ 148 #define IFB_REG_COMPONENT_SELECT 0x8040 149 150 /* 151 * 8044 status 152 * This register has a bit that signals completion of commands issued 153 * to the acceleration hardware. 154 */ 155 #define IFB_REG_STATUS 0x8044 156 #define IFB_REG_STATUS_DONE 0x00000004 157 158 /* 159 * 8058 magnifying configuration 160 * This register apparently controls magnifying. 161 * bits 5-6 select the window width divider (00: by 2, 01: by 4, 10: by 8, 162 * 11: by 16) 163 * bits 7-8 select the zoom factor (00: disabled, 01: x2, 10: x4, 11: x8) 164 */ 165 #define IFB_REG_MAGNIFY 0x8058 166 #define IFB_REG_MAGNIFY_DISABLE 0x00000000 167 #define IFB_REG_MAGNIFY_X2 0x00000040 168 #define IFB_REG_MAGNIFY_X4 0x00000080 169 #define IFB_REG_MAGNIFY_X8 0x000000c0 170 #define IFB_REG_MAGNIFY_WINDIV2 0x00000000 171 #define IFB_REG_MAGNIFY_WINDIV4 0x00000010 172 #define IFB_REG_MAGNIFY_WINDIV8 0x00000020 173 #define IFB_REG_MAGNIFY_WINDIV16 0x00000030 174 175 /* 176 * 8070 display resolution 177 * Contains the size of the display, as ((height - 1) << 16) | (width - 1) 178 */ 179 #define IFB_REG_RESOLUTION 0x8070 180 /* 181 * 8074 configuration register 182 * Contains 0x1a000088 | ((Log2 stride) << 16) 183 */ 184 #define IFB_REG_CONFIG 0x8074 185 /* 186 * 8078 32bit frame buffer window #0 (8 to 9 MB) 187 * Contains the offset (relative to BAR0) of the 32 bit frame buffer window. 188 */ 189 #define IFB_REG_FB32_0 0x8078 190 /* 191 * 807c 32bit frame buffer window #1 (8 to 9 MB) 192 * Contains the offset (relative to BAR0) of the 32 bit frame buffer window. 193 */ 194 #define IFB_REG_FB32_1 0x807c 195 /* 196 * 8080 8bit frame buffer window #0 (2 to 2.2 MB) 197 * Contains the offset (relative to BAR0) of the 8 bit frame buffer window. 198 */ 199 #define IFB_REG_FB8_0 0x8080 200 /* 201 * 8084 8bit frame buffer window #1 (2 to 2.2 MB) 202 * Contains the offset (relative to BAR0) of the 8 bit frame buffer window. 203 */ 204 #define IFB_REG_FB8_1 0x8084 205 /* 206 * 8088 unknown window (as large as a 32 bit frame buffer) 207 */ 208 #define IFB_REG_FB_UNK0 0x8088 209 /* 210 * 808c unknown window (as large as a 8 bit frame buffer) 211 */ 212 #define IFB_REG_FB_UNK1 0x808c 213 /* 214 * 8090 unknown window (as large as a 8 bit frame buffer) 215 */ 216 #define IFB_REG_FB_UNK2 0x8090 217 218 /* 219 * 80bc RAMDAC palette index register 220 */ 221 #define IFB_REG_CMAP_INDEX 0x80bc 222 /* 223 * 80c0 RAMDAC palette data register 224 */ 225 #define IFB_REG_CMAP_DATA 0x80c0 226 227 /* 228 * 80e4 DPMS state register 229 * States ``off'' and ``suspend'' need chip reprogramming before video can 230 * be enabled again. 231 */ 232 #define IFB_REG_DPMS_STATE 0x80e4 233 #define IFB_REG_DPMS_OFF 0x00000000 234 #define IFB_REG_DPMS_SUSPEND 0x00000001 235 #define IFB_REG_DPMS_STANDBY 0x00000002 236 #define IFB_REG_DPMS_ON 0x00000003 237 238 /* 239 * (some) ROP codes 240 */ 241 242 #define IFB_ROP_CLEAR 0x00000000 /* clear bits in rop mask */ 243 #define IFB_ROP_SRC 0x00330000 /* copy src bits matching rop mask */ 244 #define IFB_ROP_XOR 0x00cc0000 /* xor src bits with rop mask */ 245 #define IFB_ROP_SET 0x00ff0000 /* set bits in rop mask */ 246 247 #define IFB_COORDS(x, y) ((x) | (y) << 16) 248 249 /* blitter directions */ 250 #define IFB_BLT_DIR_BACKWARDS_Y (0x08 | 0x02) 251 #define IFB_BLT_DIR_BACKWARDS_X (0x04 | 0x01) 252 253 #define IFB_PIXELMASK 0x7f /* 7bpp */ 254 255 struct ifb_softc { 256 struct sunfb sc_sunfb; 257 258 bus_space_tag_t sc_mem_t; 259 pcitag_t sc_pcitag; 260 261 /* overlays mappings */ 262 bus_space_handle_t sc_mem_h; 263 bus_addr_t sc_membase, sc_fb8bank0_base, sc_fb8bank1_base; 264 bus_size_t sc_memlen; 265 vaddr_t sc_memvaddr, sc_fb8bank0_vaddr, sc_fb8bank1_vaddr; 266 267 /* registers mapping */ 268 bus_space_handle_t sc_reg_h; 269 bus_addr_t sc_regbase; 270 bus_size_t sc_reglen; 271 272 /* communication area */ 273 volatile uint32_t *sc_comm; 274 275 /* acceleration information */ 276 u_int sc_acceltype; 277 #define IFB_ACCEL_NONE 0 278 #define IFB_ACCEL_IFB 1 /* Expert3D style */ 279 #define IFB_ACCEL_JFB 2 /* XVR-500 style */ 280 void (*sc_rop)(void *, int, int, int, int, int, int, uint32_t, int32_t); 281 282 /* wsdisplay related goo */ 283 u_int sc_mode; 284 struct wsdisplay_emulops sc_old_ops; 285 u_int8_t sc_cmap_red[256]; 286 u_int8_t sc_cmap_green[256]; 287 u_int8_t sc_cmap_blue[256]; 288 }; 289 290 int ifb_ioctl(void *, u_long, caddr_t, int, struct proc *); 291 paddr_t ifb_mmap(void *, off_t, int); 292 void ifb_burner(void *, u_int, u_int); 293 294 struct wsdisplay_accessops ifb_accessops = { 295 ifb_ioctl, 296 ifb_mmap, 297 NULL, /* alloc_screen */ 298 NULL, /* free_screen */ 299 NULL, /* show_screen */ 300 NULL, /* load_font */ 301 NULL, /* scrollback */ 302 NULL, /* getchar */ 303 ifb_burner, 304 NULL /* pollc */ 305 }; 306 307 int ifbmatch(struct device *, void *, void *); 308 void ifbattach(struct device *, struct device *, void *); 309 310 struct cfattach ifb_ca = { 311 sizeof (struct ifb_softc), ifbmatch, ifbattach 312 }; 313 314 struct cfdriver ifb_cd = { 315 NULL, "ifb", DV_DULL 316 }; 317 318 int ifb_accel_identify(const char *); 319 static inline 320 u_int ifb_dac_value(u_int, u_int, u_int); 321 int ifb_getcmap(struct ifb_softc *, struct wsdisplay_cmap *); 322 static inline 323 int ifb_is_console(int); 324 int ifb_mapregs(struct ifb_softc *, struct pci_attach_args *); 325 int ifb_putcmap(struct ifb_softc *, struct wsdisplay_cmap *); 326 void ifb_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t); 327 void ifb_setcolormap(struct sunfb *, 328 void (*)(void *, u_int, u_int8_t, u_int8_t, u_int8_t)); 329 330 void ifb_copyrect(struct ifb_softc *, int, int, int, int, int, int); 331 void ifb_fillrect(struct ifb_softc *, int, int, int, int, int); 332 static inline 333 void ifb_rop(struct ifb_softc *, int, int, int, int, int, int, uint32_t, 334 int32_t); 335 void ifb_rop_common(struct ifb_softc *, bus_addr_t, int, int, int, int, 336 int, int, uint32_t, int32_t); 337 void ifb_rop_ifb(void *, int, int, int, int, int, int, uint32_t, int32_t); 338 void ifb_rop_jfb(void *, int, int, int, int, int, int, uint32_t, int32_t); 339 int ifb_rop_wait(struct ifb_softc *); 340 341 int ifb_putchar_dumb(void *, int, int, u_int, long); 342 int ifb_copycols_dumb(void *, int, int, int, int); 343 int ifb_erasecols_dumb(void *, int, int, int, long); 344 int ifb_copyrows_dumb(void *, int, int, int); 345 int ifb_eraserows_dumb(void *, int, int, long); 346 int ifb_do_cursor_dumb(struct rasops_info *); 347 348 int ifb_putchar(void *, int, int, u_int, long); 349 int ifb_copycols(void *, int, int, int, int); 350 int ifb_erasecols(void *, int, int, int, long); 351 int ifb_copyrows(void *, int, int, int); 352 int ifb_eraserows(void *, int, int, long); 353 int ifb_do_cursor(struct rasops_info *); 354 355 int 356 ifbmatch(struct device *parent, void *cf, void *aux) 357 { 358 return ifb_ident(aux); 359 } 360 361 void 362 ifbattach(struct device *parent, struct device *self, void *aux) 363 { 364 struct ifb_softc *sc = (struct ifb_softc *)self; 365 struct pci_attach_args *paa = aux; 366 struct rasops_info *ri; 367 uint32_t dev_comm; 368 int node, console; 369 char *name, *text; 370 char namebuf[32]; 371 372 sc->sc_mem_t = paa->pa_memt; 373 sc->sc_pcitag = paa->pa_tag; 374 375 node = PCITAG_NODE(paa->pa_tag); 376 console = ifb_is_console(node); 377 378 printf("\n"); 379 380 /* 381 * Multiple heads appear as PCI subfunctions. 382 * However, the ofw node for it lacks most properties, 383 * and its BAR only give access to registers, not 384 * frame buffer memory. 385 */ 386 if (!node_has_property(node, "device_type")) { 387 printf("%s: secondary output not supported yet\n", 388 self->dv_xname); 389 return; 390 } 391 392 /* 393 * Describe the beast. 394 */ 395 396 name = text = getpropstringA(node, "name", namebuf); 397 if (strncmp(text, "SUNW,", 5) == 0) 398 text += 5; 399 printf("%s: %s", self->dv_xname, text); 400 text = getpropstring(node, "model"); 401 if (*text != '\0') 402 printf(" (%s)", text); 403 404 if (ifb_mapregs(sc, paa)) 405 return; 406 407 sc->sc_fb8bank0_base = bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 408 IFB_REG_FB8_0); 409 sc->sc_fb8bank1_base = bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 410 IFB_REG_FB8_1); 411 412 sc->sc_memvaddr = (vaddr_t)bus_space_vaddr(sc->sc_mem_t, sc->sc_mem_h); 413 sc->sc_fb8bank0_vaddr = sc->sc_memvaddr + 414 sc->sc_fb8bank0_base - sc->sc_membase; 415 sc->sc_fb8bank1_vaddr = sc->sc_memvaddr + 416 sc->sc_fb8bank1_base - sc->sc_membase; 417 418 /* 419 * The values stored into the node properties might have been 420 * modified since the Fcode was last run. Pick the geometry 421 * information from the configuration registers instead. 422 * This replaces 423 fb_setsize(&sc->sc_sunfb, 8, 1152, 900, node, 0); 424 */ 425 426 sc->sc_sunfb.sf_width = (bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 427 IFB_REG_RESOLUTION) & 0xffff) + 1; 428 sc->sc_sunfb.sf_height = (bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 429 IFB_REG_RESOLUTION) >> 16) + 1; 430 sc->sc_sunfb.sf_depth = 8; 431 sc->sc_sunfb.sf_linebytes = 1 << (bus_space_read_4(sc->sc_mem_t, 432 sc->sc_reg_h, IFB_REG_CONFIG) >> 16); 433 sc->sc_sunfb.sf_fbsize = 434 sc->sc_sunfb.sf_height * sc->sc_sunfb.sf_linebytes; 435 436 printf(", %dx%d\n", sc->sc_sunfb.sf_width, sc->sc_sunfb.sf_height); 437 438 ri = &sc->sc_sunfb.sf_ro; 439 ri->ri_bits = NULL; 440 ri->ri_hw = sc; 441 442 fbwscons_init(&sc->sc_sunfb, RI_BSWAP, console); 443 444 /* 445 * Find out what flavour of ifb we are... 446 */ 447 448 sc->sc_acceltype = ifb_accel_identify(name); 449 450 switch (sc->sc_acceltype) { 451 case IFB_ACCEL_IFB: 452 sc->sc_rop = ifb_rop_ifb; 453 break; 454 case IFB_ACCEL_JFB: 455 /* 456 * Remember the address of the communication area 457 */ 458 if (OF_getprop(node, "dev-comm", &dev_comm, 459 sizeof dev_comm) != -1) { 460 sc->sc_comm = (volatile uint32_t *)(vaddr_t)dev_comm; 461 } 462 sc->sc_rop = ifb_rop_jfb; 463 break; 464 } 465 466 /* 467 * Clear the unwanted pixel planes: all if non console (thus 468 * white background), and all planes above 7bpp otherwise. 469 * This also allows to check whether the accelerated code works, 470 * or not. 471 */ 472 473 if (sc->sc_acceltype != IFB_ACCEL_NONE) { 474 ifb_rop(sc, 0, 0, 0, 0, sc->sc_sunfb.sf_width, 475 sc->sc_sunfb.sf_height, IFB_ROP_CLEAR, 476 console ? ~IFB_PIXELMASK : ~0); 477 if (ifb_rop_wait(sc) == 0) { 478 /* fall back to dumb software operation */ 479 sc->sc_acceltype = IFB_ACCEL_NONE; 480 } 481 } 482 483 if (sc->sc_acceltype == IFB_ACCEL_NONE) { 484 /* due to the way we will handle updates */ 485 ri->ri_flg &= ~RI_FULLCLEAR; 486 487 if (!console) { 488 bzero((void *)sc->sc_fb8bank0_vaddr, 489 sc->sc_sunfb.sf_fbsize); 490 bzero((void *)sc->sc_fb8bank1_vaddr, 491 sc->sc_sunfb.sf_fbsize); 492 } 493 } 494 495 /* pick centering delta */ 496 sc->sc_fb8bank0_vaddr += ri->ri_bits - ri->ri_origbits; 497 sc->sc_fb8bank1_vaddr += ri->ri_bits - ri->ri_origbits; 498 499 sc->sc_old_ops = ri->ri_ops; /* structure copy */ 500 501 if (sc->sc_acceltype != IFB_ACCEL_NONE) { 502 ri->ri_ops.copyrows = ifb_copyrows; 503 ri->ri_ops.copycols = ifb_copycols; 504 ri->ri_ops.eraserows = ifb_eraserows; 505 ri->ri_ops.erasecols = ifb_erasecols; 506 ri->ri_ops.putchar = ifb_putchar_dumb; 507 ri->ri_do_cursor = ifb_do_cursor; 508 } else { 509 ri->ri_ops.copyrows = ifb_copyrows_dumb; 510 ri->ri_ops.copycols = ifb_copycols_dumb; 511 ri->ri_ops.eraserows = ifb_eraserows_dumb; 512 ri->ri_ops.erasecols = ifb_erasecols_dumb; 513 ri->ri_ops.putchar = ifb_putchar_dumb; 514 ri->ri_do_cursor = ifb_do_cursor_dumb; 515 } 516 517 ifb_setcolormap(&sc->sc_sunfb, ifb_setcolor); 518 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 519 520 if (console) 521 fbwscons_console_init(&sc->sc_sunfb, -1); 522 fbwscons_attach(&sc->sc_sunfb, &ifb_accessops, console); 523 } 524 525 /* 526 * Attempt to identify what kind of ifb we are talking to, so as to setup 527 * proper acceleration information. 528 */ 529 int 530 ifb_accel_identify(const char *name) 531 { 532 if (strcmp(name, "SUNW,Expert3D") == 0 || 533 strcmp(name, "SUNW,Expert3D-Lite") == 0) 534 return IFB_ACCEL_IFB; /* ifblite */ 535 536 if (strcmp(name, "SUNW,XVR-1200") == 0) 537 return IFB_ACCEL_JFB; /* jfb */ 538 539 if (strcmp(name, "SUNW,XVR-600") == 0) 540 return IFB_ACCEL_JFB; /* xvr600 */ 541 542 /* XVR-500 is bobcat */ 543 544 return IFB_ACCEL_NONE; 545 } 546 547 int 548 ifb_ioctl(void *v, u_long cmd, caddr_t data, int flags, struct proc *p) 549 { 550 struct ifb_softc *sc = v; 551 struct wsdisplay_fbinfo *wdf; 552 struct pcisel *sel; 553 int mode; 554 555 switch (cmd) { 556 case WSDISPLAYIO_GTYPE: 557 *(u_int *)data = WSDISPLAY_TYPE_IFB; 558 break; 559 560 case WSDISPLAYIO_SMODE: 561 mode = *(u_int *)data; 562 if (mode == WSDISPLAYIO_MODE_EMUL) 563 ifb_setcolormap(&sc->sc_sunfb, ifb_setcolor); 564 sc->sc_mode = mode; 565 break; 566 case WSDISPLAYIO_GINFO: 567 wdf = (void *)data; 568 wdf->height = sc->sc_sunfb.sf_height; 569 wdf->width = sc->sc_sunfb.sf_width; 570 wdf->depth = sc->sc_sunfb.sf_depth; 571 wdf->cmsize = 256; 572 break; 573 case WSDISPLAYIO_LINEBYTES: 574 *(u_int *)data = sc->sc_sunfb.sf_linebytes; 575 break; 576 577 case WSDISPLAYIO_GETCMAP: 578 return ifb_getcmap(sc, (struct wsdisplay_cmap *)data); 579 case WSDISPLAYIO_PUTCMAP: 580 return ifb_putcmap(sc, (struct wsdisplay_cmap *)data); 581 582 case WSDISPLAYIO_GPCIID: 583 sel = (struct pcisel *)data; 584 sel->pc_bus = PCITAG_BUS(sc->sc_pcitag); 585 sel->pc_dev = PCITAG_DEV(sc->sc_pcitag); 586 sel->pc_func = PCITAG_FUN(sc->sc_pcitag); 587 break; 588 589 case WSDISPLAYIO_SVIDEO: 590 case WSDISPLAYIO_GVIDEO: 591 break; 592 593 case WSDISPLAYIO_GCURPOS: 594 case WSDISPLAYIO_SCURPOS: 595 case WSDISPLAYIO_GCURMAX: 596 case WSDISPLAYIO_GCURSOR: 597 case WSDISPLAYIO_SCURSOR: 598 default: 599 return -1; /* not supported yet */ 600 } 601 602 return 0; 603 } 604 605 static inline 606 u_int 607 ifb_dac_value(u_int r, u_int g, u_int b) 608 { 609 /* 610 * Convert 8 bit values to 10 bit scale, by shifting and inserting 611 * the former high bits in the low two bits. 612 * Simply shifting is sligthly too dull. 613 */ 614 r = (r << 2) | (r >> 6); 615 g = (g << 2) | (g >> 6); 616 b = (b << 2) | (b >> 6); 617 618 return (b << 20) | (g << 10) | r; 619 } 620 621 int 622 ifb_getcmap(struct ifb_softc *sc, struct wsdisplay_cmap *cm) 623 { 624 u_int index = cm->index; 625 u_int count = cm->count; 626 int error; 627 628 if (index >= 256 || count > 256 - index) 629 return EINVAL; 630 631 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 632 if (error) 633 return error; 634 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 635 if (error) 636 return error; 637 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 638 if (error) 639 return error; 640 return 0; 641 } 642 643 int 644 ifb_putcmap(struct ifb_softc *sc, struct wsdisplay_cmap *cm) 645 { 646 u_int index = cm->index; 647 u_int count = cm->count; 648 u_int i; 649 int error; 650 u_char *r, *g, *b; 651 652 if (index >= 256 || count > 256 - index) 653 return EINVAL; 654 655 if ((error = copyin(cm->red, &sc->sc_cmap_red[index], count)) != 0) 656 return error; 657 if ((error = copyin(cm->green, &sc->sc_cmap_green[index], count)) != 0) 658 return error; 659 if ((error = copyin(cm->blue, &sc->sc_cmap_blue[index], count)) != 0) 660 return error; 661 662 r = &sc->sc_cmap_red[index]; 663 g = &sc->sc_cmap_green[index]; 664 b = &sc->sc_cmap_blue[index]; 665 666 for (i = 0; i < count; i++) { 667 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, 668 IFB_REG_CMAP_INDEX, index); 669 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, IFB_REG_CMAP_DATA, 670 ifb_dac_value(*r, *g, *b)); 671 r++, g++, b++, index++; 672 } 673 return 0; 674 } 675 676 void 677 ifb_setcolor(void *v, u_int index, u_int8_t r, u_int8_t g, u_int8_t b) 678 { 679 struct ifb_softc *sc = v; 680 681 sc->sc_cmap_red[index] = r; 682 sc->sc_cmap_green[index] = g; 683 sc->sc_cmap_blue[index] = b; 684 685 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, IFB_REG_CMAP_INDEX, 686 index); 687 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, IFB_REG_CMAP_DATA, 688 ifb_dac_value(r, g, b)); 689 } 690 691 /* similar in spirit to fbwscons_setcolormap() */ 692 void 693 ifb_setcolormap(struct sunfb *sf, 694 void (*setcolor)(void *, u_int, u_int8_t, u_int8_t, u_int8_t)) 695 { 696 struct rasops_info *ri = &sf->sf_ro; 697 int i; 698 const u_char *color; 699 700 /* 701 * Compensate for overlay plane limitations. Since we'll operate 702 * in 7bpp mode, our basic colors will use positions 00 to 0f, 703 * and the inverted colors will use positions 7f to 70. 704 */ 705 706 for (i = 0x00; i < 0x10; i++) { 707 color = &rasops_cmap[i * 3]; 708 setcolor(sf, i, color[0], color[1], color[2]); 709 } 710 for (i = 0x70; i < 0x80; i++) { 711 color = &rasops_cmap[(0xf0 | i) * 3]; 712 setcolor(sf, i, color[0], color[1], color[2]); 713 } 714 715 /* 716 * Proper operation apparently needs black to be 01, always. 717 * Replace black, red and white with white, black and red. 718 * Kind of ugly, but it works. 719 */ 720 ri->ri_devcmap[WSCOL_WHITE] = 0x00000000; 721 ri->ri_devcmap[WSCOL_BLACK] = 0x01010101; 722 ri->ri_devcmap[WSCOL_RED] = 0x07070707; 723 724 color = &rasops_cmap[(WSCOL_WHITE + 8) * 3]; /* real white */ 725 setcolor(sf, 0, color[0], color[1], color[2]); 726 setcolor(sf, IFB_PIXELMASK ^ 0, ~color[0], ~color[1], ~color[2]); 727 color = &rasops_cmap[WSCOL_BLACK * 3]; 728 setcolor(sf, 1, color[0], color[1], color[2]); 729 setcolor(sf, IFB_PIXELMASK ^ 1, ~color[0], ~color[1], ~color[2]); 730 color = &rasops_cmap[WSCOL_RED * 3]; 731 setcolor(sf, 7, color[0], color[1], color[2]); 732 setcolor(sf, IFB_PIXELMASK ^ 7, ~color[0], ~color[1], ~color[2]); 733 } 734 735 paddr_t 736 ifb_mmap(void *v, off_t off, int prot) 737 { 738 struct ifb_softc *sc = (struct ifb_softc *)v; 739 740 switch (sc->sc_mode) { 741 case WSDISPLAYIO_MODE_MAPPED: 742 /* 743 * In mapped mode, provide access to the two overlays, 744 * followed by the control registers, at the following 745 * addresses: 746 * 00000000 overlay 0, size up to 2MB (visible fb size) 747 * 01000000 overlay 1, size up to 2MB (visible fb size) 748 * 02000000 control registers 749 */ 750 off -= 0x00000000; 751 if (off >= 0 && off < round_page(sc->sc_sunfb.sf_fbsize)) { 752 return bus_space_mmap(sc->sc_mem_t, 753 sc->sc_fb8bank0_base, 754 off, prot, BUS_SPACE_MAP_LINEAR); 755 } 756 off -= 0x01000000; 757 if (off >= 0 && off < round_page(sc->sc_sunfb.sf_fbsize)) { 758 return bus_space_mmap(sc->sc_mem_t, 759 sc->sc_fb8bank1_base, 760 off, prot, BUS_SPACE_MAP_LINEAR); 761 } 762 #ifdef APERTURE 763 off -= 0x01000000; 764 if (allowaperture != 0 && sc->sc_acceltype != IFB_ACCEL_NONE) { 765 if (off >= 0 && off < round_page(sc->sc_reglen)) { 766 return bus_space_mmap(sc->sc_mem_t, 767 sc->sc_regbase, 768 off, prot, BUS_SPACE_MAP_LINEAR); 769 } 770 } 771 #endif 772 break; 773 } 774 775 return -1; 776 } 777 778 void 779 ifb_burner(void *v, u_int on, u_int flags) 780 { 781 struct ifb_softc *sc = (struct ifb_softc *)v; 782 int s; 783 uint32_t dpms; 784 785 s = splhigh(); 786 if (on) 787 dpms = IFB_REG_DPMS_ON; 788 else { 789 #ifdef notyet 790 if (flags & WSDISPLAY_BURN_VBLANK) 791 dpms = IFB_REG_DPMS_SUSPEND; 792 else 793 #endif 794 dpms = IFB_REG_DPMS_STANDBY; 795 } 796 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, IFB_REG_DPMS_STATE, dpms); 797 splx(s); 798 } 799 800 static inline int 801 ifb_is_console(int node) 802 { 803 extern int fbnode; 804 805 return fbnode == node; 806 } 807 808 int 809 ifb_mapregs(struct ifb_softc *sc, struct pci_attach_args *pa) 810 { 811 u_int32_t cf; 812 int bar, rc; 813 814 cf = pci_conf_read(pa->pa_pc, pa->pa_tag, IFB_PCI_CFG); 815 bar = PCI_MAPREG_START + IFB_PCI_CFG_BAR_OFFSET(cf); 816 817 cf = pci_conf_read(pa->pa_pc, pa->pa_tag, bar); 818 if (PCI_MAPREG_TYPE(cf) == PCI_MAPREG_TYPE_IO) 819 rc = EINVAL; 820 else { 821 rc = pci_mapreg_map(pa, bar, cf, 822 BUS_SPACE_MAP_LINEAR, NULL, &sc->sc_mem_h, 823 &sc->sc_membase, &sc->sc_memlen, 0); 824 } 825 if (rc != 0) { 826 printf("\n%s: can't map video memory\n", 827 sc->sc_sunfb.sf_dev.dv_xname); 828 return rc; 829 } 830 831 cf = pci_conf_read(pa->pa_pc, pa->pa_tag, bar + 4); 832 if (PCI_MAPREG_TYPE(cf) == PCI_MAPREG_TYPE_IO) 833 rc = EINVAL; 834 else { 835 rc = pci_mapreg_map(pa, bar + 4, cf, 836 0, NULL, &sc->sc_reg_h, 837 &sc->sc_regbase, &sc->sc_reglen, 0x9000); 838 } 839 if (rc != 0) { 840 printf("\n%s: can't map register space\n", 841 sc->sc_sunfb.sf_dev.dv_xname); 842 return rc; 843 } 844 845 return 0; 846 } 847 848 /* 849 * Non accelerated routines. 850 */ 851 852 int 853 ifb_putchar_dumb(void *cookie, int row, int col, u_int uc, long attr) 854 { 855 struct rasops_info *ri = cookie; 856 struct ifb_softc *sc = ri->ri_hw; 857 858 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 859 sc->sc_old_ops.putchar(cookie, row, col, uc, attr); 860 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 861 sc->sc_old_ops.putchar(cookie, row, col, uc, attr); 862 863 return 0; 864 } 865 866 int 867 ifb_copycols_dumb(void *cookie, int row, int src, int dst, int num) 868 { 869 struct rasops_info *ri = cookie; 870 struct ifb_softc *sc = ri->ri_hw; 871 872 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 873 sc->sc_old_ops.copycols(cookie, row, src, dst, num); 874 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 875 sc->sc_old_ops.copycols(cookie, row, src, dst, num); 876 877 return 0; 878 } 879 880 int 881 ifb_erasecols_dumb(void *cookie, int row, int col, int num, long attr) 882 { 883 struct rasops_info *ri = cookie; 884 struct ifb_softc *sc = ri->ri_hw; 885 886 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 887 sc->sc_old_ops.erasecols(cookie, row, col, num, attr); 888 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 889 sc->sc_old_ops.erasecols(cookie, row, col, num, attr); 890 891 return 0; 892 } 893 894 int 895 ifb_copyrows_dumb(void *cookie, int src, int dst, int num) 896 { 897 struct rasops_info *ri = cookie; 898 struct ifb_softc *sc = ri->ri_hw; 899 900 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 901 sc->sc_old_ops.copyrows(cookie, src, dst, num); 902 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 903 sc->sc_old_ops.copyrows(cookie, src, dst, num); 904 905 return 0; 906 } 907 908 int 909 ifb_eraserows_dumb(void *cookie, int row, int num, long attr) 910 { 911 struct rasops_info *ri = cookie; 912 struct ifb_softc *sc = ri->ri_hw; 913 914 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 915 sc->sc_old_ops.eraserows(cookie, row, num, attr); 916 ri->ri_bits = (void *)sc->sc_fb8bank1_vaddr; 917 sc->sc_old_ops.eraserows(cookie, row, num, attr); 918 919 return 0; 920 } 921 922 /* Similar to rasops_do_cursor(), but using a 7bit pixel mask. */ 923 924 #define CURSOR_MASK 0x7f7f7f7f 925 926 int 927 ifb_do_cursor_dumb(struct rasops_info *ri) 928 { 929 struct ifb_softc *sc = ri->ri_hw; 930 int full1, height, cnt, slop1, slop2, row, col; 931 int ovl_offset = sc->sc_fb8bank1_vaddr - sc->sc_fb8bank0_vaddr; 932 u_char *dp0, *dp1, *rp; 933 934 row = ri->ri_crow; 935 col = ri->ri_ccol; 936 937 ri->ri_bits = (void *)sc->sc_fb8bank0_vaddr; 938 rp = ri->ri_bits + row * ri->ri_yscale + col * ri->ri_xscale; 939 height = ri->ri_font->fontheight; 940 slop1 = (4 - ((long)rp & 3)) & 3; 941 942 if (slop1 > ri->ri_xscale) 943 slop1 = ri->ri_xscale; 944 945 slop2 = (ri->ri_xscale - slop1) & 3; 946 full1 = (ri->ri_xscale - slop1 - slop2) >> 2; 947 948 if ((slop1 | slop2) == 0) { 949 /* A common case */ 950 while (height--) { 951 dp0 = rp; 952 dp1 = dp0 + ovl_offset; 953 rp += ri->ri_stride; 954 955 for (cnt = full1; cnt; cnt--) { 956 *(int32_t *)dp0 ^= CURSOR_MASK; 957 *(int32_t *)dp1 ^= CURSOR_MASK; 958 dp0 += 4; 959 dp1 += 4; 960 } 961 } 962 } else { 963 /* XXX this is stupid.. use masks instead */ 964 while (height--) { 965 dp0 = rp; 966 dp1 = dp0 + ovl_offset; 967 rp += ri->ri_stride; 968 969 if (slop1 & 1) { 970 *dp0++ ^= (u_char)CURSOR_MASK; 971 *dp1++ ^= (u_char)CURSOR_MASK; 972 } 973 974 if (slop1 & 2) { 975 *(int16_t *)dp0 ^= (int16_t)CURSOR_MASK; 976 *(int16_t *)dp1 ^= (int16_t)CURSOR_MASK; 977 dp0 += 2; 978 dp1 += 2; 979 } 980 981 for (cnt = full1; cnt; cnt--) { 982 *(int32_t *)dp0 ^= CURSOR_MASK; 983 *(int32_t *)dp1 ^= CURSOR_MASK; 984 dp0 += 4; 985 dp1 += 4; 986 } 987 988 if (slop2 & 1) { 989 *dp0++ ^= (u_char)CURSOR_MASK; 990 *dp1++ ^= (u_char)CURSOR_MASK; 991 } 992 993 if (slop2 & 2) { 994 *(int16_t *)dp0 ^= (int16_t)CURSOR_MASK; 995 *(int16_t *)dp1 ^= (int16_t)CURSOR_MASK; 996 } 997 } 998 } 999 1000 return 0; 1001 } 1002 1003 /* 1004 * Accelerated routines. 1005 */ 1006 1007 int 1008 ifb_copycols(void *cookie, int row, int src, int dst, int num) 1009 { 1010 struct rasops_info *ri = cookie; 1011 struct ifb_softc *sc = ri->ri_hw; 1012 1013 num *= ri->ri_font->fontwidth; 1014 src *= ri->ri_font->fontwidth; 1015 dst *= ri->ri_font->fontwidth; 1016 row *= ri->ri_font->fontheight; 1017 1018 ifb_copyrect(sc, ri->ri_xorigin + src, ri->ri_yorigin + row, 1019 ri->ri_xorigin + dst, ri->ri_yorigin + row, 1020 num, ri->ri_font->fontheight); 1021 1022 return 0; 1023 } 1024 1025 int 1026 ifb_erasecols(void *cookie, int row, int col, int num, long attr) 1027 { 1028 struct rasops_info *ri = cookie; 1029 struct ifb_softc *sc = ri->ri_hw; 1030 int bg, fg; 1031 1032 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 1033 1034 row *= ri->ri_font->fontheight; 1035 col *= ri->ri_font->fontwidth; 1036 num *= ri->ri_font->fontwidth; 1037 1038 ifb_fillrect(sc, ri->ri_xorigin + col, ri->ri_yorigin + row, 1039 num, ri->ri_font->fontheight, ri->ri_devcmap[bg]); 1040 1041 return 0; 1042 } 1043 1044 int 1045 ifb_copyrows(void *cookie, int src, int dst, int num) 1046 { 1047 struct rasops_info *ri = cookie; 1048 struct ifb_softc *sc = ri->ri_hw; 1049 1050 num *= ri->ri_font->fontheight; 1051 src *= ri->ri_font->fontheight; 1052 dst *= ri->ri_font->fontheight; 1053 1054 ifb_copyrect(sc, ri->ri_xorigin, ri->ri_yorigin + src, 1055 ri->ri_xorigin, ri->ri_yorigin + dst, ri->ri_emuwidth, num); 1056 1057 return 0; 1058 } 1059 1060 int 1061 ifb_eraserows(void *cookie, int row, int num, long attr) 1062 { 1063 struct rasops_info *ri = cookie; 1064 struct ifb_softc *sc = ri->ri_hw; 1065 int bg, fg; 1066 int x, y, w; 1067 1068 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 1069 1070 if ((num == ri->ri_rows) && ISSET(ri->ri_flg, RI_FULLCLEAR)) { 1071 num = ri->ri_height; 1072 x = y = 0; 1073 w = ri->ri_width; 1074 } else { 1075 num *= ri->ri_font->fontheight; 1076 x = ri->ri_xorigin; 1077 y = ri->ri_yorigin + row * ri->ri_font->fontheight; 1078 w = ri->ri_emuwidth; 1079 } 1080 ifb_fillrect(sc, x, y, w, num, ri->ri_devcmap[bg]); 1081 1082 return 0; 1083 } 1084 1085 void 1086 ifb_copyrect(struct ifb_softc *sc, int sx, int sy, int dx, int dy, int w, int h) 1087 { 1088 ifb_rop(sc, sx, sy, dx, dy, w, h, IFB_ROP_SRC, IFB_PIXELMASK); 1089 ifb_rop_wait(sc); 1090 } 1091 1092 void 1093 ifb_fillrect(struct ifb_softc *sc, int x, int y, int w, int h, int bg) 1094 { 1095 int32_t mask; 1096 1097 /* pixels to set... */ 1098 mask = IFB_PIXELMASK & bg; 1099 if (mask != 0) { 1100 ifb_rop(sc, x, y, x, y, w, h, IFB_ROP_SET, mask); 1101 ifb_rop_wait(sc); 1102 } 1103 1104 /* pixels to clear... */ 1105 mask = IFB_PIXELMASK & ~bg; 1106 if (mask != 0) { 1107 ifb_rop(sc, x, y, x, y, w, h, IFB_ROP_CLEAR, mask); 1108 ifb_rop_wait(sc); 1109 } 1110 } 1111 1112 /* 1113 * Perform a raster operation on both overlay planes. 1114 * Puzzled by all the magic numbers in there? So are we. Isn't a dire 1115 * lack of documentation wonderful? 1116 */ 1117 1118 static inline void 1119 ifb_rop(struct ifb_softc *sc, int sx, int sy, int dx, int dy, int w, int h, 1120 uint32_t rop, int32_t planemask) 1121 { 1122 (*sc->sc_rop)(sc, sx, sy, dx, dy, w, h, rop, planemask); 1123 } 1124 1125 void 1126 ifb_rop_common(struct ifb_softc *sc, bus_addr_t reg, int sx, int sy, 1127 int dx, int dy, int w, int h, uint32_t rop, int32_t planemask) 1128 { 1129 int dir = 0; 1130 1131 /* 1132 * Compute rop direction. This only really matters for 1133 * screen-to-screen copies. 1134 */ 1135 if (sy < dy /* && sy + h > dy */) { 1136 sy += h - 1; 1137 dy += h; 1138 dir |= IFB_BLT_DIR_BACKWARDS_Y; 1139 } 1140 if (sx < dx /* && sx + w > dx */) { 1141 sx += w - 1; 1142 dx += w; 1143 dir |= IFB_BLT_DIR_BACKWARDS_X; 1144 } 1145 1146 /* Which one of those below is your magic number for today? */ 1147 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x61000001); 1148 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0); 1149 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x6301c080); 1150 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x80000000); 1151 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, rop); 1152 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, planemask); 1153 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0); 1154 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x64000303); 1155 /* 1156 * This value is a pixel offset within the destination area. It is 1157 * probably used to define complex polygon shapes, with the 1158 * last pixel in the list being back to (0,0). 1159 */ 1160 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(0, 0)); 1161 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0); 1162 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x00030000); 1163 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x2200010d); 1164 1165 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x33f01000 | dir); 1166 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(dx, dy)); 1167 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(w, h)); 1168 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(sx, sy)); 1169 } 1170 1171 void 1172 ifb_rop_ifb(void *v, int sx, int sy, int dx, int dy, int w, int h, 1173 uint32_t rop, int32_t planemask) 1174 { 1175 struct ifb_softc *sc = (struct ifb_softc *)v; 1176 bus_addr_t reg = IFB_REG_ENGINE; 1177 1178 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 2); 1179 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 1); 1180 /* the ``0101'' part is probably a component selection */ 1181 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x540101ff); 1182 1183 ifb_rop_common(sc, reg, sx, sy, dx, dy, w, h, rop, planemask); 1184 } 1185 1186 void 1187 ifb_rop_jfb(void *v, int sx, int sy, int dx, int dy, int w, int h, 1188 uint32_t rop, int32_t planemask) 1189 { 1190 struct ifb_softc *sc = (struct ifb_softc *)v; 1191 bus_addr_t reg = JFB_REG_ENGINE; 1192 uint32_t spr, splr; 1193 1194 /* 1195 * Pick the current spr and splr values from the communication 1196 * area if possible. 1197 */ 1198 if (sc->sc_comm != NULL) { 1199 spr = sc->sc_comm[IFB_SHARED_TERM8_SPR >> 2]; 1200 splr = sc->sc_comm[IFB_SHARED_TERM8_SPLR >> 2]; 1201 } else { 1202 /* supposedly sane defaults */ 1203 spr = 0x54ff0303; 1204 splr = 0x5c0000ff; 1205 } 1206 1207 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x00400016); 1208 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5b000002); 1209 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5a000000); 1210 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, spr); 1211 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, splr); 1212 1213 ifb_rop_common(sc, reg, sx, sy, dx, dy, w, h, rop, planemask); 1214 1215 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5a000001); 1216 bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5b000001); 1217 } 1218 1219 int 1220 ifb_rop_wait(struct ifb_softc *sc) 1221 { 1222 int i; 1223 1224 for (i = 1000000; i != 0; i--) { 1225 if (bus_space_read_4(sc->sc_mem_t, sc->sc_reg_h, 1226 IFB_REG_STATUS) & IFB_REG_STATUS_DONE) 1227 break; 1228 DELAY(1); 1229 } 1230 1231 return i; 1232 } 1233 1234 int 1235 ifb_do_cursor(struct rasops_info *ri) 1236 { 1237 struct ifb_softc *sc = ri->ri_hw; 1238 int y, x; 1239 1240 y = ri->ri_yorigin + ri->ri_crow * ri->ri_font->fontheight; 1241 x = ri->ri_xorigin + ri->ri_ccol * ri->ri_font->fontwidth; 1242 1243 ifb_rop(sc, x, y, x, y, ri->ri_font->fontwidth, ri->ri_font->fontheight, 1244 IFB_ROP_XOR, IFB_PIXELMASK); 1245 ifb_rop_wait(sc); 1246 1247 return 0; 1248 } 1249